From: Ciro Santilli <ciro.santilli@arm.com>
Date: Mon, 30 Sep 2019 15:52:32 +0000 (+0100)
Subject: kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR
X-Git-Tag: v19.0.0.0~472
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a00953c0a7c80ac68003546a50b6556975720235;p=gem5.git

kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR

Those registers are 32-bit instead of 64 in the KVM API.

The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains:

    0x6020 0000 0010 00d4 FPSR        32  fp_regs.fpsr
    0x6020 0000 0010 00d5 FPCR        32  fp_regs.fpcr

The register itself is 64-bit in the ARM manual, but the top 32 are
RES0.

This fixes the following error when running ARM KVM early in the
simulation:

panic: KVM: Failed to set register (0x60300000001000d4) value
(errno: 22)

Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 3757e2602..5a843fcd5 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, 2017 ARM Limited
+ * Copyright (c) 2015, 2017, 2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -109,8 +109,8 @@ const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = {
     MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
     MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
     MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
-    MiscRegInfo(INT_REG(fp_regs.fpsr), MISCREG_FPSR, "FPSR"),
-    MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"),
+    MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"),
+    MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"),
 };
 
 const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = {