From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 May 2021 13:50:12 +0000 (+0000)
Subject: set fake PLL Master Cell directions explicitly
X-Git-Tag: LS180_RC3~41
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a020e116fb1d0b0405d6bb58383c7cbe176ba9d4;p=soclayout.git

set fake PLL Master Cell directions explicitly
---

diff --git a/experiments9/pll.py b/experiments9/pll.py
index ec31755..68a3bf6 100644
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -226,6 +226,14 @@ def _load():
             'out_v': Net.create(cell, 'out_v'),
         }
 
+        # set net directions
+        nets['ref'].setDirection( Net.Direction.IN )
+        nets['a0'].setDirection( Net.Direction.IN )
+        nets['a1'].setDirection( Net.Direction.IN )
+        nets['div_out_test'].setDirection( Net.Direction.OUT )
+        nets['vco_test_ana'].setDirection( Net.Direction.OUT )
+        nets['out_v'].setDirection( Net.Direction.OUT )
+
         # create series of stepped pins
         x = space*20
         wid = space