From: Gene Wu <Gene.Wu@arm.com>
Date: Mon, 23 Aug 2010 16:18:41 +0000 (-0500)
Subject: ARM: Implement DBG instruction that doesn't do much for now.
X-Git-Tag: stable_2012_02_02~882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a02d82f9f8cd4fb826e294bbb333ca20cb5533de;p=gem5.git

ARM: Implement DBG instruction that doesn't do much for now.
---

diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index b1818adf0..fccfe2897 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -166,7 +166,7 @@ def format Thumb32BranchesAndMiscCtrl() {{
                                                   ((enable ? 1 : 0) << 9);
                             return new Cps(machInst, mods);
                         } else if ((op2 & 0xf0) == 0xf0) {
-                            return new WarnUnimplemented("dbg", machInst);
+                            return new Dbg(machInst);
                         } else {
                             switch (op2) {
                               case 0x0:
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 33197eaec..120372603 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -708,6 +708,15 @@ let {{
     decoder_output += BasicConstructor.subst(dmbIop)
     exec_output += PredOpExecute.subst(dmbIop)
 
+    dbgCode = '''
+    '''
+    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
+                             {"code": dbgCode,
+                               "predicate_test": predicateTest})
+    header_output += BasicDeclare.subst(dbgIop)
+    decoder_output += BasicConstructor.subst(dbgIop)
+    exec_output += PredOpExecute.subst(dbgIop)
+
     cpsCode = '''
     uint32_t mode = bits(imm, 4, 0);
     uint32_t f = bits(imm, 5);