From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 6 Jul 2020 10:45:53 +0000 (+0200)
Subject: Fix formal support in FHDLTestCase
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a04306c07c8f236ff2b4facc7ccd093f36ac051a;p=gram.git

Fix formal support in FHDLTestCase
---

diff --git a/gram/test/utils.py b/gram/test/utils.py
index 6b4ad4c..6712429 100644
--- a/gram/test/utils.py
+++ b/gram/test/utils.py
@@ -92,7 +92,6 @@ class FHDLTestCase(unittest.TestCase):
         """).format(
             mode=mode,
             depth=depth,
-            script=script,
             rtlil=rtlil.convert(Fragment.get(spec, platform="formal"))
         )
         with subprocess.Popen([require_tool("sby"), "-f", "-d", spec_name],