From: David Shah <dave@ds0.me>
Date: Sat, 4 May 2019 16:27:21 +0000 (+0100)
Subject: vexriscv: Fix some floating signals
X-Git-Tag: 24jan2021_ls180~1239^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a048ba47c4db99b54fcee7bf994422c1d9308d9e;p=litex.git

vexriscv: Fix some floating signals

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index e40a2d38..de30de8d 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -126,6 +126,9 @@ class VexRiscv(Module, AutoCSR):
                 i_dBusWishbone_ERR=dbus.err)
 
         if "linux" in variant:
+            # Tie zero to prevent 1'bx here
+            self.cpu_params["i_softwareInterrupt"] = 0
+            self.cpu_params["i_externalInterruptS"] = 0
             self.add_timer()
 
         if "debug" in variant: