From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 24 Aug 2019 01:15:24 +0000 (-0700)
Subject: Do not allow Q of last cell of variable length SRL to be (* keep *)
X-Git-Tag: working-ls180~1085^2~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a048fc93e8cf187b28bd5ed924643671b9314678;p=yosys.git

Do not allow Q of last cell of variable length SRL to be (* keep *)
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index 76134de1a..cfa1cacfb 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -176,6 +176,7 @@ endcode
 match first
 	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
 	select !first->has_keep_attr()
+	select !port(first, \Q)[0].wire->get_bool_attribute(\keep)
 	slice idx GetSize(port(first, \Q))
 	select nusers(port(first, \Q)[idx]) <= 2
 	index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]