From: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
Date: Sat, 12 Feb 2011 00:29:35 +0000 (-0600)
Subject: O3: Fix pipeline restart when a table walk completes in the fetch stage.
X-Git-Tag: stable_2012_02_02~553^2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a05032f4df8be28c0ceaefba03114f3e7a5f6ab4;p=gem5.git

O3: Fix pipeline restart when a table walk completes in the fetch stage.

When a table walk is initiated by the fetch stage, the CPU can
potentially move to the idle state and never wake up.

The fetch stage must call cpu->wakeCPU() when a translation completes
(in finishTranslation()).
---

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d0c83d586..2e4e4819e 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -604,6 +604,9 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
     ThreadID tid = mem_req->threadId();
     Addr block_PC = mem_req->getVaddr();
 
+    // Wake up CPU if it was idle
+    cpu->wakeCPU();
+
     // If translation was successful, attempt to read the icache block.
     if (fault == NoFault) {
         // Build packet here.
@@ -654,6 +657,9 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
         instruction->fault = fault;
         wroteToTimeBuffer = true;
 
+        DPRINTF(Activity, "Activity this cycle.\n");
+        cpu->activityThisCycle();
+
         fetchStatus[tid] = TrapPending;
 
         DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);