From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Apr 2019 11:09:25 +0000 (+0100)
Subject: moo? added an option to stop buffer register from being used in BufferedPipeline
X-Git-Tag: ls180-24jan2020~1313
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a06c6a65b468eded314544fb49eb1ac4365e3c3c;p=ieee754fpu.git

moo? added an option to stop buffer register from being used in BufferedPipeline
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 11fee068..590773a8 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -568,9 +568,10 @@ class BufferedPipeline(ControlBase):
         input may begin to be processed and transferred directly to output.
 
     """
-    def __init__(self, stage, stage_ctl=False):
+    def __init__(self, stage, stage_ctl=False, buffermode=True):
         ControlBase.__init__(self, stage_ctl=stage_ctl)
         self.stage = stage
+        self.buffermode = buffermode
 
         # set up the input and output data
         self.p.i_data = stage.ispec() # input type
@@ -581,7 +582,8 @@ class BufferedPipeline(ControlBase):
         self.m = ControlBase._elaborate(self, platform)
 
         result = self.stage.ospec()
-        r_data = self.stage.ospec()
+        if self.buffermode:
+            r_data = self.stage.ospec()
         if hasattr(self.stage, "setup"):
             self.stage.setup(self.m, self.p.i_data)
 
@@ -599,9 +601,10 @@ class BufferedPipeline(ControlBase):
         # store result of processing in combinatorial temporary
         self.m.d.comb += eq(result, self.stage.process(self.p.i_data))
 
-        # if not in stall condition, update the temporary register
-        with self.m.If(self.p.o_ready): # not stalled
-            self.m.d.sync += eq(r_data, result) # update buffer
+        if self.buffermode:
+            # if not in stall condition, update the temporary register
+            with self.m.If(self.p.o_ready): # not stalled
+                self.m.d.sync += eq(r_data, result) # update buffer
 
         with self.m.If(n_i_ready): # next stage is ready
             with self.m.If(self.p._o_ready): # not stalled
@@ -609,9 +612,10 @@ class BufferedPipeline(ControlBase):
                 self.m.d.sync += [self.n.o_valid.eq(p_i_valid),
                                   eq(self.n.o_data, result), # update output
                             ]
-            with self.m.Else(): # p.o_ready is false, and something in buffer
-                # Flush the [already processed] buffer to the output port.
-                self.m.d.sync += [self.n.o_valid.eq(1),     # reg empty
+            if self.buffermode:
+                with self.m.Else(): # p.o_ready is false, and data in buffer
+                    # Flush the [already processed] buffer to the output port.
+                    self.m.d.sync += [self.n.o_valid.eq(1),  # reg empty
                                   eq(self.n.o_data, r_data), # flush buffer
                                   self.p._o_ready.eq(1),     # clear stall
                             ]