From: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Thu, 1 Jul 2021 13:49:17 +0000 (+0200)
Subject: examples/sdram_soc: reduce L1 sizes to 1KB to meet timing.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a08c426f1b4c07c8530c3c7e41f1f246d7f3b871;p=lambdasoc.git

examples/sdram_soc: reduce L1 sizes to 1KB to meet timing.
---

diff --git a/examples/sdram_soc.py b/examples/sdram_soc.py
index bbe68eb..d3f5dcb 100644
--- a/examples/sdram_soc.py
+++ b/examples/sdram_soc.py
@@ -32,9 +32,9 @@ class SDRAMSoC(CPUSoC, Elaboratable):
 
         self.cpu = MinervaCPU(
             reset_address=reset_addr,
-            with_icache=True, icache_nlines=128, icache_nwords=4, icache_nways=1,
+            with_icache=True, icache_nlines=64, icache_nwords=4, icache_nways=1,
                               icache_base=sdram_addr, icache_limit=sdram_addr + sdram_core.size,
-            with_dcache=True, dcache_nlines=128, dcache_nwords=4, dcache_nways=1,
+            with_dcache=True, dcache_nlines=64, dcache_nwords=4, dcache_nways=1,
                               dcache_base=sdram_addr, dcache_limit=sdram_addr + sdram_core.size,
             with_muldiv=True,
         )