From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Aug 2019 01:35:15 +0000 (+0100)
Subject: remove more redundant modules
X-Git-Tag: ls180-24jan2020~572
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0a67c0e5476908611d76a1f218540fe4cdfe069;p=ieee754fpu.git

remove more redundant modules
---

diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py
index 204ef32e..0e9f0321 100644
--- a/src/ieee754/fclass/pipeline.py
+++ b/src/ieee754/fclass/pipeline.py
@@ -1,21 +1,9 @@
 # IEEE754 FCLASS Module
 # Copyright (C) 2019 Luke Kenneth Casson Leighon <lkcl@lkcl.net>
 
-
-from nmigen import Module, Signal, Elaboratable
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
-
-from ieee754.fpcommon.basedata import FPBaseData
-from ieee754.fpcommon.pack import FPPackData
-
-
-from ieee754.fpcommon.fpbase import FPState, FPNumBase
-from ieee754.fpcommon.getop import FPPipeContext
-
-from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.fpbase import FPNumBase
 from ieee754.fclass.fclass import FPClassMod
 from ieee754.pipeline import PipelineSpec, DynamicPipe
 
diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 2cc0b087..7ec367bc 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -8,22 +8,10 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 import sys
 import functools
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.basedata import FPBaseData
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
-
-
-from nmigen import Module, Signal, Elaboratable
-from math import log
-
-from ieee754.fpcommon.getop import FPPipeContext
-
 from ieee754.pipeline import PipelineSpec, DynamicPipe
 
 from ieee754.fcvt.float2int import FPCVTFloatToIntMod
@@ -32,6 +20,8 @@ from ieee754.fcvt.upsize import FPCVTUpConvertMod
 from ieee754.fcvt.downsize import FPCVTDownConvertMod
 
 
+# not used, yet
+# from nmigen import Signal
 class SignedOp:
     def __init__(self):
         self.signed = Signal(reset_less=True)
diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 43247417..a1f8f21a 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -38,17 +38,9 @@ RoundMod, FPAddStage0Mod etc.
 
 """
 
-from nmigen import Module
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
-from nmutil.multipipe import CombMuxOutPipe
-from nmutil.multipipe import PriorityCombMuxInPipe
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.basedata import FPBaseData
-from ieee754.fpcommon.denorm import FPSCData
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from ieee754.fpadd.specialcases import FPAddSpecialCasesDeNorm
 from ieee754.fpadd.addstages import FPAddAlignSingleAdd
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 939447ac..42f7d1b0 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -66,10 +66,7 @@ even 8 is starting to get alarmingly high.
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.basedata import FPBaseData
-from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.fpbase import FPFormat
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index 82b881ca..4be6b0b5 100644
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -40,18 +40,12 @@ in #60: http://bugs.libre-riscv.org/show_bug.cgi?id=60
 
 """
 
-from nmigen import Module
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.basedata import FPBaseData
-from ieee754.fpcommon.denorm import FPSCData
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
-from .specialcases import FPMulSpecialCasesDeNorm
-from .mulstages import FPMulStages
+from ieee754.fpmul.specialcases import FPMulSpecialCasesDeNorm
+from ieee754.fpmul.mulstages import FPMulStages
 from ieee754.pipeline import PipelineSpec