From: Carl Love Date: Tue, 22 Nov 2016 16:49:02 +0000 (+0000) Subject: rs6000-c.c: Add built-in support for vector compare equal and vector compare not... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0af8668dcfac575d5c0f426d2dfac76d5a1490a;p=gcc.git rs6000-c.c: Add built-in support for vector compare equal and vector compare not equal. gcc/ChangeLog: 2016-11-21 Carl Love * config/rs6000/rs6000-c.c: Add built-in support for vector compare equal and vector compare not equal. The vector compares take two arguments of type vector bool char, vector bool short, vector bool int, vector bool long long with the same return type. * doc/extend.texi: Update built-in documentation file for the new powerpc built-ins. gcc/testsuite/ChangeLog: 2016-11-21 Carl Love * gcc.target/powerpc/builtins-3.c: New file to test the new built-ins for vector compare equal and vector compare not equal. From-SVN: r242706 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b19a3005423..a81c423f477 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-11-22 Carl Love + + * config/rs6000/rs6000-c.c: Add built-in support for vector compare + equal and vector compare not equal. The vector compares take two + arguments of type vector bool char, vector bool short, vector bool int, + vector bool long long with the same return type. + * doc/extend.texi: Update built-in documentation file for the new + powerpc built-ins. + 2016-11-22 Uros Bizjak * Makefile.in ($(lang_checks_parallelized)): Fix detection diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 4bba2934e1d..4f332d71735 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1107,14 +1107,22 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, @@ -4485,6 +4493,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, + RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, @@ -4508,7 +4519,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - + { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, + RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED, diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 4dcc7f6b555..ca469186650 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -15652,6 +15652,9 @@ vector float vec_ceil (vector float); vector signed int vec_cmpb (vector float, vector float); +vector bool char vec_cmpeq (vector bool char, vector bool char); +vector bool short vec_cmpeq (vector bool short, vector bool short); +vector bool int vec_cmpeq (vector bool int, vector bool int); vector bool char vec_cmpeq (vector signed char, vector signed char); vector bool char vec_cmpeq (vector unsigned char, vector unsigned char); vector bool short vec_cmpeq (vector signed short, vector signed short); @@ -17568,6 +17571,8 @@ int vec_any_lt (vector unsigned long long, vector unsigned long long); int vec_any_ne (vector long long, vector long long); int vec_any_ne (vector unsigned long long, vector unsigned long long); +vector bool long long vec_cmpeq (vector bool long long, vector bool long long); + vector long long vec_eqv (vector long long, vector long long); vector long long vec_eqv (vector bool long long, vector long long); vector long long vec_eqv (vector long long, vector bool long long); @@ -17901,6 +17906,11 @@ If the ISA 3.0 instruction set additions (@option{-mcpu=power9}) are available: @smallexample +vector bool char vec_cmpne (vector bool char, vector bool char); +vector bool short vec_cmpne (vector bool short, vector bool short); +vector bool int vec_cmpne (vector bool int, vector bool int); +vector bool long long vec_cmpne (vector bool long long, vector bool long long); + vector long long vec_vctz (vector long long); vector unsigned long long vec_vctz (vector unsigned long long); vector int vec_vctz (vector int); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 55d20c3e894..e6c41c4d855 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-11-22 Carl Love + + * gcc.target/powerpc/builtins-3.c: New file to test the new + built-ins for vector compare equal and vector compare not equal. + 2016-11-22 Janus Weil PR fortran/78443 diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c new file mode 100644 index 00000000000..8d4b63d806d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c @@ -0,0 +1,68 @@ +#include + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +vector bool char +test_eq_char (vector bool char x, vector bool char y) +{ + return vec_cmpeq (x, y); +} + +vector bool short +test_eq_short (vector bool short x, vector bool short y) +{ + return vec_cmpeq (x, y); +} + +vector bool int +test_eq_int (vector bool int x, vector bool int y) +{ + return vec_cmpeq (x, y); +} + +vector bool long +test_eq_long (vector bool long x, vector bool long y) +{ + return vec_cmpeq (x, y); +} + +vector bool char +test_ne_char (vector bool char x, vector bool char y) +{ + return vec_cmpne (x, y); +} + +vector bool short +test_ne_short (vector bool short x, vector bool short y) +{ + return vec_cmpne (x, y); +} + +vector bool int +test_ne_int (vector bool int x, vector bool int y) +{ + return vec_cmpne (x, y); +} + +vector bool long +test_ne_long (vector bool long x, vector bool long y) +{ + return vec_cmpne (x, y); +} + +/* Note: vec_cmpne is implemented as vcmpeq and then NOT'ed + using the xxlnor instruction. + + Expected test results: + test_eq_char 1 vcmpeq inst + test_eq_short 1 vcmpeq inst + test_eq_int 1 vcmpeq inst + test_eq_long 1 vcmpeq inst + test_ne_char 1 vcmpeq, 1 xxlnor inst + test_ne_short 1 vcmpeq, 1 xxlnor inst + test_ne_int 1 vcmpeq, 1 xxlnor inst + test_ne_long 1 vcmpeq, 1 xxlnor inst */ + +/* { dg-final { scan-assembler-times "vcmpeq" 8 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 4 } } */