From: lkcl <lkcl@web>
Date: Mon, 14 Dec 2020 01:51:34 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1330
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0b27f7dfdea12222999aefa20cf2037c1c5afe4;p=libreriscv.git

---

diff --git a/openpower/sv/example_dep_matrices.mdwn b/openpower/sv/example_dep_matrices.mdwn
index 3a33c42c9..554d27e56 100644
--- a/openpower/sv/example_dep_matrices.mdwn
+++ b/openpower/sv/example_dep_matrices.mdwn
@@ -19,3 +19,7 @@ See <https://bugs.libre-soc.org/show_bug.cgi?id=213#c83>
 |S\_LOGIC1  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
 |S\_LOGIC2  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
 
+Register allocation associated with this DM layout: Vectors may *only* be allocated to Vector FPs if RA%4 == RB%4
+== RT%4 and all reg numbers are over 32.  otherwise they are allocated
+to *scalar* FUs which has significantly less computational resources
+but far greater crossbar routing.