From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 7 Jun 2019 09:46:16 +0000 (+0200)
Subject: Cleanup tux3-implicit_named_connection
X-Git-Tag: yosys-0.9~82^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0b57f2a6ffae3b5770e38bf5a9af0df50db8522;p=yosys.git

Cleanup tux3-implicit_named_connection

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2fffc7536..6d3afed0e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -154,7 +154,7 @@ struct specify_rise_fall {
 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
-%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list named_port
+%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv
new file mode 100644
index 000000000..8b0a6f386
--- /dev/null
+++ b/tests/simple/implicit_ports.sv
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+	assign cout = cin;
+	assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+	wire cin = 1;
+	alu alu (
+		.a(a),
+		.b, // Implicit connection is equivalent to .b(b)
+		.cin(), // Explicitely unconnected
+		.cout(cout),
+		.result(alu_result)
+	);
+endmodule
diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv
deleted file mode 100644
index 6a766bd51..000000000
--- a/tests/various/implicit_ports.sv
+++ /dev/null
@@ -1,19 +0,0 @@
-// Test implicit port connections
-module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
-	assign cout = cin;
-	assign result = a + b;
-endmodule
-
-module named_ports(output [2:0] alu_result, output cout);
-	wire [2:0] a = 3'b010, b = 3'b100;
-	wire cin = 1;
-
-	alu alu (
-		.a(a),
-		.b, // Implicit connection is equivalent to .b(b)
-		.cin(), // Explicitely unconnected
-		.cout(cout),
-		.result(alu_result)
-	);
-endmodule
-
diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys
deleted file mode 100644
index 7b4764921..000000000
--- a/tests/various/implicit_ports.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog -sv implicit_ports.sv
-proc; opt
-
-flatten
-select -module named_ports
-
-sat -verify -prove alu_result 6
-sat -verify -set-all-undef cout