From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 Mar 2019 10:16:38 +0000 (+0000)
Subject: add ilang generation of ltbufpipe
X-Git-Tag: ls180-24jan2020~1534
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0ba6e16a0b7fa6e906655d347791338cab41c32;p=ieee754fpu.git

add ilang generation of ltbufpipe
---

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index be472c43..665da43f 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -572,4 +572,8 @@ if __name__ == '__main__':
     dut = ExampleLTBufferedPipeDerived()
     test = Test5(dut, test6_resultfn)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd")
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_ltbufpipe10.il", "w") as f:
+        f.write(vl)
+