From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 8 May 2016 04:13:47 +0000 (-0700)
Subject: Added simulation timescale declaration
X-Git-Tag: yosys-0.7~226^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0c19aae55d878576c7481a6a4a5d10ba98c5224;p=yosys.git

Added simulation timescale declaration
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 6cf29fe6e..da3704638 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -1,3 +1,5 @@
+`timescale 1ns/1ps;
+
 module GP_2LUT(input IN0, IN1, output OUT);
 	parameter [3:0] INIT = 0;
 	assign OUT = INIT[{IN1, IN0}];