From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 2 Jul 2018 22:19:02 +0000 (+0100)
Subject: wrong test changed, uart_tx being set to 1, must test iocell0=1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0c379ccbc68f1cd0b06a26f8b49e74630a785eb;p=pinmux.git

wrong test changed, uart_tx being set to 1, must test iocell0=1
---

diff --git a/src/test_bsv/tests/test_pinmux.py b/src/test_bsv/tests/test_pinmux.py
index b226eb4..e016ac9 100644
--- a/src/test_bsv/tests/test_pinmux.py
+++ b/src/test_bsv/tests/test_pinmux.py
@@ -86,7 +86,7 @@ def pinmux_basic_test(dut):
 
     yield Timer(2)
 
-    if dut.iocell_side_io0_cell_out != 0:
+    if dut.iocell_side_io0_cell_out != 1:
         raise TestFailure(
             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
             str(dut.iocell_side_io0_cell_out))