From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Apr 2021 08:48:37 +0000 (+0100)
Subject: add icachemmu option to ISACaller
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0cd3943c6768c4676d39e821f58269d15e76596;p=soc.git

add icachemmu option to ISACaller
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index ba24f48f..315db251 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -424,7 +424,8 @@ class ISACaller:
                  disassembly=None,
                  initial_pc=0,
                  bigendian=False,
-                 mmu=False):
+                 mmu=False,
+                 icachemmu=False):
 
         self.bigendian = bigendian
         self.halted = False
@@ -472,7 +473,8 @@ class ISACaller:
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
         if mmu:
             self.mem = RADIX(self.mem, self)
-            self.imem = RADIX(self.imem, self)
+            if icachemmu:
+                self.imem = RADIX(self.imem, self)
         self.pc = PC()
 
         # TODO, needed here: