From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 21 Jan 2023 18:58:22 +0000 (+0300)
Subject: power_insn: hack CR assembly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0cd87f428b56cb125b9480c308e0e4b98278b1f;p=openpower-isa.git

power_insn: hack CR assembly
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index aad06c38..df7bb4a9 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -2653,9 +2653,6 @@ class SpecifierFFPR(SpecifierPredicate):
         if self.record.svp64.mode is _SVMode.CROP:
             if self.mode == "pr":
                 raise ValueError("crop: 'pr' mode not supported")
-            if (self.record.svp64.extra_CR_3bit and
-                    (self.pred.mode is not _SVP64PredMode.RC1)):
-                raise ValueError("3-bit CRs only support RC1/~RC1 BO")
 
     def assemble(self, insn):
         selector = insn.select(record=self.record)
@@ -2663,9 +2660,12 @@ class SpecifierFFPR(SpecifierPredicate):
             raise ValueError("cannot override mode")
         if self.record.svp64.mode is _SVMode.CROP:
             selector.mode.sel = 0b10
-            selector.inv = self.pred.inv
-            if not self.record.svp64.extra_CR_3bit:
-                selector.CR = self.pred.state
+            # HACK: please finally provide correct logic for CRs.
+            if self.pred in (_SVP64Pred.RC1, _SVP64Pred.RC1_N):
+                selector.mode[2] = (self.pred is _SVP64Pred.RC1_N)
+            else:
+                selector.mode[2] = self.pred.inv
+                selector.mode[3, 4] = self.pred.state
         else:
             selector.mode.sel = 0b01 if self.mode == "ff" else 0b11
             selector.inv = self.pred.inv