From: whitequark <cz@m-labs.hk>
Date: Sat, 21 Sep 2019 06:53:39 +0000 (+0000)
Subject: lib.fifo: update docs. NFC.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0d343fde0032ea24b6886dffc5c2cec153285dd;p=nmigen.git

lib.fifo: update docs. NFC.
---

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index 1ce9e8c..da7023c 100644
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -240,7 +240,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
     does not use asynchronous memory reads, which are incompatible with FPGA block RAMs.
 
     In exchange, the latency betw_enen an entry being written to an empty queue and that entry
-    becoming available on the output is increased to one cycle.
+    becoming available on the output is increased by one cycle compared to :class:`SyncFIFO`.
     """.strip(),
     parameters="""
     fwft : bool
@@ -404,7 +404,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
     on the output, improving timing in case of block RAM that has large clock-to-output delay.
 
     In exchange, the latency between an entry being written to an empty queue and that entry
-    becoming available on the output is increased to one cycle.
+    becoming available on the output is increased by one cycle compared to :class:`AsyncFIFO`.
     """.strip(),
     parameters="""
     r_domain : str