From: Gabriel Somlo Date: Thu, 12 Dec 2019 14:02:47 +0000 (-0500) Subject: soc_core: additional CSR safety assertions X-Git-Tag: 24jan2021_ls180~810^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0dad1b071e61b707744552c7fbf266dd8deb447;p=litex.git soc_core: additional CSR safety assertions Since csr_data_width=64 has probably never worked properly, remove it as one of the possible options (to be fixed and re-added later). Add csr_data_width=16, which has been tested and does work. Additionally, ensure csr_data_width <= csr_alignment (we should not attempt to create (sub)registers larger than the CPU's native word size or XLen). Signed-off-by: Gabriel Somlo --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index ca670ff0..63c1f8ef 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -137,7 +137,7 @@ class SoCCore(Module): self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size - assert csr_data_width in [8, 32, 64] + assert csr_data_width in [8, 16, 32] self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width @@ -257,6 +257,7 @@ class SoCCore(Module): csr_alignment = max(csr_alignment, self.cpu.data_width) self.config["CSR_DATA_WIDTH"] = csr_data_width self.config["CSR_ALIGNMENT"] = csr_alignment + assert csr_data_width <= csr_alignment self.csr_data_width = csr_data_width self.csr_alignment = csr_alignment if with_wishbone: