From: Luke Kenneth Casson Leighton Date: Mon, 22 Jul 2019 01:20:25 +0000 (+0100) Subject: compare_rhs is a multi-bit value (cant use bool()) X-Git-Tag: ls180-24jan2020~788 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0e0d0b1163b7a9531eaf0f32b7afd0efb32f339;p=ieee754fpu.git compare_rhs is a multi-bit value (cant use bool()) --- diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index da1be3ac..547af3ce 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -376,19 +376,18 @@ class DivPipeCoreCalculateStage(Elaboratable): bit_value ^= pass_flags[j] m.d.comb += next_bits.part(i, 1).eq(bit_value) - # XXX using a list to accumulate the bits and then using bool - # is IMPORTANT. if done using |= it results in a chain of OR gates. - l = [] # next_compare_rhs + # merge/select multi-bit trial_compare_rhs_values, to go + # into compare_rhs. XXX (only one of these will succeed?) + next_compare_rhs = 0 for i in range(radix): next_flag = pass_flags[i + 1] if i + 1 < radix else 0 selected = Signal(name=f"selected_{i}", reset_less=True) m.d.comb += selected.eq(pass_flags[i] & ~next_flag) - l.append(Mux(selected, trial_compare_rhs_values[i], 0) - - # concatenate the list of Mux results together and OR them using - # the bool operator. - m.d.comb += self.o.compare_rhs.eq(Cat(*l).bool()) + next_compare_rhs |= Mux(selected, + trial_compare_rhs_values[i], + 0) + m.d.comb += self.o.compare_rhs.eq(next_compare_rhs) m.d.comb += self.o.root_times_radicand.eq(self.i.root_times_radicand + ((self.i.divisor_radicand * next_bits)