From: lkcl Date: Thu, 2 Jun 2022 16:54:32 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2008 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a0f7e411243e1eff7dfb80ff88fa966bbe336f0c;p=libreriscv.git --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 591afccdd..5ffc33a7d 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -38,7 +38,7 @@ Table of contents # Introduction -This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]]. +This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section. All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB and counting up as you move to the LSB end). All bit ranges are inclusive