From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Sep 2019 19:11:11 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7dsp
X-Git-Tag: working-ls180~1039^2~120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1123b095c54adb3a700aa33f98edf1dcee12ac2;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7dsp
---

a1123b095c54adb3a700aa33f98edf1dcee12ac2
diff --cc CHANGELOG
index 50c611b8d,890fad978..8d7dd3e19
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -39,11 -39,7 +39,12 @@@ Yosys 0.9 .. Yosys 0.9-de
      - Added "xilinx_srl" for Xilinx shift register extraction
      - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
      - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
+     - Added "-match-init" option to "dff2dffs" pass
 +    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
 +    - Added "xilinx_dsp" for Xilinx DSP packing
 +    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
 +    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
 +    - "synth_ice40 -dsp" to infer DSP blocks
  
  Yosys 0.8 .. Yosys 0.9
  ----------------------