From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 1 Jan 2020 15:24:30 +0000 (+0100)
Subject: Added a test case
X-Git-Tag: working-ls180~892^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1344ec06ead35a3b7933ee93b5757eeff2e5d4a;p=yosys.git

Added a test case
---

diff --git a/tests/arch/xilinx/bug1605.ys b/tests/arch/xilinx/bug1605.ys
new file mode 100644
index 000000000..4be659860
--- /dev/null
+++ b/tests/arch/xilinx/bug1605.ys
@@ -0,0 +1,19 @@
+read_verilog <<EOT
+module top(inout io);
+    wire in;
+    wire t;
+    wire o;
+
+    IOBUF IOBUF(
+      .I(in),
+      .T(t),
+      .IO(io),
+      .O(o)
+    );
+endmodule
+EOT
+
+synth_xilinx
+cd top
+select -assert-count 1 t:IOBUF
+select -assert-none t:* t:IOBUF %d