From: lkcl Date: Sat, 9 Apr 2022 14:53:29 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2824 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a139e7f825c933ab1ea422bb3a08b9bcc2f37a23;p=libreriscv.git --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 34de36b25..e5b353d60 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -380,9 +380,15 @@ Notes from Jacob: CR6-7 allows Scalar ops to refer to these without having to do Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*). +These mappings are part of the SVP64 Specification in exactly the same +way as X-Form, D-Form. New Scalar instructions added to the Power ISA +will need a corresponding SVP64 Mapping, which can be derived by-rote +from examining the Register "Profile" of the instruction. + There are two categories: Single and Twin Predication. Due to space considerations further subdivision of Single Predication -is based on whether the number of src operands is 2 or 3. +is based on whether the number of src operands is 2 or 3. With only +9 bits available some compromises have to be made. * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd). * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)