From: lkcl <lkcl@web>
Date: Sat, 20 Feb 2021 22:59:59 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~144
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1498e479969a23683b4767adaaba2364dc930db;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 71e9925ba..2f62b8ec5 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -140,9 +140,11 @@ unit tests:
 
 * GPR
 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
-* Condition Registers
+* Condition Registers.  see note below
 * FPR (if present)
 
+When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
+
 ## Increasing register file sizes
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.