From: lkcl <lkcl@web>
Date: Sun, 21 Aug 2022 20:54:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~797
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a14b43a86b95216f196e1b31224886145889ff8f;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 74b02f863..9e0460463 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -17,7 +17,14 @@ Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, which was designed
 primarily for vectors of arithmetic and logical operations. However
 if predicates may be bits of CR Fields it makes sense to extend
-Simple-V to cover CR Operations.
+Simple-V to cover CR Operations, especially given that Vectorised Rc=1
+may be processed by Vectorised CR Operations tbat usefully in turn
+may become Predicate Masks to yet more Vector operations, like so:
+
+    sv.cmpi/ew=8 *BA,*ra,0      # compare bytes against zero
+    sv.cmpi/ew=8 *BA2,*ra,13.   # and against newline
+    sv.cror PM.EQ,BA.EQ,BA2.EQ  # OR compares to create predicate mask
+    sv.st/sm=EQ/ew=8 ...        # store only nonzero/newline
 
 Element width however is clearly meaningless for a 4-bit
 collation of Conditions, EQ LT GE SO. Likewise, arithmetic saturation