From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 17 May 2021 15:33:31 +0000 (+0100)
Subject: update reg sort order in ISACaller
X-Git-Tag: xlen-bcd~603
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1698c4d20d224c32daab1e5f41dab53add1d262;p=openpower-isa.git

update reg sort order in ISACaller
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 763b0ace..2efb0ea2 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -52,8 +52,6 @@ special_sprs = {
 
 
 REG_SORT_ORDER = {
-    # TODO (lkcl): adjust other registers that should be in a particular order
-    # probably CA, CA32, and CR
     "FRT": 0,
     "FRA": 0,
     "FRB": 0,
@@ -64,16 +62,18 @@ REG_SORT_ORDER = {
     "RB": 0,
     "RC": 0,
     "RS": 0,
-    "CR": 0,
-    "LR": 0,
-    "CTR": 0,
-    "TAR": 0,
-    "CA": 0,
-    "CA32": 0,
-    "MSR": 0,
-    "SVSTATE": 0,
-
-    "overflow": 1, # should definitely be last
+
+    "LR": 1,
+    "CTR": 1,
+    "TAR": 1,
+    "MSR": 1,
+    "SVSTATE": 1,
+
+    "CR": 4,
+    "CA": 5,
+    "CA32": 6,
+
+    "overflow": 7, # should definitely be last
 }
 
 fregs = ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']