From: Jacob Lifshay Date: Fri, 5 Nov 2021 23:10:35 +0000 (-0700) Subject: add ternaryi X-Git-Tag: sv_maxu_works-initial~765 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a17a252e474d5d5bf34026c25a19682e3f2015c3;p=openpower-isa.git add ternaryi --- diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 8da5faab..1d0cd7ba 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -80,6 +80,7 @@ divduo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwuo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +ternaryi,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 ffadds,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdivs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsubs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index f1ba11ef..3baa6fdf 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -283,6 +283,10 @@ |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 | | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO | / | +# 1.6.34 TI-FORM + |0 |6 |11 |16 |21 |29 |31 | + | PO | RT | RA | RB | TII | XO |Rc | + # 1.6.28 Instruction Fields A (6) Field used by the tbegin. instruction to specify an @@ -824,6 +828,10 @@ and dcbtst instructions (see Section 4.3.2 of Book II). Formats: X + TII (21:28) + Field used by the ternaryi instruction as the + look-up table. + Formats: TI TO (6:10) Field used to specify the conditions on which to trap. The encoding is described in @@ -948,6 +956,9 @@ XO (27:30) Extended opcode field. Formats: MDS + XO (29:30) + Extended opcode field. + Formats: TI XO (29:31) Extended opcode field. Formats: DQ diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv new file mode 100644 index 00000000..8fa5c11c --- /dev/null +++ b/openpower/isatables/minor_5.csv @@ -0,0 +1,2 @@ +opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 +--------00-,ALU,OP_TERNARYI,RA,RB,CONST_TII,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternaryi,TI,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py index f579a75c..8fabeabc 100644 --- a/src/openpower/decoder/power_decoder.py +++ b/src/openpower/decoder/power_decoder.py @@ -734,6 +734,8 @@ def create_pdecode(name=None, col_subset=None, row_subset=None, opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]), Subdecoder(pattern=22, opcodes=get_csv("minor_22.csv"), opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]), + Subdecoder(pattern=5, opcodes=get_csv("minor_5.csv"), + opint=True, bitsel=(0, 11), suffix=None, subdecoders=[]), ] # FP 63L/H decoders. TODO: move mffsfamily to separate subdecoder diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index c6dd9efa..ec9ed77d 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -120,6 +120,7 @@ class Form(Enum): SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY + TI = 34 # ternaryi # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/ @@ -329,6 +330,7 @@ _insns = [ "subf", "subfc", "subfco", "subfe", "subfeo", "subfic", "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", + "ternaryi", "td", "tdi", "tlbie", "tlbiel", "tw", "twi", @@ -433,6 +435,7 @@ class MicrOp(Enum): OP_ADDG6S = 83 OP_CDTBCD = 84 OP_CBCDTD = 85 + OP_TERNARYI = 86 @unique @@ -475,6 +478,7 @@ class In3Sel(Enum): FRS = 3 FRC = 4 RC = 5 # for SVP64 bit-reverse LD/ST + CONST_TII = 6 # for ternaryi @unique