From: Luke Kenneth Casson Leighton Date: Tue, 8 Sep 2020 15:42:57 +0000 (+0000) Subject: new version of test_issuer.il X-Git-Tag: partial-core-ls180-gdsii~80 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a17ad389d0b80aab74f23b09df521ffc187f00d1;p=soclayout.git new version of test_issuer.il --- diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index ea4b287..42b446a 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -205,17 +205,17 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__imm + wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__imm_ok + wire width 1 input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__rc_ok + wire width 1 input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__oe_ok + wire width 1 input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -340,17 +340,17 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__imm$4 + wire width 64 output 26 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \alu_op__imm_data__imm_ok$5 + wire width 1 output 27 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 28 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__rc__rc_ok$7 + wire width 1 output 29 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 30 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__oe__oe_ok$9 + wire width 1 output 31 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 32 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -447,12 +447,7 @@ module \input end process $group_5 assign \xer_so$22 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" - switch { \alu_op__oe__oe_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" - case 1'1 - assign \xer_so$22 \xer_so - end + assign \xer_so$22 \xer_so sync init end process $group_6 @@ -463,12 +458,12 @@ module \input process $group_7 assign \alu_op__insn_type$2 7'0000000 assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5 1'0 + assign \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$5 1'0 assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__rc_ok$7 1'0 + assign \alu_op__rc__ok$7 1'0 assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__oe_ok$9 1'0 + assign \alu_op__oe__ok$9 1'0 assign \alu_op__invert_in$10 1'0 assign \alu_op__zero_a$11 1'0 assign \alu_op__invert_out$12 1'0 @@ -479,7 +474,7 @@ module \input assign \alu_op__is_signed$17 1'0 assign \alu_op__data_len$18 4'0000 assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } sync init end end @@ -578,17 +573,17 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__imm + wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__imm_ok + wire width 1 input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__rc_ok + wire width 1 input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__oe_ok + wire width 1 input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -713,17 +708,17 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__imm$4 + wire width 64 output 26 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \alu_op__imm_data__imm_ok$5 + wire width 1 output 27 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 28 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__rc__rc_ok$7 + wire width 1 output 29 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 30 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__oe__oe_ok$9 + wire width 1 output 31 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 32 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -803,14 +798,38 @@ module \main end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" wire width 64 \a_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + cell $eq $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $26 + end process $group_1 assign \a_i 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - switch { \is_32bit } + switch { \is_32bit $26 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - case 1'1 - assign \a_i { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } + case 2'-1 + assign \a_i \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + case 2'1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \alu_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + case 1'1 + assign \a_i { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + case + assign \a_i { { 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 } \ra [31:0] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:73" case assign \a_i \ra end @@ -818,14 +837,38 @@ module \main end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + cell $eq $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $28 + end process $group_2 assign \b_i 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - switch { \is_32bit } + switch { \is_32bit $28 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - case 1'1 - assign \b_i { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } + case 2'-1 + assign \b_i \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + case 2'1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \alu_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + case 1'1 + assign \b_i { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + case + assign \b_i { { 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 } \rb [31:0] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:73" case assign \b_i \rb end @@ -833,10 +876,10 @@ module \main end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" wire width 66 \add_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - cell $eq $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $31 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -844,12 +887,12 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $26 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - cell $eq $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $33 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -857,26 +900,26 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $28 + connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - cell $or $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $26 - connect \B $28 - connect \Y $30 + connect \A $30 + connect \B $32 + connect \Y $34 end process $group_3 assign \add_a 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch { $30 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch { $34 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" case 1'1 assign \add_a { 1'0 \a_i \xer_ca [0] } end @@ -884,10 +927,10 @@ module \main end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" wire width 66 \add_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - cell $eq $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $37 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -895,12 +938,12 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $32 + connect \Y $36 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - cell $eq $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $39 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -908,26 +951,26 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $34 + connect \Y $38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - cell $or $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 + connect \A $36 + connect \B $38 + connect \Y $40 end process $group_4 assign \add_b 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch { $36 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch { $40 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" case 1'1 assign \add_b { 1'0 \b_i 1'1 } end @@ -935,10 +978,10 @@ module \main end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" wire width 66 \add_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - cell $eq $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $43 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -946,12 +989,12 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $38 + connect \Y $42 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - cell $eq $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $45 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -959,27 +1002,27 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $40 + connect \Y $44 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - cell $or $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $38 - connect \B $40 - connect \Y $42 + connect \A $42 + connect \B $44 + connect \Y $46 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - wire width 67 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - wire width 67 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - cell $add $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + wire width 67 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + wire width 67 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $add $50 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -987,23 +1030,610 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $45 + connect \Y $49 end - connect $44 $45 + connect $48 $49 process $group_5 assign \add_o 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch { $42 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch { $46 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" case 1'1 - assign \add_o $44 [65:0] + assign \add_o $48 [65:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93" + wire width 64 \a_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire width 64 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + cell $not $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $51 + end + process $group_6 + assign \a_n 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \a_n $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + wire width 1 \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + cell $xor $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + cell $xor $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $53 + connect \B \rb [32] + connect \Y $55 + end + process $group_7 + assign \carry_32 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \carry_32 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" + wire width 1 \carry_64 + process $group_8 + assign \carry_64 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \carry_64 \add_o [65] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire width 1 \zerolo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire width 1 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire width 32 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $xor $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $reduce_bool $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A $59 + connect \Y $58 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $not $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $58 + connect \Y $57 + end + process $group_9 + assign \zerolo 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \zerolo $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" + wire width 1 \zerohi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + wire width 32 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $65 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $reduce_bool $67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A $65 + connect \Y $64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $not $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $64 + connect \Y $63 + end + process $group_10 + assign \zerohi 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \zerohi $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:94" + wire width 5 \tval + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B $69 + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire width 1 \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire width 1 \msb_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - wire width 1 $47 + wire width 1 $73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $eq $48 + cell $ne $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95" + wire width 1 \a_lt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + cell $not $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + cell $not $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $77 + end + process $group_11 + assign \tval 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + case 1'1 + assign \tval [2] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch { $73 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + case 1'1 + assign \tval { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:124" + case + assign \tval { \a_lt $77 1'0 \a_lt $75 } + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $79 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B $79 + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $mux $84 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $83 + end + process $group_12 + assign \msb_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" + case + assign \msb_a $83 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B $85 + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" + cell $mux $90 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $89 + end + process $group_13 + assign \msb_b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" + case + assign \msb_b $89 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B $91 + connect \Y $93 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + cell $ne $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" + cell $mux $98 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $97 + end + process $group_14 + assign \a_lt 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch { $95 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:124" + case + assign \a_lt $97 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:174" + wire width 8 \eqs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" + cell $reduce_or $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $99 + end + process $group_15 + assign \cr_a 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \cr_a [1:0] { \tval [2] \xer_so } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + switch { \alu_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + case 1'1 + assign \cr_a [3:2] \tval [4:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + case + assign \cr_a [3:2] \tval [1:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \cr_a { 1'0 $99 2'00 } + end + sync init + end + process $group_16 + assign \cr_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \cr_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \cr_a_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + cell $eq $102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -1011,12 +1641,12 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $47 + connect \Y $101 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $eq $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + cell $eq $104 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -1024,12 +1654,12 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $49 + connect \Y $103 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $eq $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $106 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -1037,89 +1667,85 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $51 + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:136" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - wire width 8 \eqs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:136" - cell $reduce_or $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + cell $reduce_or $108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $53 + connect \Y $107 end - process $group_6 + process $group_17 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - assign \o \add_o [64:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \o \add_o [64:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + switch { $101 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" case 1'1 assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + switch { $103 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" case 1'1 assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch { $105 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" case 1'1 assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 - assign \o [0] $53 + assign \o [0] $107 end sync init end - process $group_7 + process $group_18 assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 assign \o_ok 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:146" wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - cell $xor $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + cell $xor $110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -1127,88 +1753,88 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $55 + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - cell $xor $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + cell $xor $112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \add_o [33] - connect \B $55 - connect \Y $57 + connect \B $109 + connect \Y $111 end - process $group_8 + process $group_19 assign \ca 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \ca [0] \add_o [65] - assign \ca [1] $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + assign \ca [1] $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 end sync init end - process $group_9 + process $group_20 assign \xer_ca$20 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \xer_ca$20 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 end sync init end - process $group_10 + process $group_21 assign \xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \xer_ca_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" wire width 2 \ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $59 + wire width 1 $113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $60 + cell $xor $114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -1216,14 +1842,14 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $59 + connect \Y $113 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $61 + wire width 1 $115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $62 + wire width 1 $116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $63 + cell $xor $117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -1231,33 +1857,33 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $62 + connect \Y $116 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $64 + cell $not $118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $62 - connect \Y $61 + connect \A $116 + connect \Y $115 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $65 + wire width 1 $119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $66 + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $59 - connect \B $61 - connect \Y $65 + connect \A $113 + connect \B $115 + connect \Y $119 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $67 + wire width 1 $121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $68 + cell $xor $122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -1265,14 +1891,14 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $67 + connect \Y $121 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $69 + wire width 1 $123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $70 + wire width 1 $124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $71 + cell $xor $125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -1280,116 +1906,116 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $70 + connect \Y $124 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $72 + cell $not $126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $70 - connect \Y $69 + connect \A $124 + connect \Y $123 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $73 + wire width 1 $127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $74 + cell $and $128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $67 - connect \B $69 - connect \Y $73 + connect \A $121 + connect \B $123 + connect \Y $127 end - process $group_11 + process $group_22 assign \ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 - assign \ov [0] $65 - assign \ov [1] $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + assign \ov [0] $119 + assign \ov [1] $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 end sync init end - process $group_12 + process $group_23 assign \xer_ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \xer_ov \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 end sync init end - process $group_13 + process $group_24 assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 assign \xer_ov_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:175" wire width 8 \src1 - process $group_14 + process $group_25 assign \src1 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 assign \src1 \ra [7:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $130 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1397,12 +2023,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $75 + connect \Y $129 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $132 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1410,12 +2036,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $77 + connect \Y $131 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $134 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1423,12 +2049,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $79 + connect \Y $133 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $136 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1436,12 +2062,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $81 + connect \Y $135 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $138 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1449,12 +2075,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $83 + connect \Y $137 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $140 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1462,12 +2088,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $85 + connect \Y $139 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $142 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1475,12 +2101,12 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $87 + connect \Y $141 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" - cell $eq $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 1 $143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $144 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -1488,104 +2114,54 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $89 + connect \Y $143 end - process $group_15 + process $group_26 assign \eqs 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" attribute \nmigen.decoding "OP_CMP/10" case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" attribute \nmigen.decoding "OP_ADD/2" case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" attribute \nmigen.decoding "OP_EXTS/31" case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" attribute \nmigen.decoding "OP_CMPEQB/12" case 7'0001100 - assign \eqs [0] $75 - assign \eqs [1] $77 - assign \eqs [2] $79 - assign \eqs [3] $81 - assign \eqs [4] $83 - assign \eqs [5] $85 - assign \eqs [6] $87 - assign \eqs [7] $89 + assign \eqs [0] $129 + assign \eqs [1] $131 + assign \eqs [2] $133 + assign \eqs [3] $135 + assign \eqs [4] $137 + assign \eqs [5] $139 + assign \eqs [6] $141 + assign \eqs [7] $143 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:138" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:138" - cell $reduce_or $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $91 - end - process $group_16 - assign \cr_a 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \cr_a { 1'0 $91 2'00 } - end - sync init - end - process $group_17 - assign \cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \cr_a_ok 1'1 - end - sync init - end - process $group_18 + process $group_27 assign \xer_so$21 1'0 assign \xer_so$21 \xer_so sync init end - process $group_19 + process $group_28 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_20 + process $group_29 assign \alu_op__insn_type$2 7'0000000 assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5 1'0 + assign \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$5 1'0 assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__rc_ok$7 1'0 + assign \alu_op__rc__ok$7 1'0 assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__oe_ok$9 1'0 + assign \alu_op__oe__ok$9 1'0 assign \alu_op__invert_in$10 1'0 assign \alu_op__zero_a$11 1'0 assign \alu_op__invert_out$12 1'0 @@ -1596,16 +2172,16 @@ module \main assign \alu_op__is_signed$17 1'0 assign \alu_op__data_len$18 4'0000 assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" module \pipe1 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 2 \n_valid_o @@ -1709,29 +2285,29 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \alu_op__imm_data__imm + wire width 64 output 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$next + wire width 64 \alu_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \alu_op__imm_data__imm_ok + wire width 1 output 8 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$next + wire width 1 \alu_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 9 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \alu_op__rc__rc_ok + wire width 1 output 10 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$next + wire width 1 \alu_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 11 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \alu_op__oe__oe_ok + wire width 1 output 12 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$next + wire width 1 \alu_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 13 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -1912,17 +2488,17 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 37 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \alu_op__imm_data__imm$4 + wire width 64 input 38 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 39 \alu_op__imm_data__imm_ok$5 + wire width 1 input 39 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 40 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 41 \alu_op__rc__rc_ok$7 + wire width 1 input 41 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 42 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 43 \alu_op__oe__oe_ok$9 + wire width 1 input 43 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 44 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -2055,17 +2631,17 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__imm + wire width 64 \input_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__imm_data__imm_ok + wire width 1 \input_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__rc__rc_ok + wire width 1 \input_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__oe__oe_ok + wire width 1 \input_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -2190,17 +2766,17 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_alu_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__imm$25 + wire width 64 \input_alu_op__imm_data__data$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__imm_data__imm_ok$26 + wire width 1 \input_alu_op__imm_data__ok$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_alu_op__rc__rc$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__rc__rc_ok$28 + wire width 1 \input_alu_op__rc__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_alu_op__oe__oe$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__oe__oe_ok$30 + wire width 1 \input_alu_op__oe__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_alu_op__invert_in$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -2237,12 +2813,12 @@ module \pipe1 connect \muxid \input_muxid connect \alu_op__insn_type \input_alu_op__insn_type connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__imm_data__imm \input_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm_ok + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__rc_ok \input_alu_op__rc__rc_ok + connect \alu_op__rc__ok \input_alu_op__rc__ok connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__oe_ok \input_alu_op__oe__oe_ok + connect \alu_op__oe__ok \input_alu_op__oe__ok connect \alu_op__invert_in \input_alu_op__invert_in connect \alu_op__zero_a \input_alu_op__zero_a connect \alu_op__invert_out \input_alu_op__invert_out @@ -2260,12 +2836,12 @@ module \pipe1 connect \muxid$1 \input_muxid$22 connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__imm$4 \input_alu_op__imm_data__imm$25 - connect \alu_op__imm_data__imm_ok$5 \input_alu_op__imm_data__imm_ok$26 + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__rc__rc_ok$7 \input_alu_op__rc__rc_ok$28 + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__oe_ok$9 \input_alu_op__oe__oe_ok$30 + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 @@ -2373,17 +2949,17 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \main_alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__imm + wire width 64 \main_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__imm_data__imm_ok + wire width 1 \main_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__rc__rc_ok + wire width 1 \main_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__oe__oe_ok + wire width 1 \main_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -2508,17 +3084,17 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \main_alu_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__imm$48 + wire width 64 \main_alu_op__imm_data__data$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__imm_data__imm_ok$49 + wire width 1 \main_alu_op__imm_data__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_alu_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__rc__rc_ok$51 + wire width 1 \main_alu_op__rc__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_alu_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__oe__oe_ok$53 + wire width 1 \main_alu_op__oe__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_alu_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -2565,12 +3141,12 @@ module \pipe1 connect \muxid \main_muxid connect \alu_op__insn_type \main_alu_op__insn_type connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__imm_data__imm \main_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm_ok + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__rc_ok \main_alu_op__rc__rc_ok + connect \alu_op__rc__ok \main_alu_op__rc__ok connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__oe_ok \main_alu_op__oe__oe_ok + connect \alu_op__oe__ok \main_alu_op__oe__ok connect \alu_op__invert_in \main_alu_op__invert_in connect \alu_op__zero_a \main_alu_op__zero_a connect \alu_op__invert_out \main_alu_op__invert_out @@ -2588,12 +3164,12 @@ module \pipe1 connect \muxid$1 \main_muxid$45 connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__imm$4 \main_alu_op__imm_data__imm$48 - connect \alu_op__imm_data__imm_ok$5 \main_alu_op__imm_data__imm_ok$49 + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__rc__rc_ok$7 \main_alu_op__rc__rc_ok$51 + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__oe_ok$9 \main_alu_op__oe__oe_ok$53 + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 @@ -2622,12 +3198,12 @@ module \pipe1 process $group_1 assign \input_alu_op__insn_type 7'0000000 assign \input_alu_op__fn_unit 11'00000000000 - assign \input_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_alu_op__imm_data__imm_ok 1'0 + assign \input_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_alu_op__imm_data__ok 1'0 assign \input_alu_op__rc__rc 1'0 - assign \input_alu_op__rc__rc_ok 1'0 + assign \input_alu_op__rc__ok 1'0 assign \input_alu_op__oe__oe 1'0 - assign \input_alu_op__oe__oe_ok 1'0 + assign \input_alu_op__oe__ok 1'0 assign \input_alu_op__invert_in 1'0 assign \input_alu_op__zero_a 1'0 assign \input_alu_op__invert_out 1'0 @@ -2638,7 +3214,7 @@ module \pipe1 assign \input_alu_op__is_signed 1'0 assign \input_alu_op__data_len 4'0000 assign \input_alu_op__insn 32'00000000000000000000000000000000 - assign { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in { \input_alu_op__oe__oe_ok \input_alu_op__oe__oe } { \input_alu_op__rc__rc_ok \input_alu_op__rc__rc } { \input_alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm } \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } + assign { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in { \input_alu_op__oe__ok \input_alu_op__oe__oe } { \input_alu_op__rc__ok \input_alu_op__rc__rc } { \input_alu_op__imm_data__ok \input_alu_op__imm_data__data } \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } sync init end process $group_19 @@ -2669,12 +3245,12 @@ module \pipe1 process $group_24 assign \main_alu_op__insn_type 7'0000000 assign \main_alu_op__fn_unit 11'00000000000 - assign \main_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_alu_op__imm_data__imm_ok 1'0 + assign \main_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_alu_op__imm_data__ok 1'0 assign \main_alu_op__rc__rc 1'0 - assign \main_alu_op__rc__rc_ok 1'0 + assign \main_alu_op__rc__ok 1'0 assign \main_alu_op__oe__oe 1'0 - assign \main_alu_op__oe__oe_ok 1'0 + assign \main_alu_op__oe__ok 1'0 assign \main_alu_op__invert_in 1'0 assign \main_alu_op__zero_a 1'0 assign \main_alu_op__invert_out 1'0 @@ -2685,7 +3261,7 @@ module \pipe1 assign \main_alu_op__is_signed 1'0 assign \main_alu_op__data_len 4'0000 assign \main_alu_op__insn 32'00000000000000000000000000000000 - assign { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in { \main_alu_op__oe__oe_ok \main_alu_op__oe__oe } { \main_alu_op__rc__rc_ok \main_alu_op__rc__rc } { \main_alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm } \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 { \input_alu_op__oe__oe_ok$30 \input_alu_op__oe__oe$29 } { \input_alu_op__rc__rc_ok$28 \input_alu_op__rc__rc$27 } { \input_alu_op__imm_data__imm_ok$26 \input_alu_op__imm_data__imm$25 } \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + assign { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in { \main_alu_op__oe__ok \main_alu_op__oe__oe } { \main_alu_op__rc__ok \main_alu_op__rc__rc } { \main_alu_op__imm_data__ok \main_alu_op__imm_data__data } \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 { \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 } { \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 } { \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 } \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } sync init end process $group_42 @@ -2839,17 +3415,17 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_op__fn_unit$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$72 + wire width 64 \alu_op__imm_data__data$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$73 + wire width 1 \alu_op__imm_data__ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__rc__rc$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$75 + wire width 1 \alu_op__rc__ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__oe__oe$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$77 + wire width 1 \alu_op__oe__ok$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__invert_in$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -2877,12 +3453,12 @@ module \pipe1 process $group_50 assign \alu_op__insn_type$70 7'0000000 assign \alu_op__fn_unit$71 11'00000000000 - assign \alu_op__imm_data__imm$72 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$73 1'0 + assign \alu_op__imm_data__data$72 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$73 1'0 assign \alu_op__rc__rc$74 1'0 - assign \alu_op__rc__rc_ok$75 1'0 + assign \alu_op__rc__ok$75 1'0 assign \alu_op__oe__oe$76 1'0 - assign \alu_op__oe__oe_ok$77 1'0 + assign \alu_op__oe__ok$77 1'0 assign \alu_op__invert_in$78 1'0 assign \alu_op__zero_a$79 1'0 assign \alu_op__invert_out$80 1'0 @@ -2893,7 +3469,7 @@ module \pipe1 assign \alu_op__is_signed$85 1'0 assign \alu_op__data_len$86 4'0000 assign \alu_op__insn$87 32'00000000000000000000000000000000 - assign { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__oe_ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__rc_ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__imm_ok$73 \alu_op__imm_data__imm$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 { \main_alu_op__oe__oe_ok$53 \main_alu_op__oe__oe$52 } { \main_alu_op__rc__rc_ok$51 \main_alu_op__rc__rc$50 } { \main_alu_op__imm_data__imm_ok$49 \main_alu_op__imm_data__imm$48 } \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + assign { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 { \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 } { \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 } { \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 } \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -2992,12 +3568,12 @@ module \pipe1 process $group_80 assign \alu_op__insn_type$next \alu_op__insn_type assign \alu_op__fn_unit$next \alu_op__fn_unit - assign \alu_op__imm_data__imm$next \alu_op__imm_data__imm - assign \alu_op__imm_data__imm_ok$next \alu_op__imm_data__imm_ok + assign \alu_op__imm_data__data$next \alu_op__imm_data__data + assign \alu_op__imm_data__ok$next \alu_op__imm_data__ok assign \alu_op__rc__rc$next \alu_op__rc__rc - assign \alu_op__rc__rc_ok$next \alu_op__rc__rc_ok + assign \alu_op__rc__ok$next \alu_op__rc__ok assign \alu_op__oe__oe$next \alu_op__oe__oe - assign \alu_op__oe__oe_ok$next \alu_op__oe__oe_ok + assign \alu_op__oe__ok$next \alu_op__oe__ok assign \alu_op__invert_in$next \alu_op__invert_in assign \alu_op__zero_a$next \alu_op__zero_a assign \alu_op__invert_out$next \alu_op__invert_out @@ -3012,30 +3588,30 @@ module \pipe1 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__oe_ok$next \alu_op__oe__oe$next } { \alu_op__rc__rc_ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__imm_ok$next \alu_op__imm_data__imm$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__oe_ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__rc_ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__imm_ok$73 \alu_op__imm_data__imm$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__ok$next \alu_op__oe__oe$next } { \alu_op__rc__ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__ok$next \alu_op__imm_data__data$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__oe_ok$next \alu_op__oe__oe$next } { \alu_op__rc__rc_ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__imm_ok$next \alu_op__imm_data__imm$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__oe_ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__rc_ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__imm_ok$73 \alu_op__imm_data__imm$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__ok$next \alu_op__oe__oe$next } { \alu_op__rc__ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__ok$next \alu_op__imm_data__data$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$next 1'0 + assign \alu_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$next 1'0 assign \alu_op__rc__rc$next 1'0 - assign \alu_op__rc__rc_ok$next 1'0 + assign \alu_op__rc__ok$next 1'0 assign \alu_op__oe__oe$next 1'0 - assign \alu_op__oe__oe_ok$next 1'0 + assign \alu_op__oe__ok$next 1'0 end sync init update \alu_op__insn_type 7'0000000 update \alu_op__fn_unit 11'00000000000 - update \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_op__imm_data__imm_ok 1'0 + update \alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_op__imm_data__ok 1'0 update \alu_op__rc__rc 1'0 - update \alu_op__rc__rc_ok 1'0 + update \alu_op__rc__ok 1'0 update \alu_op__oe__oe 1'0 - update \alu_op__oe__oe_ok 1'0 + update \alu_op__oe__ok 1'0 update \alu_op__invert_in 1'0 update \alu_op__zero_a 1'0 update \alu_op__invert_out 1'0 @@ -3049,12 +3625,12 @@ module \pipe1 sync posedge \coresync_clk update \alu_op__insn_type \alu_op__insn_type$next update \alu_op__fn_unit \alu_op__fn_unit$next - update \alu_op__imm_data__imm \alu_op__imm_data__imm$next - update \alu_op__imm_data__imm_ok \alu_op__imm_data__imm_ok$next + update \alu_op__imm_data__data \alu_op__imm_data__data$next + update \alu_op__imm_data__ok \alu_op__imm_data__ok$next update \alu_op__rc__rc \alu_op__rc__rc$next - update \alu_op__rc__rc_ok \alu_op__rc__rc_ok$next + update \alu_op__rc__ok \alu_op__rc__ok$next update \alu_op__oe__oe \alu_op__oe__oe$next - update \alu_op__oe__oe_ok \alu_op__oe__oe_ok$next + update \alu_op__oe__ok \alu_op__oe__ok$next update \alu_op__invert_in \alu_op__invert_in$next update \alu_op__zero_a \alu_op__zero_a$next update \alu_op__invert_out \alu_op__invert_out$next @@ -3349,17 +3925,17 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__imm + wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__imm_ok + wire width 1 input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__rc_ok + wire width 1 input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__oe_ok + wire width 1 input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -3488,17 +4064,17 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 27 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 28 \alu_op__imm_data__imm$4 + wire width 64 output 28 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__imm_data__imm_ok$5 + wire width 1 output 29 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 30 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__rc__rc_ok$7 + wire width 1 output 31 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 32 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__oe__oe_ok$9 + wire width 1 output 33 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 34 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -3543,74 +4119,109 @@ module \output wire width 1 output 52 \xer_so$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 53 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $26 + end + process $group_0 + assign \oe 1'0 + assign \oe $26 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire width 1 \so + process $group_1 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + case 1'1 + assign \so \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" + case + assign \so \xer_so + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $31 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $28 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $32 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 - connect \A $28 - connect \Y $27 + connect \A $30 + connect \Y $29 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $31 + wire width 65 $33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $32 + cell $pos $34 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $31 + connect \Y $33 end - process $group_0 - assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + process $group_2 + assign \o$28 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" switch { \alu_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" case 1'1 - assign \o$26 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + assign \o$28 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" case - assign \o$26 $31 + assign \o$28 $33 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - process $group_1 + process $group_3 assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$26 [63:0] + assign \target \o$28 [63:0] sync init end - process $group_2 + process $group_4 assign \xer_ca$23 2'00 assign \xer_ca$23 \xer_ca sync init end - process $group_3 + process $group_5 assign \xer_ca_ok 1'0 assign \xer_ca_ok \alu_op__output_carry sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $36 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -3618,19 +4229,19 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $33 + connect \Y $35 end - process $group_4 + process $group_6 assign \is_cmp 1'0 - assign \is_cmp $33 + assign \is_cmp $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $38 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -3638,118 +4249,92 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $35 + connect \Y $37 end - process $group_5 + process $group_7 assign \is_cmpeqb 1'0 - assign \is_cmpeqb $35 + assign \is_cmpeqb $37 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire width 1 \msb_test - process $group_6 + process $group_8 assign \msb_test 1'0 assign \msb_test \target [63] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_bool $40 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $37 + connect \Y $39 end - process $group_7 + process $group_9 assign \is_nzero 1'0 - assign \is_nzero $37 + assign \is_nzero $39 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire width 1 \is_negative + process $group_10 + assign \is_negative 1'0 + assign \is_negative \msb_test sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $39 + connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \B $39 - connect \Y $41 + connect \B $41 + connect \Y $43 end - process $group_8 + process $group_11 assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $41 - end + assign \is_positive $43 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $43 + connect \A \is_cmpeqb + connect \B \is_cmp connect \Y $45 end - process $group_9 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -3757,53 +4342,53 @@ module \output connect \A \is_nzero connect \Y $47 end - process $group_10 + process $group_12 assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch { $45 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" case 1'1 assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" case - assign \cr0 { \is_negative \is_positive $47 \xer_so$25 } + assign \cr0 { \is_negative \is_positive $47 \so } end sync init end - process $group_11 + process $group_13 assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$26 [63:0] + assign \o$20 \o$28 [63:0] sync init end - process $group_12 + process $group_14 assign \o_ok$21 1'0 assign \o_ok$21 \o_ok sync init end - process $group_13 + process $group_15 assign \cr_a$22 4'0000 assign \cr_a$22 \cr0 sync init end - process $group_14 + process $group_16 assign \cr_a_ok 1'0 assign \cr_a_ok \alu_op__write_cr0 sync init end - process $group_15 + process $group_17 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_16 + process $group_18 assign \alu_op__insn_type$2 7'0000000 assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5 1'0 + assign \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$5 1'0 assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__rc_ok$7 1'0 + assign \alu_op__rc__ok$7 1'0 assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__oe_ok$9 1'0 + assign \alu_op__oe__ok$9 1'0 assign \alu_op__invert_in$10 1'0 assign \alu_op__zero_a$11 1'0 assign \alu_op__invert_out$12 1'0 @@ -3814,35 +4399,33 @@ module \output assign \alu_op__is_signed$17 1'0 assign \alu_op__data_len$18 4'0000 assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $50 + wire width 1 \oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe - connect \B \alu_op__oe__oe_ok - connect \Y $49 + connect \B \alu_op__oe__ok + connect \Y $50 end - process $group_34 - assign \oe 1'0 - assign \oe $49 + process $group_36 + assign \oe$49 1'0 + assign \oe$49 $50 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -3850,53 +4433,43 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $51 - end - process $group_35 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $51 - end - sync init + connect \Y $52 end - process $group_36 + process $group_37 assign \xer_so$25 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 - assign \xer_so$25 \so + assign \xer_so$25 $52 end sync init end - process $group_37 + process $group_38 assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_so_ok 1'1 end sync init end - process $group_38 + process $group_39 assign \xer_ov$24 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_ov$24 \xer_ov end sync init end - process $group_39 + process $group_40 assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_ov_ok 1'1 end @@ -3906,9 +4479,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" module \pipe2 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -4006,17 +4579,17 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__imm + wire width 64 input 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__imm_data__imm_ok + wire width 1 input 8 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__rc__rc_ok + wire width 1 input 10 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__oe__oe_ok + wire width 1 input 12 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -4163,29 +4736,29 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \alu_op__imm_data__imm$4 + wire width 64 output 38 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$4$next + wire width 64 \alu_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__imm_data__imm_ok$5 + wire width 1 output 39 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$5$next + wire width 1 \alu_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 40 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \alu_op__rc__rc_ok$7 + wire width 1 output 41 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$7$next + wire width 1 \alu_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 42 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \alu_op__oe__oe_ok$9 + wire width 1 output 43 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$9$next + wire width 1 \alu_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 44 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -4370,17 +4943,17 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__imm + wire width 64 \output_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__imm_data__imm_ok + wire width 1 \output_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__rc__rc_ok + wire width 1 \output_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__oe__oe_ok + wire width 1 \output_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -4509,17 +5082,17 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_alu_op__fn_unit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__imm$33 + wire width 64 \output_alu_op__imm_data__data$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__imm_data__imm_ok$34 + wire width 1 \output_alu_op__imm_data__ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_alu_op__rc__rc$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__rc__rc_ok$36 + wire width 1 \output_alu_op__rc__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_alu_op__oe__oe$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__oe__oe_ok$38 + wire width 1 \output_alu_op__oe__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_alu_op__invert_in$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -4568,12 +5141,12 @@ module \pipe2 connect \muxid \output_muxid connect \alu_op__insn_type \output_alu_op__insn_type connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__imm_data__imm \output_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm_ok + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc_ok \output_alu_op__rc__rc_ok + connect \alu_op__rc__ok \output_alu_op__rc__ok connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__oe_ok \output_alu_op__oe__oe_ok + connect \alu_op__oe__ok \output_alu_op__oe__ok connect \alu_op__invert_in \output_alu_op__invert_in connect \alu_op__zero_a \output_alu_op__zero_a connect \alu_op__invert_out \output_alu_op__invert_out @@ -4593,12 +5166,12 @@ module \pipe2 connect \muxid$1 \output_muxid$30 connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 - connect \alu_op__imm_data__imm$4 \output_alu_op__imm_data__imm$33 - connect \alu_op__imm_data__imm_ok$5 \output_alu_op__imm_data__imm_ok$34 + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__rc__rc_ok$7 \output_alu_op__rc__rc_ok$36 + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 - connect \alu_op__oe__oe_ok$9 \output_alu_op__oe__oe_ok$38 + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 @@ -4628,12 +5201,12 @@ module \pipe2 process $group_1 assign \output_alu_op__insn_type 7'0000000 assign \output_alu_op__fn_unit 11'00000000000 - assign \output_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_alu_op__imm_data__imm_ok 1'0 + assign \output_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_alu_op__imm_data__ok 1'0 assign \output_alu_op__rc__rc 1'0 - assign \output_alu_op__rc__rc_ok 1'0 + assign \output_alu_op__rc__ok 1'0 assign \output_alu_op__oe__oe 1'0 - assign \output_alu_op__oe__oe_ok 1'0 + assign \output_alu_op__oe__ok 1'0 assign \output_alu_op__invert_in 1'0 assign \output_alu_op__zero_a 1'0 assign \output_alu_op__invert_out 1'0 @@ -4644,7 +5217,7 @@ module \pipe2 assign \output_alu_op__is_signed 1'0 assign \output_alu_op__data_len 4'0000 assign \output_alu_op__insn 32'00000000000000000000000000000000 - assign { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in { \output_alu_op__oe__oe_ok \output_alu_op__oe__oe } { \output_alu_op__rc__rc_ok \output_alu_op__rc__rc } { \output_alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm } \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + assign { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in { \output_alu_op__oe__ok \output_alu_op__oe__oe } { \output_alu_op__rc__ok \output_alu_op__rc__rc } { \output_alu_op__imm_data__ok \output_alu_op__imm_data__data } \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } sync init end process $group_19 @@ -4816,17 +5389,17 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_op__fn_unit$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$65 + wire width 64 \alu_op__imm_data__data$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$66 + wire width 1 \alu_op__imm_data__ok$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__rc__rc$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$68 + wire width 1 \alu_op__rc__ok$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__oe__oe$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$70 + wire width 1 \alu_op__oe__ok$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__invert_in$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -4854,12 +5427,12 @@ module \pipe2 process $group_33 assign \alu_op__insn_type$63 7'0000000 assign \alu_op__fn_unit$64 11'00000000000 - assign \alu_op__imm_data__imm$65 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$66 1'0 + assign \alu_op__imm_data__data$65 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$66 1'0 assign \alu_op__rc__rc$67 1'0 - assign \alu_op__rc__rc_ok$68 1'0 + assign \alu_op__rc__ok$68 1'0 assign \alu_op__oe__oe$69 1'0 - assign \alu_op__oe__oe_ok$70 1'0 + assign \alu_op__oe__ok$70 1'0 assign \alu_op__invert_in$71 1'0 assign \alu_op__zero_a$72 1'0 assign \alu_op__invert_out$73 1'0 @@ -4870,7 +5443,7 @@ module \pipe2 assign \alu_op__is_signed$78 1'0 assign \alu_op__data_len$79 4'0000 assign \alu_op__insn$80 32'00000000000000000000000000000000 - assign { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__oe_ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__rc_ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__imm_ok$66 \alu_op__imm_data__imm$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 { \output_alu_op__oe__oe_ok$38 \output_alu_op__oe__oe$37 } { \output_alu_op__rc__rc_ok$36 \output_alu_op__rc__rc$35 } { \output_alu_op__imm_data__imm_ok$34 \output_alu_op__imm_data__imm$33 } \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + assign { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 { \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 } { \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 } { \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 } \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -4967,12 +5540,12 @@ module \pipe2 process $group_63 assign \alu_op__insn_type$2$next \alu_op__insn_type$2 assign \alu_op__fn_unit$3$next \alu_op__fn_unit$3 - assign \alu_op__imm_data__imm$4$next \alu_op__imm_data__imm$4 - assign \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm_ok$5 + assign \alu_op__imm_data__data$4$next \alu_op__imm_data__data$4 + assign \alu_op__imm_data__ok$5$next \alu_op__imm_data__ok$5 assign \alu_op__rc__rc$6$next \alu_op__rc__rc$6 - assign \alu_op__rc__rc_ok$7$next \alu_op__rc__rc_ok$7 + assign \alu_op__rc__ok$7$next \alu_op__rc__ok$7 assign \alu_op__oe__oe$8$next \alu_op__oe__oe$8 - assign \alu_op__oe__oe_ok$9$next \alu_op__oe__oe_ok$9 + assign \alu_op__oe__ok$9$next \alu_op__oe__ok$9 assign \alu_op__invert_in$10$next \alu_op__invert_in$10 assign \alu_op__zero_a$11$next \alu_op__zero_a$11 assign \alu_op__invert_out$12$next \alu_op__invert_out$12 @@ -4987,30 +5560,30 @@ module \pipe2 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__oe_ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__rc_ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__imm_ok$66 \alu_op__imm_data__imm$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__ok$5$next \alu_op__imm_data__data$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__oe_ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__rc_ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__imm_ok$66 \alu_op__imm_data__imm$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__ok$5$next \alu_op__imm_data__data$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5$next 1'0 + assign \alu_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$5$next 1'0 assign \alu_op__rc__rc$6$next 1'0 - assign \alu_op__rc__rc_ok$7$next 1'0 + assign \alu_op__rc__ok$7$next 1'0 assign \alu_op__oe__oe$8$next 1'0 - assign \alu_op__oe__oe_ok$9$next 1'0 + assign \alu_op__oe__ok$9$next 1'0 end sync init update \alu_op__insn_type$2 7'0000000 update \alu_op__fn_unit$3 11'00000000000 - update \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_op__imm_data__imm_ok$5 1'0 + update \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_op__imm_data__ok$5 1'0 update \alu_op__rc__rc$6 1'0 - update \alu_op__rc__rc_ok$7 1'0 + update \alu_op__rc__ok$7 1'0 update \alu_op__oe__oe$8 1'0 - update \alu_op__oe__oe_ok$9 1'0 + update \alu_op__oe__ok$9 1'0 update \alu_op__invert_in$10 1'0 update \alu_op__zero_a$11 1'0 update \alu_op__invert_out$12 1'0 @@ -5024,12 +5597,12 @@ module \pipe2 sync posedge \coresync_clk update \alu_op__insn_type$2 \alu_op__insn_type$2$next update \alu_op__fn_unit$3 \alu_op__fn_unit$3$next - update \alu_op__imm_data__imm$4 \alu_op__imm_data__imm$4$next - update \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm_ok$5$next + update \alu_op__imm_data__data$4 \alu_op__imm_data__data$4$next + update \alu_op__imm_data__ok$5 \alu_op__imm_data__ok$5$next update \alu_op__rc__rc$6 \alu_op__rc__rc$6$next - update \alu_op__rc__rc_ok$7 \alu_op__rc__rc_ok$7$next + update \alu_op__rc__ok$7 \alu_op__rc__ok$7$next update \alu_op__oe__oe$8 \alu_op__oe__oe$8$next - update \alu_op__oe__oe_ok$9 \alu_op__oe__oe_ok$9$next + update \alu_op__oe__ok$9 \alu_op__oe__ok$9$next update \alu_op__invert_in$10 \alu_op__invert_in$10$next update \alu_op__zero_a$11 \alu_op__zero_a$11$next update \alu_op__invert_out$12 \alu_op__invert_out$12$next @@ -5175,7 +5748,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" module \alu_alu0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -5187,7 +5760,7 @@ module \alu_alu0 wire width 1 output 4 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 5 \xer_so_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 6 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 7 \n_valid_o @@ -5283,17 +5856,17 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 10 \alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \alu_op__imm_data__imm + wire width 64 input 11 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__imm_data__imm_ok + wire width 1 input 12 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__rc__rc_ok + wire width 1 input 14 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 15 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__oe__oe_ok + wire width 1 input 16 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 17 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -5444,17 +6017,17 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe1_alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__imm + wire width 64 \pipe1_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__imm_data__imm_ok + wire width 1 \pipe1_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__rc__rc_ok + wire width 1 \pipe1_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__oe__oe_ok + wire width 1 \pipe1_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -5595,17 +6168,17 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe1_alu_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__imm$6 + wire width 64 \pipe1_alu_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__imm_data__imm_ok$7 + wire width 1 \pipe1_alu_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_alu_op__rc__rc$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__rc__rc_ok$9 + wire width 1 \pipe1_alu_op__rc__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_alu_op__oe__oe$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__oe__oe_ok$11 + wire width 1 \pipe1_alu_op__oe__ok$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_alu_op__invert_in$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -5646,12 +6219,12 @@ module \alu_alu0 connect \muxid \pipe1_muxid connect \alu_op__insn_type \pipe1_alu_op__insn_type connect \alu_op__fn_unit \pipe1_alu_op__fn_unit - connect \alu_op__imm_data__imm \pipe1_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \pipe1_alu_op__imm_data__imm_ok + connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data + connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok connect \alu_op__rc__rc \pipe1_alu_op__rc__rc - connect \alu_op__rc__rc_ok \pipe1_alu_op__rc__rc_ok + connect \alu_op__rc__ok \pipe1_alu_op__rc__ok connect \alu_op__oe__oe \pipe1_alu_op__oe__oe - connect \alu_op__oe__oe_ok \pipe1_alu_op__oe__oe_ok + connect \alu_op__oe__ok \pipe1_alu_op__oe__ok connect \alu_op__invert_in \pipe1_alu_op__invert_in connect \alu_op__zero_a \pipe1_alu_op__zero_a connect \alu_op__invert_out \pipe1_alu_op__invert_out @@ -5677,12 +6250,12 @@ module \alu_alu0 connect \muxid$1 \pipe1_muxid$3 connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 - connect \alu_op__imm_data__imm$4 \pipe1_alu_op__imm_data__imm$6 - connect \alu_op__imm_data__imm_ok$5 \pipe1_alu_op__imm_data__imm_ok$7 + connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 + connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 - connect \alu_op__rc__rc_ok$7 \pipe1_alu_op__rc__rc_ok$9 + connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 - connect \alu_op__oe__oe_ok$9 \pipe1_alu_op__oe__oe_ok$11 + connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 @@ -5794,17 +6367,17 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe2_alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__imm + wire width 64 \pipe2_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__imm_data__imm_ok + wire width 1 \pipe2_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__rc__rc_ok + wire width 1 \pipe2_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__oe__oe_ok + wire width 1 \pipe2_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -5945,17 +6518,17 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe2_alu_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__imm$27 + wire width 64 \pipe2_alu_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__imm_data__imm_ok$28 + wire width 1 \pipe2_alu_op__imm_data__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_alu_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__rc__rc_ok$30 + wire width 1 \pipe2_alu_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_alu_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__oe__oe_ok$32 + wire width 1 \pipe2_alu_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_alu_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -6008,12 +6581,12 @@ module \alu_alu0 connect \muxid \pipe2_muxid connect \alu_op__insn_type \pipe2_alu_op__insn_type connect \alu_op__fn_unit \pipe2_alu_op__fn_unit - connect \alu_op__imm_data__imm \pipe2_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \pipe2_alu_op__imm_data__imm_ok + connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data + connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok connect \alu_op__rc__rc \pipe2_alu_op__rc__rc - connect \alu_op__rc__rc_ok \pipe2_alu_op__rc__rc_ok + connect \alu_op__rc__ok \pipe2_alu_op__rc__ok connect \alu_op__oe__oe \pipe2_alu_op__oe__oe - connect \alu_op__oe__oe_ok \pipe2_alu_op__oe__oe_ok + connect \alu_op__oe__ok \pipe2_alu_op__oe__ok connect \alu_op__invert_in \pipe2_alu_op__invert_in connect \alu_op__zero_a \pipe2_alu_op__zero_a connect \alu_op__invert_out \pipe2_alu_op__invert_out @@ -6039,12 +6612,12 @@ module \alu_alu0 connect \muxid$1 \pipe2_muxid$24 connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 - connect \alu_op__imm_data__imm$4 \pipe2_alu_op__imm_data__imm$27 - connect \alu_op__imm_data__imm_ok$5 \pipe2_alu_op__imm_data__imm_ok$28 + connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 + connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 - connect \alu_op__rc__rc_ok$7 \pipe2_alu_op__rc__rc_ok$30 + connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 - connect \alu_op__oe__oe_ok$9 \pipe2_alu_op__oe__oe_ok$32 + connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 @@ -6084,12 +6657,12 @@ module \alu_alu0 process $group_3 assign \pipe2_alu_op__insn_type 7'0000000 assign \pipe2_alu_op__fn_unit 11'00000000000 - assign \pipe2_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe2_alu_op__imm_data__imm_ok 1'0 + assign \pipe2_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe2_alu_op__imm_data__ok 1'0 assign \pipe2_alu_op__rc__rc 1'0 - assign \pipe2_alu_op__rc__rc_ok 1'0 + assign \pipe2_alu_op__rc__ok 1'0 assign \pipe2_alu_op__oe__oe 1'0 - assign \pipe2_alu_op__oe__oe_ok 1'0 + assign \pipe2_alu_op__oe__ok 1'0 assign \pipe2_alu_op__invert_in 1'0 assign \pipe2_alu_op__zero_a 1'0 assign \pipe2_alu_op__invert_out 1'0 @@ -6100,7 +6673,7 @@ module \alu_alu0 assign \pipe2_alu_op__is_signed 1'0 assign \pipe2_alu_op__data_len 4'0000 assign \pipe2_alu_op__insn 32'00000000000000000000000000000000 - assign { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in { \pipe2_alu_op__oe__oe_ok \pipe2_alu_op__oe__oe } { \pipe2_alu_op__rc__rc_ok \pipe2_alu_op__rc__rc } { \pipe2_alu_op__imm_data__imm_ok \pipe2_alu_op__imm_data__imm } \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in { \pipe1_alu_op__oe__oe_ok \pipe1_alu_op__oe__oe } { \pipe1_alu_op__rc__rc_ok \pipe1_alu_op__rc__rc } { \pipe1_alu_op__imm_data__imm_ok \pipe1_alu_op__imm_data__imm } \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } + assign { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in { \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe } { \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc } { \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data } \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in { \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe } { \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc } { \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data } \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } sync init end process $group_21 @@ -6153,12 +6726,12 @@ module \alu_alu0 process $group_34 assign \pipe1_alu_op__insn_type$4 7'0000000 assign \pipe1_alu_op__fn_unit$5 11'00000000000 - assign \pipe1_alu_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_alu_op__imm_data__imm_ok$7 1'0 + assign \pipe1_alu_op__imm_data__data$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_alu_op__imm_data__ok$7 1'0 assign \pipe1_alu_op__rc__rc$8 1'0 - assign \pipe1_alu_op__rc__rc_ok$9 1'0 + assign \pipe1_alu_op__rc__ok$9 1'0 assign \pipe1_alu_op__oe__oe$10 1'0 - assign \pipe1_alu_op__oe__oe_ok$11 1'0 + assign \pipe1_alu_op__oe__ok$11 1'0 assign \pipe1_alu_op__invert_in$12 1'0 assign \pipe1_alu_op__zero_a$13 1'0 assign \pipe1_alu_op__invert_out$14 1'0 @@ -6169,7 +6742,7 @@ module \alu_alu0 assign \pipe1_alu_op__is_signed$19 1'0 assign \pipe1_alu_op__data_len$20 4'0000 assign \pipe1_alu_op__insn$21 32'00000000000000000000000000000000 - assign { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 { \pipe1_alu_op__oe__oe_ok$11 \pipe1_alu_op__oe__oe$10 } { \pipe1_alu_op__rc__rc_ok$9 \pipe1_alu_op__rc__rc$8 } { \pipe1_alu_op__imm_data__imm_ok$7 \pipe1_alu_op__imm_data__imm$6 } \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + assign { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 { \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 } { \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 } { \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 } \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } sync init end process $group_52 @@ -6299,17 +6872,17 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$56 + wire width 64 \alu_op__imm_data__data$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$57 + wire width 1 \alu_op__imm_data__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__rc__rc$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$59 + wire width 1 \alu_op__rc__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$61 + wire width 1 \alu_op__oe__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_op__invert_in$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -6337,12 +6910,12 @@ module \alu_alu0 process $group_59 assign \alu_op__insn_type$54 7'0000000 assign \alu_op__fn_unit$55 11'00000000000 - assign \alu_op__imm_data__imm$56 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$57 1'0 + assign \alu_op__imm_data__data$56 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__ok$57 1'0 assign \alu_op__rc__rc$58 1'0 - assign \alu_op__rc__rc_ok$59 1'0 + assign \alu_op__rc__ok$59 1'0 assign \alu_op__oe__oe$60 1'0 - assign \alu_op__oe__oe_ok$61 1'0 + assign \alu_op__oe__ok$61 1'0 assign \alu_op__invert_in$62 1'0 assign \alu_op__zero_a$63 1'0 assign \alu_op__invert_out$64 1'0 @@ -6353,7 +6926,7 @@ module \alu_alu0 assign \alu_op__is_signed$69 1'0 assign \alu_op__data_len$70 4'0000 assign \alu_op__insn$71 32'00000000000000000000000000000000 - assign { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 { \alu_op__oe__oe_ok$61 \alu_op__oe__oe$60 } { \alu_op__rc__rc_ok$59 \alu_op__rc__rc$58 } { \alu_op__imm_data__imm_ok$57 \alu_op__imm_data__imm$56 } \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 { \pipe2_alu_op__oe__oe_ok$32 \pipe2_alu_op__oe__oe$31 } { \pipe2_alu_op__rc__rc_ok$30 \pipe2_alu_op__rc__rc$29 } { \pipe2_alu_op__imm_data__imm_ok$28 \pipe2_alu_op__imm_data__imm$27 } \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } + assign { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 { \alu_op__oe__ok$61 \alu_op__oe__oe$60 } { \alu_op__rc__ok$59 \alu_op__rc__rc$58 } { \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 } \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 { \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 } { \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 } { \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 } \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } sync init end process $group_77 @@ -6391,9 +6964,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" module \src_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 input 2 \s_src @@ -6536,9 +7109,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" module \opc_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -6681,9 +7254,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" module \req_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 output 2 \q_req @@ -6826,9 +7399,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" module \rst_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -6971,9 +7544,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" module \rok_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -7116,9 +7689,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" module \alui_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -7261,9 +7834,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" module \alu_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -7406,7 +7979,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" module \alu0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7498,17 +8071,17 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_alu0__imm_data__imm + wire width 64 input 3 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_alu0__imm_data__imm_ok + wire width 1 input 4 \oper_i_alu_alu0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_alu0__rc__rc_ok + wire width 1 input 6 \oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_alu0__oe__oe_ok + wire width 1 input 8 \oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -7575,7 +8148,7 @@ module \alu0 wire width 1 output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 1 output 39 \dest5_o - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 40 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_alu0_n_valid_o @@ -7675,29 +8248,29 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_alu0_alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_alu0_alu_op__imm_data__imm + wire width 64 \alu_alu0_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_alu0_alu_op__imm_data__imm$next + wire width 64 \alu_alu0_alu_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__imm_data__imm_ok + wire width 1 \alu_alu0_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__imm_data__imm_ok$next + wire width 1 \alu_alu0_alu_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_alu0_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_alu0_alu_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__rc_ok + wire width 1 \alu_alu0_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__rc_ok$next + wire width 1 \alu_alu0_alu_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_alu0_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_alu0_alu_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__oe_ok + wire width 1 \alu_alu0_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__oe_ok$next + wire width 1 \alu_alu0_alu_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_alu0_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -7776,12 +8349,12 @@ module \alu0 connect \n_ready_i \alu_alu0_n_ready_i connect \alu_op__insn_type \alu_alu0_alu_op__insn_type connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit - connect \alu_op__imm_data__imm \alu_alu0_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm_ok + connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data + connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc - connect \alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc_ok + connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe - connect \alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe_ok + connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok connect \alu_op__invert_in \alu_alu0_alu_op__invert_in connect \alu_op__zero_a \alu_alu0_alu_op__zero_a connect \alu_op__invert_out \alu_alu0_alu_op__invert_out @@ -8610,12 +9183,12 @@ module \alu0 process $group_27 assign \alu_alu0_alu_op__insn_type$next \alu_alu0_alu_op__insn_type assign \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__fn_unit - assign \alu_alu0_alu_op__imm_data__imm$next \alu_alu0_alu_op__imm_data__imm - assign \alu_alu0_alu_op__imm_data__imm_ok$next \alu_alu0_alu_op__imm_data__imm_ok + assign \alu_alu0_alu_op__imm_data__data$next \alu_alu0_alu_op__imm_data__data + assign \alu_alu0_alu_op__imm_data__ok$next \alu_alu0_alu_op__imm_data__ok assign \alu_alu0_alu_op__rc__rc$next \alu_alu0_alu_op__rc__rc - assign \alu_alu0_alu_op__rc__rc_ok$next \alu_alu0_alu_op__rc__rc_ok + assign \alu_alu0_alu_op__rc__ok$next \alu_alu0_alu_op__rc__ok assign \alu_alu0_alu_op__oe__oe$next \alu_alu0_alu_op__oe__oe - assign \alu_alu0_alu_op__oe__oe_ok$next \alu_alu0_alu_op__oe__oe_ok + assign \alu_alu0_alu_op__oe__ok$next \alu_alu0_alu_op__oe__ok assign \alu_alu0_alu_op__invert_in$next \alu_alu0_alu_op__invert_in assign \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__zero_a assign \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__invert_out @@ -8630,27 +9203,27 @@ module \alu0 switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_alu0_alu_op__insn$next \alu_alu0_alu_op__data_len$next \alu_alu0_alu_op__is_signed$next \alu_alu0_alu_op__is_32bit$next \alu_alu0_alu_op__output_carry$next \alu_alu0_alu_op__input_carry$next \alu_alu0_alu_op__write_cr0$next \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__invert_in$next { \alu_alu0_alu_op__oe__oe_ok$next \alu_alu0_alu_op__oe__oe$next } { \alu_alu0_alu_op__rc__rc_ok$next \alu_alu0_alu_op__rc__rc$next } { \alu_alu0_alu_op__imm_data__imm_ok$next \alu_alu0_alu_op__imm_data__imm$next } \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + assign { \alu_alu0_alu_op__insn$next \alu_alu0_alu_op__data_len$next \alu_alu0_alu_op__is_signed$next \alu_alu0_alu_op__is_32bit$next \alu_alu0_alu_op__output_carry$next \alu_alu0_alu_op__input_carry$next \alu_alu0_alu_op__write_cr0$next \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__invert_in$next { \alu_alu0_alu_op__oe__ok$next \alu_alu0_alu_op__oe__oe$next } { \alu_alu0_alu_op__rc__ok$next \alu_alu0_alu_op__rc__rc$next } { \alu_alu0_alu_op__imm_data__ok$next \alu_alu0_alu_op__imm_data__data$next } \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in { \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_alu0_alu_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_alu_op__imm_data__imm_ok$next 1'0 + assign \alu_alu0_alu_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_alu_op__imm_data__ok$next 1'0 assign \alu_alu0_alu_op__rc__rc$next 1'0 - assign \alu_alu0_alu_op__rc__rc_ok$next 1'0 + assign \alu_alu0_alu_op__rc__ok$next 1'0 assign \alu_alu0_alu_op__oe__oe$next 1'0 - assign \alu_alu0_alu_op__oe__oe_ok$next 1'0 + assign \alu_alu0_alu_op__oe__ok$next 1'0 end sync init update \alu_alu0_alu_op__insn_type 7'0000000 update \alu_alu0_alu_op__fn_unit 11'00000000000 - update \alu_alu0_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_alu0_alu_op__imm_data__imm_ok 1'0 + update \alu_alu0_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_alu0_alu_op__imm_data__ok 1'0 update \alu_alu0_alu_op__rc__rc 1'0 - update \alu_alu0_alu_op__rc__rc_ok 1'0 + update \alu_alu0_alu_op__rc__ok 1'0 update \alu_alu0_alu_op__oe__oe 1'0 - update \alu_alu0_alu_op__oe__oe_ok 1'0 + update \alu_alu0_alu_op__oe__ok 1'0 update \alu_alu0_alu_op__invert_in 1'0 update \alu_alu0_alu_op__zero_a 1'0 update \alu_alu0_alu_op__invert_out 1'0 @@ -8664,12 +9237,12 @@ module \alu0 sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type \alu_alu0_alu_op__insn_type$next update \alu_alu0_alu_op__fn_unit \alu_alu0_alu_op__fn_unit$next - update \alu_alu0_alu_op__imm_data__imm \alu_alu0_alu_op__imm_data__imm$next - update \alu_alu0_alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm_ok$next + update \alu_alu0_alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data$next + update \alu_alu0_alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok$next update \alu_alu0_alu_op__rc__rc \alu_alu0_alu_op__rc__rc$next - update \alu_alu0_alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc_ok$next + update \alu_alu0_alu_op__rc__ok \alu_alu0_alu_op__rc__ok$next update \alu_alu0_alu_op__oe__oe \alu_alu0_alu_op__oe__oe$next - update \alu_alu0_alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe_ok$next + update \alu_alu0_alu_op__oe__ok \alu_alu0_alu_op__oe__ok$next update \alu_alu0_alu_op__invert_in \alu_alu0_alu_op__invert_in$next update \alu_alu0_alu_op__zero_a \alu_alu0_alu_op__zero_a$next update \alu_alu0_alu_op__invert_out \alu_alu0_alu_op__invert_out$next @@ -8969,7 +9542,7 @@ module \alu0 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__imm_data__imm_ok + connect \S \alu_alu0_alu_op__imm_data__ok connect \Y $86 end process $group_58 @@ -8985,8 +9558,8 @@ module \alu0 cell $mux $90 parameter \WIDTH 64 connect \A \src2_i - connect \B \alu_alu0_alu_op__imm_data__imm - connect \S \alu_alu0_alu_op__imm_data__imm_ok + connect \B \alu_alu0_alu_op__imm_data__data + connect \S \alu_alu0_alu_op__imm_data__ok connect \Y $89 end process $group_59 @@ -9229,7 +9802,7 @@ module \alu0 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_alu0_alu_op__imm_data__imm_ok + connect \A \alu_alu0_alu_op__imm_data__ok connect \Y $107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -9697,24 +10270,20 @@ module \main$9 wire width 11 input 2 \cr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \cr_op__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \cr_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 6 \ra + wire width 64 input 4 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 7 \rb + wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 8 \full_cr + wire width 32 input 6 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 9 \cr_a + wire width 4 input 7 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 10 \cr_b + wire width 4 input 8 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_c + wire width 4 input 9 \cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 12 \muxid$1 + wire width 2 output 10 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -9789,7 +10358,7 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 13 \cr_op__insn_type$2 + wire width 7 output 11 \cr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -9803,261 +10372,250 @@ module \main$9 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 14 \cr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 15 \cr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \cr_op__read_cr_whole$5 + wire width 11 output 12 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 17 \cr_op__write_cr_whole$6 + wire width 32 output 13 \cr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \o + wire width 64 output 14 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \o_ok + wire width 1 output 15 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 20 \full_cr$7 + wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 21 \full_cr_ok + wire width 1 output 17 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 22 \cr_a$8 + wire width 4 output 18 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:51" - wire width 32 \mask - process $group_0 - assign \mask 32'00000000000000000000000000000000 - assign \mask { { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] } } - sync init - end + wire width 1 output 19 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 5 $9 + wire width 5 $7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $10 + cell $pos $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $9 + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" wire width 1 \bit_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" wire width 2 \bt - process $group_1 - assign \cr_a$8 4'0000 + process $group_0 + assign \cr_a$6 4'0000 assign \cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - assign { \cr_a_ok \cr_a$8 } $9 + assign { \cr_a_ok \cr_a$6 } $7 assign \cr_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - assign \cr_a$8 \cr_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" + assign \cr_a$6 \cr_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt case 2'00 - assign { \cr_a_ok \cr_a$8 } [0] \bit_o + assign { \cr_a_ok \cr_a$6 } [0] \bit_o case 2'01 - assign { \cr_a_ok \cr_a$8 } [1] \bit_o + assign { \cr_a_ok \cr_a$6 } [1] \bit_o case 2'10 - assign { \cr_a_ok \cr_a$8 } [2] \bit_o + assign { \cr_a_ok \cr_a$6 } [2] \bit_o case 2'-- - assign { \cr_a_ok \cr_a$8 } [3] \bit_o + assign { \cr_a_ok \cr_a$6 } [3] \bit_o end switch { } case assign \cr_a_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut - process $group_3 + process $group_2 assign \lut 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 assign \lut \cr_op__insn [9:6] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - wire width 3 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - cell $sub $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $11 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A 2'11 - connect \B { \cr_op__insn [25] \cr_op__insn [24] \cr_op__insn [23] \cr_op__insn [22] \cr_op__insn [21] } [1:0] - connect \Y $12 + connect \B { \cr_op__insn [22] \cr_op__insn [21] } + connect \Y $10 end - connect $11 $12 - process $group_4 + connect $9 $10 + process $group_3 assign \bt 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - assign \bt $11 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + assign \bt $9 [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" wire width 2 \ba - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - wire width 3 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - cell $sub $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $14 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A 2'11 - connect \B { \cr_op__insn [20] \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] } [1:0] - connect \Y $15 + connect \B { \cr_op__insn [17] \cr_op__insn [16] } + connect \Y $13 end - connect $14 $15 - process $group_5 + connect $12 $13 + process $group_4 assign \ba 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - assign \ba $14 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + assign \ba $12 [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" wire width 2 \bb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" - wire width 3 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" - wire width 3 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" - cell $sub $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $17 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A 2'11 - connect \B { \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] \cr_op__insn [11] } [1:0] - connect \Y $18 + connect \B { \cr_op__insn [12] \cr_op__insn [11] } + connect \Y $16 end - connect $17 $18 - process $group_6 + connect $15 $16 + process $group_5 assign \bb 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - assign \bb $17 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + assign \bb $15 [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" wire width 1 \bit_a - process $group_7 + process $group_6 assign \bit_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" switch \ba case 2'00 assign \bit_a \cr_a [0] @@ -10068,34 +10626,34 @@ module \main$9 case 2'-- assign \bit_a \cr_a [3] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" wire width 1 \bit_b - process $group_8 + process $group_7 assign \bit_b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" switch \bb case 2'00 assign \bit_b \cr_b [0] @@ -10106,308 +10664,197 @@ module \main$9 case 2'-- assign \bit_b \cr_b [3] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:106" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:106" - cell $mux $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $19 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $20 + connect \Y $18 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" - cell $mux $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $21 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $22 + connect \Y $20 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" - cell $mux $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $23 parameter \WIDTH 1 - connect \A $22 - connect \B $20 + connect \A $20 + connect \B $18 connect \S \bit_b - connect \Y $24 + connect \Y $22 end - process $group_9 + process $group_8 assign \bit_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - assign \bit_o $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + assign \bit_o $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - wire width 32 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \ra [31:0] - connect \B \mask - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - wire width 32 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \mask - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - wire width 32 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \full_cr - connect \B $28 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - wire width 32 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $26 - connect \B $30 - connect \Y $32 - end - process $group_10 - assign \full_cr$7 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + process $group_9 + assign \full_cr$5 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - assign \full_cr$7 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + assign \full_cr$5 \ra [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - process $group_11 + process $group_10 assign \full_cr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 assign \full_cr_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:128" - wire width 1 \move_one - process $group_12 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - assign \move_one \cr_op__insn [20] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" - wire width 64 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" - wire width 32 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" - cell $and $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \full_cr - connect \B \mask - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" - cell $pos $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A $35 - connect \Y $34 - end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 $38 + wire width 64 $24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $39 + cell $pos $25 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $38 + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" - wire width 65 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" - wire width 64 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 65 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 64 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" wire width 1 \cr_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" - cell $mux $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $28 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $41 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" - cell $pos $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $29 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 - connect \A $41 - connect \Y $40 + connect \A $27 + connect \Y $26 end - process $group_13 + process $group_11 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:132" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:132" - case 1'1 - assign \o $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" - case - assign \o $38 - end - switch { } - case - assign \o_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + assign \o $24 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - assign { \o_ok \o } $40 + assign { \o_ok \o } $26 assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" switch { \cr_a [2] \cr_a [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" case 2'-1 assign \o 64'1111111111111111111111111111111111111111111111111111111111111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:160" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:146" case 2'1- assign \o 64'0000000000000000000000000000000000000000000000000000000000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:148" case assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 end @@ -10418,27 +10865,55 @@ module \main$9 end sync init end - process $group_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" + wire width 2 \BC + process $group_13 + assign \BC 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + assign \BC { \cr_op__insn [7] \cr_op__insn [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 + end + sync init + end + process $group_14 assign \cr_bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" attribute \nmigen.decoding "OP_MCRF/42" case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" attribute \nmigen.decoding "OP_CROP/69" case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" attribute \nmigen.decoding "OP_MTCRF/48" case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" attribute \nmigen.decoding "OP_MFCR/45" case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" attribute \nmigen.decoding "OP_ISEL/35" case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:151" - switch { \cr_op__insn [10] \cr_op__insn [9] \cr_op__insn [8] \cr_op__insn [7] \cr_op__insn [6] } [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC case 2'00 assign \cr_bit \cr_a [3] case 2'01 @@ -10448,33 +10923,31 @@ module \main$9 case 2'-- assign \cr_bit \cr_a [0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" attribute \nmigen.decoding "OP_SETB/59" case 7'0111011 end sync init end - process $group_16 + process $group_15 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_17 + process $group_16 assign \cr_op__insn_type$2 7'0000000 assign \cr_op__fn_unit$3 11'00000000000 assign \cr_op__insn$4 32'00000000000000000000000000000000 - assign \cr_op__read_cr_whole$5 1'0 - assign \cr_op__write_cr_whole$6 1'0 - assign { \cr_op__write_cr_whole$6 \cr_op__read_cr_whole$5 \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + assign { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" module \pipe - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -10573,28 +11046,24 @@ module \pipe wire width 11 input 6 \cr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \cr_op__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \cr_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \ra + wire width 64 input 8 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \rb + wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 12 \full_cr + wire width 32 input 10 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 13 \cr_a + wire width 4 input 11 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 14 \cr_b + wire width 4 input 12 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 15 \cr_c + wire width 4 input 13 \cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 16 \n_valid_o + wire width 1 output 14 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 17 \n_ready_i + wire width 1 input 15 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 + wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" @@ -10671,7 +11140,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 19 \cr_op__insn_type$2 + wire width 7 output 17 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$2$next attribute \enum_base_type "Function" @@ -10687,43 +11156,35 @@ module \pipe attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 20 \cr_op__fn_unit$3 + wire width 11 output 18 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \cr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 21 \cr_op__insn$4 + wire width 32 output 19 \cr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \cr_op__insn$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \cr_op__read_cr_whole$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__read_cr_whole$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \cr_op__write_cr_whole$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__write_cr_whole$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \o + wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \o_ok + wire width 1 output 21 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 26 \full_cr$7 + wire width 32 output 22 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$7$next + wire width 32 \full_cr$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \full_cr_ok + wire width 1 output 23 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \full_cr_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 28 \cr_a$8 + wire width 4 output 24 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$8$next + wire width 4 \cr_a$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \cr_a_ok + wire width 1 output 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \cr_a_ok$next cell \p$7 \p @@ -10827,10 +11288,6 @@ module \pipe wire width 11 \main_cr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -10844,7 +11301,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$9 + wire width 2 \main_muxid$7 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -10919,7 +11376,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type$10 + wire width 7 \main_cr_op__insn_type$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -10933,23 +11390,19 @@ module \pipe attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_cr_op__fn_unit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__read_cr_whole$13 + wire width 11 \main_cr_op__fn_unit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__write_cr_whole$14 + wire width 32 \main_cr_op__insn$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \main_full_cr$15 + wire width 32 \main_full_cr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \main_full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \main_cr_a$16 + wire width 4 \main_cr_a$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \main_cr_a_ok cell \main$9 \main @@ -10957,25 +11410,21 @@ module \pipe connect \cr_op__insn_type \main_cr_op__insn_type connect \cr_op__fn_unit \main_cr_op__fn_unit connect \cr_op__insn \main_cr_op__insn - connect \cr_op__read_cr_whole \main_cr_op__read_cr_whole - connect \cr_op__write_cr_whole \main_cr_op__write_cr_whole connect \ra \main_ra connect \rb \main_rb connect \full_cr \main_full_cr connect \cr_a \main_cr_a connect \cr_b \main_cr_b connect \cr_c \main_cr_c - connect \muxid$1 \main_muxid$9 - connect \cr_op__insn_type$2 \main_cr_op__insn_type$10 - connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$11 - connect \cr_op__insn$4 \main_cr_op__insn$12 - connect \cr_op__read_cr_whole$5 \main_cr_op__read_cr_whole$13 - connect \cr_op__write_cr_whole$6 \main_cr_op__write_cr_whole$14 + connect \muxid$1 \main_muxid$7 + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn$4 \main_cr_op__insn$10 connect \o \main_o connect \o_ok \main_o_ok - connect \full_cr$7 \main_full_cr$15 + connect \full_cr$5 \main_full_cr$11 connect \full_cr_ok \main_full_cr_ok - connect \cr_a$8 \main_cr_a$16 + connect \cr_a$6 \main_cr_a$12 connect \cr_a_ok \main_cr_a_ok end process $group_0 @@ -10987,51 +11436,49 @@ module \pipe assign \main_cr_op__insn_type 7'0000000 assign \main_cr_op__fn_unit 11'00000000000 assign \main_cr_op__insn 32'00000000000000000000000000000000 - assign \main_cr_op__read_cr_whole 1'0 - assign \main_cr_op__write_cr_whole 1'0 - assign { \main_cr_op__write_cr_whole \main_cr_op__read_cr_whole \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + assign { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } sync init end - process $group_6 + process $group_4 assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_ra \ra sync init end - process $group_7 + process $group_5 assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_rb \rb sync init end - process $group_8 + process $group_6 assign \main_full_cr 32'00000000000000000000000000000000 assign \main_full_cr \full_cr sync init end - process $group_9 + process $group_7 assign \main_cr_a 4'0000 assign \main_cr_a \cr_a sync init end - process $group_10 + process $group_8 assign \main_cr_b 4'0000 assign \main_cr_b \cr_b sync init end - process $group_11 + process $group_9 assign \main_cr_c 4'0000 assign \main_cr_c \cr_c sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$17 - process $group_12 - assign \p_valid_i$17 1'0 - assign \p_valid_i$17 \p_valid_i + wire width 1 \p_valid_i$13 + process $group_10 + assign \p_valid_i$13 1'0 + assign \p_valid_i$13 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_13 + process $group_11 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -11039,28 +11486,28 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $18 + wire width 1 $14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $19 + cell $and $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$17 + connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $18 + connect \Y $14 end - process $group_14 + process $group_12 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $18 + assign \p_valid_i_p_ready_o $14 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$20 - process $group_15 - assign \muxid$20 2'00 - assign \muxid$20 \main_muxid$9 + wire width 2 \muxid$16 + process $group_13 + assign \muxid$16 2'00 + assign \muxid$16 \main_muxid$7 sync init end attribute \enum_base_type "MicrOp" @@ -11137,7 +11584,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$21 + wire width 7 \cr_op__insn_type$17 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -11151,57 +11598,51 @@ module \pipe attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__read_cr_whole$24 + wire width 11 \cr_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__write_cr_whole$25 - process $group_16 - assign \cr_op__insn_type$21 7'0000000 - assign \cr_op__fn_unit$22 11'00000000000 - assign \cr_op__insn$23 32'00000000000000000000000000000000 - assign \cr_op__read_cr_whole$24 1'0 - assign \cr_op__write_cr_whole$25 1'0 - assign { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } { \main_cr_op__write_cr_whole$14 \main_cr_op__read_cr_whole$13 \main_cr_op__insn$12 \main_cr_op__fn_unit$11 \main_cr_op__insn_type$10 } + wire width 32 \cr_op__insn$19 + process $group_14 + assign \cr_op__insn_type$17 7'0000000 + assign \cr_op__fn_unit$18 11'00000000000 + assign \cr_op__insn$19 32'00000000000000000000000000000000 + assign { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$26 + wire width 64 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$27 - process $group_21 - assign \o$26 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$27 1'0 - assign { \o_ok$27 \o$26 } { \main_o_ok \main_o } + wire width 1 \o_ok$21 + process $group_17 + assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$21 1'0 + assign { \o_ok$21 \o$20 } { \main_o_ok \main_o } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$28 + wire width 32 \full_cr$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \full_cr_ok$29 - process $group_23 - assign \full_cr$28 32'00000000000000000000000000000000 - assign \full_cr_ok$29 1'0 - assign { \full_cr_ok$29 \full_cr$28 } { \main_full_cr_ok \main_full_cr$15 } + wire width 1 \full_cr_ok$23 + process $group_19 + assign \full_cr$22 32'00000000000000000000000000000000 + assign \full_cr_ok$23 1'0 + assign { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$30 + wire width 4 \cr_a$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$31 - process $group_25 - assign \cr_a$30 4'0000 - assign \cr_a_ok$31 1'0 - assign { \cr_a_ok$31 \cr_a$30 } { \main_cr_a_ok \main_cr_a$16 } + wire width 1 \cr_a_ok$25 + process $group_21 + assign \cr_a$24 4'0000 + assign \cr_a_ok$25 1'0 + assign { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_27 + process $group_23 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -11222,61 +11663,55 @@ module \pipe sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_28 + process $group_24 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$20 + assign \muxid$1$next \muxid$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$20 + assign \muxid$1$next \muxid$16 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_29 + process $group_25 assign \cr_op__insn_type$2$next \cr_op__insn_type$2 assign \cr_op__fn_unit$3$next \cr_op__fn_unit$3 assign \cr_op__insn$4$next \cr_op__insn$4 - assign \cr_op__read_cr_whole$5$next \cr_op__read_cr_whole$5 - assign \cr_op__write_cr_whole$6$next \cr_op__write_cr_whole$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } + assign { \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } + assign { \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } end sync init update \cr_op__insn_type$2 7'0000000 update \cr_op__fn_unit$3 11'00000000000 update \cr_op__insn$4 32'00000000000000000000000000000000 - update \cr_op__read_cr_whole$5 1'0 - update \cr_op__write_cr_whole$6 1'0 sync posedge \coresync_clk update \cr_op__insn_type$2 \cr_op__insn_type$2$next update \cr_op__fn_unit$3 \cr_op__fn_unit$3$next update \cr_op__insn$4 \cr_op__insn$4$next - update \cr_op__read_cr_whole$5 \cr_op__read_cr_whole$5$next - update \cr_op__write_cr_whole$6 \cr_op__write_cr_whole$6$next end - process $group_34 + process $group_28 assign \o$next \o assign \o_ok$next \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$27 \o$26 } + assign { \o_ok$next \o$next } { \o_ok$21 \o$20 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$next \o$next } { \o_ok$27 \o$26 } + assign { \o_ok$next \o$next } { \o_ok$21 \o$20 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -11290,17 +11725,17 @@ module \pipe update \o \o$next update \o_ok \o_ok$next end - process $group_36 - assign \full_cr$7$next \full_cr$7 + process $group_30 + assign \full_cr$5$next \full_cr$5 assign \full_cr_ok$next \full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 } + assign { \full_cr_ok$next \full_cr$5$next } { \full_cr_ok$23 \full_cr$22 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 } + assign { \full_cr_ok$next \full_cr$5$next } { \full_cr_ok$23 \full_cr$22 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -11308,23 +11743,23 @@ module \pipe assign \full_cr_ok$next 1'0 end sync init - update \full_cr$7 32'00000000000000000000000000000000 + update \full_cr$5 32'00000000000000000000000000000000 update \full_cr_ok 1'0 sync posedge \coresync_clk - update \full_cr$7 \full_cr$7$next + update \full_cr$5 \full_cr$5$next update \full_cr_ok \full_cr_ok$next end - process $group_38 - assign \cr_a$8$next \cr_a$8 + process $group_32 + assign \cr_a$6$next \cr_a$6 assign \cr_a_ok$next \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 } + assign { \cr_a_ok$next \cr_a$6$next } { \cr_a_ok$25 \cr_a$24 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 } + assign { \cr_a_ok$next \cr_a$6$next } { \cr_a_ok$25 \cr_a$24 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -11332,18 +11767,18 @@ module \pipe assign \cr_a_ok$next 1'0 end sync init - update \cr_a$8 4'0000 + update \cr_a$6 4'0000 update \cr_a_ok 1'0 sync posedge \coresync_clk - update \cr_a$8 \cr_a$8$next + update \cr_a$6 \cr_a$6$next update \cr_a_ok \cr_a_ok$next end - process $group_40 + process $group_34 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_41 + process $group_35 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init @@ -11352,7 +11787,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" module \alu_cr0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -11360,7 +11795,7 @@ module \alu_cr0 wire width 1 output 2 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 3 \cr_a_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 4 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 5 \n_valid_o @@ -11457,32 +11892,28 @@ module \alu_cr0 wire width 11 input 8 \cr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 9 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \cr_op__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \cr_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 12 \o + wire width 64 output 10 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 13 \full_cr + wire width 32 output 11 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 14 \cr_a + wire width 4 output 12 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \ra + wire width 64 input 13 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \rb + wire width 64 input 14 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 17 \full_cr$1 + wire width 32 input 15 \full_cr$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 18 \cr_a$2 + wire width 4 input 16 \cr_a$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 19 \cr_b + wire width 4 input 17 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 20 \cr_c + wire width 4 input 18 \cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 21 \p_valid_i + wire width 1 input 19 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 22 \p_ready_o + wire width 1 output 20 \p_ready_o cell \p$5 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -11588,10 +12019,6 @@ module \alu_cr0 wire width 11 \pipe_cr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -11701,20 +12128,16 @@ module \alu_cr0 wire width 11 \pipe_cr_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_cr_op__insn$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__read_cr_whole$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__write_cr_whole$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \pipe_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \pipe_full_cr$9 + wire width 32 \pipe_full_cr$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe_full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a$10 + wire width 4 \pipe_cr_a$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe_cr_a_ok cell \pipe \pipe @@ -11726,8 +12149,6 @@ module \alu_cr0 connect \cr_op__insn_type \pipe_cr_op__insn_type connect \cr_op__fn_unit \pipe_cr_op__fn_unit connect \cr_op__insn \pipe_cr_op__insn - connect \cr_op__read_cr_whole \pipe_cr_op__read_cr_whole - connect \cr_op__write_cr_whole \pipe_cr_op__write_cr_whole connect \ra \pipe_ra connect \rb \pipe_rb connect \full_cr \pipe_full_cr @@ -11740,13 +12161,11 @@ module \alu_cr0 connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 connect \cr_op__insn$4 \pipe_cr_op__insn$6 - connect \cr_op__read_cr_whole$5 \pipe_cr_op__read_cr_whole$7 - connect \cr_op__write_cr_whole$6 \pipe_cr_op__write_cr_whole$8 connect \o \pipe_o connect \o_ok \pipe_o_ok - connect \full_cr$7 \pipe_full_cr$9 + connect \full_cr$5 \pipe_full_cr$7 connect \full_cr_ok \pipe_full_cr_ok - connect \cr_a$8 \pipe_cr_a$10 + connect \cr_a$6 \pipe_cr_a$8 connect \cr_a_ok \pipe_cr_a_ok end process $group_0 @@ -11770,56 +12189,54 @@ module \alu_cr0 assign \pipe_cr_op__insn_type 7'0000000 assign \pipe_cr_op__fn_unit 11'00000000000 assign \pipe_cr_op__insn 32'00000000000000000000000000000000 - assign \pipe_cr_op__read_cr_whole 1'0 - assign \pipe_cr_op__write_cr_whole 1'0 - assign { \pipe_cr_op__write_cr_whole \pipe_cr_op__read_cr_whole \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + assign { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } sync init end - process $group_8 + process $group_6 assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_ra \ra sync init end - process $group_9 + process $group_7 assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_rb \rb sync init end - process $group_10 + process $group_8 assign \pipe_full_cr 32'00000000000000000000000000000000 assign \pipe_full_cr \full_cr$1 sync init end - process $group_11 + process $group_9 assign \pipe_cr_a 4'0000 assign \pipe_cr_a \cr_a$2 sync init end - process $group_12 + process $group_10 assign \pipe_cr_b 4'0000 assign \pipe_cr_b \cr_b sync init end - process $group_13 + process $group_11 assign \pipe_cr_c 4'0000 assign \pipe_cr_c \cr_c sync init end - process $group_14 + process $group_12 assign \n_valid_o 1'0 assign \n_valid_o \pipe_n_valid_o sync init end - process $group_15 + process $group_13 assign \pipe_n_ready_i 1'0 assign \pipe_n_ready_i \n_ready_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$11 - process $group_16 - assign \muxid$11 2'00 - assign \muxid$11 \pipe_muxid$3 + wire width 2 \muxid$9 + process $group_14 + assign \muxid$9 2'00 + assign \muxid$9 \pipe_muxid$3 sync init end attribute \enum_base_type "MicrOp" @@ -11896,7 +12313,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$12 + wire width 7 \cr_op__insn_type$10 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -11910,38 +12327,32 @@ module \alu_cr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$14 + wire width 11 \cr_op__fn_unit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__read_cr_whole$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__write_cr_whole$16 - process $group_17 - assign \cr_op__insn_type$12 7'0000000 - assign \cr_op__fn_unit$13 11'00000000000 - assign \cr_op__insn$14 32'00000000000000000000000000000000 - assign \cr_op__read_cr_whole$15 1'0 - assign \cr_op__write_cr_whole$16 1'0 - assign { \cr_op__write_cr_whole$16 \cr_op__read_cr_whole$15 \cr_op__insn$14 \cr_op__fn_unit$13 \cr_op__insn_type$12 } { \pipe_cr_op__write_cr_whole$8 \pipe_cr_op__read_cr_whole$7 \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + wire width 32 \cr_op__insn$12 + process $group_15 + assign \cr_op__insn_type$10 7'0000000 + assign \cr_op__fn_unit$11 11'00000000000 + assign \cr_op__insn$12 32'00000000000000000000000000000000 + assign { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } sync init end - process $group_22 + process $group_18 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o_ok 1'0 assign { \o_ok \o } { \pipe_o_ok \pipe_o } sync init end - process $group_24 + process $group_20 assign \full_cr 32'00000000000000000000000000000000 assign \full_cr_ok 1'0 - assign { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$9 } + assign { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } sync init end - process $group_26 + process $group_22 assign \cr_a 4'0000 assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$10 } + assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } sync init end connect \muxid 2'00 @@ -11949,9 +12360,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" module \src_l$10 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 6 input 2 \s_src @@ -12094,9 +12505,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" module \opc_l$11 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -12239,9 +12650,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" module \req_l$12 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req @@ -12384,9 +12795,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" module \rst_l$13 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -12529,9 +12940,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" module \rok_l$14 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -12674,9 +13085,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" module \alui_l$15 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -12819,9 +13230,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" module \alu_l$16 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -12964,7 +13375,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" module \cr0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13057,50 +13468,46 @@ module \cr0 wire width 11 input 2 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \oper_i_alu_cr0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_cr0__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_cr0__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 6 \cu_issue_i + wire width 1 input 4 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 7 \cu_busy_o + wire width 1 output 5 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 8 \cu_rdmaskn_i + wire width 6 input 6 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 9 \cu_rd__rel_o + wire width 6 output 7 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 10 \cu_rd__go_i + wire width 6 input 8 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 11 \src1_i + wire width 64 input 9 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 12 \src2_i + wire width 64 input 10 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 13 \src3_i + wire width 32 input 11 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 14 \src4_i + wire width 4 input 12 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 15 \src5_i + wire width 4 input 13 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 16 \src6_i + wire width 4 input 14 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \o_ok + wire width 1 output 15 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 18 \cu_wr__rel_o + wire width 3 output 16 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 19 \cu_wr__go_i + wire width 3 input 17 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 20 \dest1_o + wire width 64 output 18 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 21 \full_cr_ok + wire width 1 output 19 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 22 \dest2_o + wire width 32 output 20 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \cr_a_ok + wire width 1 output 21 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 24 \dest3_o - attribute \src "simple/issuer.py:102" - wire width 1 input 25 \coresync_rst + wire width 4 output 22 \dest3_o + attribute \src "simple/issuer.py:141" + wire width 1 input 23 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_cr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -13202,14 +13609,6 @@ module \cr0 wire width 32 \alu_cr0_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_cr0_cr_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_cr0_cr_op__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_cr0_cr_op__read_cr_whole$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_cr0_cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_cr0_cr_op__write_cr_whole$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \alu_cr0_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -13243,8 +13642,6 @@ module \cr0 connect \cr_op__insn_type \alu_cr0_cr_op__insn_type connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit connect \cr_op__insn \alu_cr0_cr_op__insn - connect \cr_op__read_cr_whole \alu_cr0_cr_op__read_cr_whole - connect \cr_op__write_cr_whole \alu_cr0_cr_op__write_cr_whole connect \o \alu_cr0_o connect \full_cr \alu_cr0_full_cr connect \cr_a \alu_cr0_cr_a @@ -14064,26 +14461,20 @@ module \cr0 assign \alu_cr0_cr_op__insn_type$next \alu_cr0_cr_op__insn_type assign \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__fn_unit assign \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__insn - assign \alu_cr0_cr_op__read_cr_whole$next \alu_cr0_cr_op__read_cr_whole - assign \alu_cr0_cr_op__write_cr_whole$next \alu_cr0_cr_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_cr0_cr_op__write_cr_whole$next \alu_cr0_cr_op__read_cr_whole$next \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__insn_type$next } { \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__insn_type$next } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } end sync init update \alu_cr0_cr_op__insn_type 7'0000000 update \alu_cr0_cr_op__fn_unit 11'00000000000 update \alu_cr0_cr_op__insn 32'00000000000000000000000000000000 - update \alu_cr0_cr_op__read_cr_whole 1'0 - update \alu_cr0_cr_op__write_cr_whole 1'0 sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type \alu_cr0_cr_op__insn_type$next update \alu_cr0_cr_op__fn_unit \alu_cr0_cr_op__fn_unit$next update \alu_cr0_cr_op__insn \alu_cr0_cr_op__insn$next - update \alu_cr0_cr_op__read_cr_whole \alu_cr0_cr_op__read_cr_whole$next - update \alu_cr0_cr_op__write_cr_whole \alu_cr0_cr_op__write_cr_whole$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o @@ -14093,7 +14484,7 @@ module \cr0 wire width 1 \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 1 \data_r0__o_ok$next - process $group_32 + process $group_30 assign \data_r0__o$next \data_r0__o assign \data_r0__o_ok$next \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" @@ -14128,7 +14519,7 @@ module \cr0 wire width 1 \data_r1__full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 1 \data_r1__full_cr_ok$next - process $group_34 + process $group_32 assign \data_r1__full_cr$next \data_r1__full_cr assign \data_r1__full_cr_ok$next \data_r1__full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" @@ -14163,7 +14554,7 @@ module \cr0 wire width 1 \data_r2__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 1 \data_r2__cr_a_ok$next - process $group_36 + process $group_34 assign \data_r2__cr_a$next \data_r2__cr_a assign \data_r2__cr_a_ok$next \data_r2__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" @@ -14229,7 +14620,7 @@ module \cr0 connect \B \cu_busy_o connect \Y $75 end - process $group_38 + process $group_36 assign \cu_wrmask_o 3'000 assign \cu_wrmask_o { $75 $73 $71 } sync init @@ -14248,12 +14639,12 @@ module \cr0 connect \S \src_l_q_src [0] connect \Y $77 end - process $group_39 + process $group_37 assign \alu_cr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 assign \alu_cr0_ra $77 sync init end - process $group_40 + process $group_38 assign \src_r0$next \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } @@ -14280,12 +14671,12 @@ module \cr0 connect \S \src_l_q_src [1] connect \Y $79 end - process $group_41 + process $group_39 assign \alu_cr0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 assign \alu_cr0_rb $79 sync init end - process $group_42 + process $group_40 assign \src_r1$next \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [1] } @@ -14312,12 +14703,12 @@ module \cr0 connect \S \src_l_q_src [2] connect \Y $81 end - process $group_43 + process $group_41 assign \alu_cr0_full_cr$1 32'00000000000000000000000000000000 assign \alu_cr0_full_cr$1 $81 sync init end - process $group_44 + process $group_42 assign \src_r2$next \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } @@ -14344,12 +14735,12 @@ module \cr0 connect \S \src_l_q_src [3] connect \Y $83 end - process $group_45 + process $group_43 assign \alu_cr0_cr_a$2 4'0000 assign \alu_cr0_cr_a$2 $83 sync init end - process $group_46 + process $group_44 assign \src_r3$next \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [3] } @@ -14376,12 +14767,12 @@ module \cr0 connect \S \src_l_q_src [4] connect \Y $85 end - process $group_47 + process $group_45 assign \alu_cr0_cr_b 4'0000 assign \alu_cr0_cr_b $85 sync init end - process $group_48 + process $group_46 assign \src_r4$next \src_r4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [4] } @@ -14408,12 +14799,12 @@ module \cr0 connect \S \src_l_q_src [5] connect \Y $87 end - process $group_49 + process $group_47 assign \alu_cr0_cr_c 4'0000 assign \alu_cr0_cr_c $87 sync init end - process $group_50 + process $group_48 assign \src_r5$next \src_r5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [5] } @@ -14426,7 +14817,7 @@ module \cr0 sync posedge \coresync_clk update \src_r5 \src_r5$next end - process $group_51 + process $group_49 assign \alu_cr0_p_valid_i 1'0 assign \alu_cr0_p_valid_i \alui_l_q_alui sync init @@ -14444,7 +14835,7 @@ module \cr0 connect \B \alui_l_q_alui connect \Y $89 end - process $group_52 + process $group_50 assign \alui_l_r_alui$next \alui_l_r_alui assign \alui_l_r_alui$next $89 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -14457,12 +14848,12 @@ module \cr0 sync posedge \coresync_clk update \alui_l_r_alui \alui_l_r_alui$next end - process $group_53 + process $group_51 assign \alui_l_s_alui 1'0 assign \alui_l_s_alui \all_rd_pulse sync init end - process $group_54 + process $group_52 assign \alu_cr0_n_ready_i 1'0 assign \alu_cr0_n_ready_i \alu_l_q_alu sync init @@ -14480,7 +14871,7 @@ module \cr0 connect \B \alu_l_q_alu connect \Y $91 end - process $group_55 + process $group_53 assign \alu_l_r_alu$next \alu_l_r_alu assign \alu_l_r_alu$next $91 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -14493,12 +14884,12 @@ module \cr0 sync posedge \coresync_clk update \alu_l_r_alu \alu_l_r_alu$next end - process $group_56 + process $group_54 assign \alu_l_s_alu 1'0 assign \alu_l_s_alu \all_rd_pulse sync init end - process $group_57 + process $group_55 assign \cu_busy_o 1'0 assign \cu_busy_o \opc_l_q_opc sync init @@ -14552,7 +14943,7 @@ module \cr0 connect \B $97 connect \Y $99 end - process $group_58 + process $group_56 assign \cu_rd__rel_o 6'000000 assign \cu_rd__rel_o $99 sync init @@ -14624,7 +15015,7 @@ module \cr0 connect \B \cu_wrmask_o connect \Y $109 end - process $group_59 + process $group_57 assign \cu_wr__rel_o 3'000 assign \cu_wr__rel_o $109 sync init @@ -14642,7 +15033,7 @@ module \cr0 connect \B \cu_busy_o connect \Y $111 end - process $group_60 + process $group_58 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch { $111 } @@ -14665,7 +15056,7 @@ module \cr0 connect \B \cu_busy_o connect \Y $113 end - process $group_61 + process $group_59 assign \dest2_o 32'00000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch { $113 } @@ -14688,7 +15079,7 @@ module \cr0 connect \B \cu_busy_o connect \Y $115 end - process $group_62 + process $group_60 assign \dest3_o 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch { $115 } @@ -14912,9 +15303,9 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__imm_data__imm + wire width 64 input 5 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \br_op__imm_data__imm_ok + wire width 1 input 6 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -15021,9 +15412,9 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 16 \br_op__insn$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 17 \br_op__imm_data__imm$6 + wire width 64 output 17 \br_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \br_op__imm_data__imm_ok$7 + wire width 1 output 18 \br_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 19 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -15100,17 +15491,24 @@ module \main$22 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" - wire width 2 \bi + wire width 5 \bo process $group_1 + assign \bo 5'00000 + assign \bo { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" + wire width 2 \bi + process $group_2 assign \bi 2'00 - assign \bi { \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] } [1:0] + assign \bi { \br_op__insn [17] \br_op__insn [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" wire width 1 \cr_bit - process $group_2 + process $group_3 assign \cr_bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:108" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" switch \bi case 2'00 assign \cr_bit \cr_a [3] @@ -15123,26 +15521,26 @@ module \main$22 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:111" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" wire width 1 \ctr_write - process $group_3 + process $group_4 assign \ctr_write 1'0 assign \ctr_write 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch { \bo [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" case assign \ctr_write 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" wire width 1 \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15150,12 +15548,12 @@ module \main$22 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [3] + connect \B \bo [3] connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" cell $or $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15163,53 +15561,53 @@ module \main$22 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $19 - connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4] + connect \B \bo [4] connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" cell $eq $24 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3] + connect \A \bo [4:3] connect \B 1'0 connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" cell $eq $26 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3] + connect \A \bo [4:3] connect \B 1'1 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4] + connect \A \bo [4] connect \B 1'1 connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" wire width 1 \ctr_zero_bo1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" cell $not $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15217,9 +15615,9 @@ module \main$22 connect \A \cr_bit connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" cell $and $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15230,9 +15628,9 @@ module \main$22 connect \B $29 connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" cell $and $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15243,37 +15641,37 @@ module \main$22 connect \B \cr_bit connect \Y $33 end - process $group_4 + process $group_5 assign \bc_taken 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch { \bo [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" case 1'1 assign \bc_taken $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" switch { $27 $25 $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" case 3'--1 assign \bc_taken $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" case 3'-1- assign \bc_taken $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" case 3'1-- assign \bc_taken \ctr_zero_bo1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" wire width 64 \ctr_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" wire width 65 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" wire width 65 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" cell $sub $37 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -15285,31 +15683,31 @@ module \main$22 connect \Y $36 end connect $35 $36 - process $group_5 + process $group_6 assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch { \bo [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" case assign \ctr_n $35 [63:0] end sync init end - process $group_6 + process $group_7 assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch { \bo [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" case assign \fast1$10 \ctr_n end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" wire width 64 \ctr_m attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 $38 @@ -15321,64 +15719,64 @@ module \main$22 connect \A \fast1 [31:0] connect \Y $38 end - process $group_7 + process $group_8 assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch { \bo [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" switch { \br_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" case 1'1 assign \ctr_m $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" case assign \ctr_m \fast1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" cell $reduce_or $41 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 - connect \A \ctr_m + connect \A \ctr_n connect \Y $40 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" cell $xor $43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [1] + connect \A \bo [1] connect \B $40 connect \Y $42 end - process $group_8 + process $group_9 assign \ctr_zero_bo1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch { \bo [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" case assign \ctr_zero_bo1 $42 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" cell $not $45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15386,9 +15784,9 @@ module \main$22 connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [5] connect \Y $44 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" cell $and $47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -15399,27 +15797,27 @@ module \main$22 connect \B $44 connect \Y $46 end - process $group_9 + process $group_10 assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" attribute \nmigen.decoding "OP_B/6" case 7'0000110 assign \br_imm_addr { { { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] } { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 assign \br_imm_addr { { { { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] } { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" switch { $46 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" case 1'1 assign \br_imm_addr { \fast1 [63:2] 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:162" case assign \br_imm_addr { \fast2 [63:2] 2'00 } end @@ -15428,58 +15826,58 @@ module \main$22 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" wire width 1 \br_taken - process $group_10 + process $group_11 assign \br_taken 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" attribute \nmigen.decoding "OP_B/6" case 7'0000110 assign \br_taken 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 assign \br_taken \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 assign \br_taken \bc_taken end sync init end - process $group_11 + process $group_12 assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" attribute \nmigen.decoding "OP_B/6" case 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 assign \fast1_ok \ctr_write - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 assign \fast1_ok \ctr_write end sync init end - process $group_12 + process $group_13 assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 assign \nia \br_addr sync init end - process $group_13 + process $group_14 assign \nia_ok 1'0 assign \nia_ok \br_taken sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" wire width 65 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" wire width 65 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" cell $add $50 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -15491,50 +15889,50 @@ module \main$22 connect \Y $49 end connect $48 $49 - process $group_14 + process $group_15 assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" switch { \br_op__lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" case 1'1 assign \fast2$11 $48 [63:0] end sync init end - process $group_15 + process $group_16 assign \fast2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" switch { \br_op__lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" case 1'1 assign \fast2_ok 1'1 end sync init end - process $group_16 + process $group_17 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_17 + process $group_18 assign \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 assign \br_op__insn_type$3 7'0000000 assign \br_op__fn_unit$4 11'00000000000 assign \br_op__insn$5 32'00000000000000000000000000000000 - assign \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$7 1'0 + assign \br_op__imm_data__data$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__ok$7 1'0 assign \br_op__lk$8 1'0 assign \br_op__is_32bit$9 1'0 - assign { \br_op__is_32bit$9 \br_op__lk$8 { \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm$6 } \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + assign { \br_op__is_32bit$9 \br_op__lk$8 { \br_op__imm_data__ok$7 \br_op__imm_data__data$6 } \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__ok \br_op__imm_data__data } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" module \pipe$19 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -15636,9 +16034,9 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 8 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \br_op__imm_data__imm + wire width 64 input 9 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \br_op__imm_data__imm_ok + wire width 1 input 10 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -15759,13 +16157,13 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \br_op__insn$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \br_op__imm_data__imm$6 + wire width 64 output 23 \br_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__imm$6$next + wire width 64 \br_op__imm_data__data$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \br_op__imm_data__imm_ok$7 + wire width 1 output 24 \br_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__imm_ok$7$next + wire width 1 \br_op__imm_data__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -15902,9 +16300,9 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__imm + wire width 64 \main_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__imm_data__imm_ok + wire width 1 \main_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -16011,9 +16409,9 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_br_op__insn$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__imm$17 + wire width 64 \main_br_op__imm_data__data$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__imm_data__imm_ok$18 + wire width 1 \main_br_op__imm_data__ok$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_br_op__lk$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -16036,8 +16434,8 @@ module \pipe$19 connect \br_op__insn_type \main_br_op__insn_type connect \br_op__fn_unit \main_br_op__fn_unit connect \br_op__insn \main_br_op__insn - connect \br_op__imm_data__imm \main_br_op__imm_data__imm - connect \br_op__imm_data__imm_ok \main_br_op__imm_data__imm_ok + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__ok \main_br_op__imm_data__ok connect \br_op__lk \main_br_op__lk connect \br_op__is_32bit \main_br_op__is_32bit connect \fast1 \main_fast1 @@ -16048,8 +16446,8 @@ module \pipe$19 connect \br_op__insn_type$3 \main_br_op__insn_type$14 connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 connect \br_op__insn$5 \main_br_op__insn$16 - connect \br_op__imm_data__imm$6 \main_br_op__imm_data__imm$17 - connect \br_op__imm_data__imm_ok$7 \main_br_op__imm_data__imm_ok$18 + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 connect \br_op__lk$8 \main_br_op__lk$19 connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 connect \fast1$10 \main_fast1$21 @@ -16069,11 +16467,11 @@ module \pipe$19 assign \main_br_op__insn_type 7'0000000 assign \main_br_op__fn_unit 11'00000000000 assign \main_br_op__insn 32'00000000000000000000000000000000 - assign \main_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_br_op__imm_data__imm_ok 1'0 + assign \main_br_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_br_op__imm_data__ok 1'0 assign \main_br_op__lk 1'0 assign \main_br_op__is_32bit 1'0 - assign { \main_br_op__is_32bit \main_br_op__lk { \main_br_op__imm_data__imm_ok \main_br_op__imm_data__imm } \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + assign { \main_br_op__is_32bit \main_br_op__lk { \main_br_op__imm_data__ok \main_br_op__imm_data__data } \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__ok \br_op__imm_data__data } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } sync init end process $group_9 @@ -16226,9 +16624,9 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \br_op__insn$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__imm$31 + wire width 64 \br_op__imm_data__data$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__imm_ok$32 + wire width 1 \br_op__imm_data__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \br_op__lk$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -16238,11 +16636,11 @@ module \pipe$19 assign \br_op__insn_type$28 7'0000000 assign \br_op__fn_unit$29 11'00000000000 assign \br_op__insn$30 32'00000000000000000000000000000000 - assign \br_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$32 1'0 + assign \br_op__imm_data__data$31 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__ok$32 1'0 assign \br_op__lk$33 1'0 assign \br_op__is_32bit$34 1'0 - assign { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 { \main_br_op__imm_data__imm_ok$18 \main_br_op__imm_data__imm$17 } \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + assign { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__ok$32 \br_op__imm_data__data$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 { \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 } \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -16321,32 +16719,32 @@ module \pipe$19 assign \br_op__insn_type$3$next \br_op__insn_type$3 assign \br_op__fn_unit$4$next \br_op__fn_unit$4 assign \br_op__insn$5$next \br_op__insn$5 - assign \br_op__imm_data__imm$6$next \br_op__imm_data__imm$6 - assign \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm_ok$7 + assign \br_op__imm_data__data$6$next \br_op__imm_data__data$6 + assign \br_op__imm_data__ok$7$next \br_op__imm_data__ok$7 assign \br_op__lk$8$next \br_op__lk$8 assign \br_op__is_32bit$9$next \br_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__ok$7$next \br_op__imm_data__data$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__ok$32 \br_op__imm_data__data$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__ok$7$next \br_op__imm_data__data$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__ok$32 \br_op__imm_data__data$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \br_op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$7$next 1'0 + assign \br_op__imm_data__data$6$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__ok$7$next 1'0 end sync init update \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 update \br_op__insn_type$3 7'0000000 update \br_op__fn_unit$4 11'00000000000 update \br_op__insn$5 32'00000000000000000000000000000000 - update \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \br_op__imm_data__imm_ok$7 1'0 + update \br_op__imm_data__data$6 64'0000000000000000000000000000000000000000000000000000000000000000 + update \br_op__imm_data__ok$7 1'0 update \br_op__lk$8 1'0 update \br_op__is_32bit$9 1'0 sync posedge \coresync_clk @@ -16354,8 +16752,8 @@ module \pipe$19 update \br_op__insn_type$3 \br_op__insn_type$3$next update \br_op__fn_unit$4 \br_op__fn_unit$4$next update \br_op__insn$5 \br_op__insn$5$next - update \br_op__imm_data__imm$6 \br_op__imm_data__imm$6$next - update \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm_ok$7$next + update \br_op__imm_data__data$6 \br_op__imm_data__data$6$next + update \br_op__imm_data__ok$7 \br_op__imm_data__ok$7$next update \br_op__lk$8 \br_op__lk$8$next update \br_op__is_32bit$9 \br_op__is_32bit$9$next end @@ -16445,7 +16843,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" module \alu_branch0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \fast1_ok @@ -16453,7 +16851,7 @@ module \alu_branch0 wire width 1 output 2 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 3 \nia_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 4 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 5 \n_valid_o @@ -16553,9 +16951,9 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 10 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \br_op__imm_data__imm + wire width 64 input 11 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \br_op__imm_data__imm_ok + wire width 1 input 12 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -16684,9 +17082,9 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__imm + wire width 64 \pipe_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__imm_data__imm_ok + wire width 1 \pipe_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -16797,9 +17195,9 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_br_op__insn$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__imm$8 + wire width 64 \pipe_br_op__imm_data__data$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__imm_data__imm_ok$9 + wire width 1 \pipe_br_op__imm_data__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_br_op__lk$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -16826,8 +17224,8 @@ module \alu_branch0 connect \br_op__insn_type \pipe_br_op__insn_type connect \br_op__fn_unit \pipe_br_op__fn_unit connect \br_op__insn \pipe_br_op__insn - connect \br_op__imm_data__imm \pipe_br_op__imm_data__imm - connect \br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm_ok + connect \br_op__imm_data__data \pipe_br_op__imm_data__data + connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok connect \br_op__lk \pipe_br_op__lk connect \br_op__is_32bit \pipe_br_op__is_32bit connect \fast1 \pipe_fast1 @@ -16840,8 +17238,8 @@ module \alu_branch0 connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 connect \br_op__insn$5 \pipe_br_op__insn$7 - connect \br_op__imm_data__imm$6 \pipe_br_op__imm_data__imm$8 - connect \br_op__imm_data__imm_ok$7 \pipe_br_op__imm_data__imm_ok$9 + connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 + connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 connect \br_op__lk$8 \pipe_br_op__lk$10 connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 connect \fast1$10 \pipe_fast1$12 @@ -16873,11 +17271,11 @@ module \alu_branch0 assign \pipe_br_op__insn_type 7'0000000 assign \pipe_br_op__fn_unit 11'00000000000 assign \pipe_br_op__insn 32'00000000000000000000000000000000 - assign \pipe_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_br_op__imm_data__imm_ok 1'0 + assign \pipe_br_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_br_op__imm_data__ok 1'0 assign \pipe_br_op__lk 1'0 assign \pipe_br_op__is_32bit 1'0 - assign { \pipe_br_op__is_32bit \pipe_br_op__lk { \pipe_br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm } \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + assign { \pipe_br_op__is_32bit \pipe_br_op__lk { \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data } \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__ok \br_op__imm_data__data } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } sync init end process $group_11 @@ -17006,9 +17404,9 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \br_op__insn$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__imm$19 + wire width 64 \br_op__imm_data__data$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__imm_ok$20 + wire width 1 \br_op__imm_data__ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \br_op__lk$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -17018,11 +17416,11 @@ module \alu_branch0 assign \br_op__insn_type$16 7'0000000 assign \br_op__fn_unit$17 11'00000000000 assign \br_op__insn$18 32'00000000000000000000000000000000 - assign \br_op__imm_data__imm$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$20 1'0 + assign \br_op__imm_data__data$19 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__ok$20 1'0 assign \br_op__lk$21 1'0 assign \br_op__is_32bit$22 1'0 - assign { \br_op__is_32bit$22 \br_op__lk$21 { \br_op__imm_data__imm_ok$20 \br_op__imm_data__imm$19 } \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 { \pipe_br_op__imm_data__imm_ok$9 \pipe_br_op__imm_data__imm$8 } \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + assign { \br_op__is_32bit$22 \br_op__lk$21 { \br_op__imm_data__ok$20 \br_op__imm_data__data$19 } \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 { \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 } \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } sync init end process $group_25 @@ -17048,9 +17446,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" module \src_l$23 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src @@ -17193,9 +17591,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" module \opc_l$24 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -17338,9 +17736,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" module \req_l$25 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req @@ -17483,9 +17881,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" module \rst_l$26 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -17628,9 +18026,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" module \rok_l$27 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -17773,9 +18171,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" module \alui_l$28 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -17918,9 +18316,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" module \alu_l$29 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -18063,7 +18461,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" module \branch0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 1 \oper_i_alu_branch0__cia @@ -18159,9 +18557,9 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_branch0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_branch0__imm_data__imm + wire width 64 input 5 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_branch0__imm_data__imm_ok + wire width 1 input 6 \oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \oper_i_alu_branch0__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -18198,7 +18596,7 @@ module \branch0 wire width 1 output 23 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 24 \dest3_o - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 25 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_branch0_n_valid_o @@ -18306,13 +18704,13 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_branch0_br_op__insn$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__imm + wire width 64 \alu_branch0_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__imm$next + wire width 64 \alu_branch0_br_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__imm_data__imm_ok + wire width 1 \alu_branch0_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__imm_data__imm_ok$next + wire width 1 \alu_branch0_br_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_branch0_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -18349,8 +18747,8 @@ module \branch0 connect \br_op__insn_type \alu_branch0_br_op__insn_type connect \br_op__fn_unit \alu_branch0_br_op__fn_unit connect \br_op__insn \alu_branch0_br_op__insn - connect \br_op__imm_data__imm \alu_branch0_br_op__imm_data__imm - connect \br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm_ok + connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data + connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok connect \br_op__lk \alu_branch0_br_op__lk connect \br_op__is_32bit \alu_branch0_br_op__is_32bit connect \fast1 \alu_branch0_fast1 @@ -19170,29 +19568,29 @@ module \branch0 assign \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__insn_type assign \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__fn_unit assign \alu_branch0_br_op__insn$next \alu_branch0_br_op__insn - assign \alu_branch0_br_op__imm_data__imm$next \alu_branch0_br_op__imm_data__imm - assign \alu_branch0_br_op__imm_data__imm_ok$next \alu_branch0_br_op__imm_data__imm_ok + assign \alu_branch0_br_op__imm_data__data$next \alu_branch0_br_op__imm_data__data + assign \alu_branch0_br_op__imm_data__ok$next \alu_branch0_br_op__imm_data__ok assign \alu_branch0_br_op__lk$next \alu_branch0_br_op__lk assign \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__lk$next { \alu_branch0_br_op__imm_data__imm_ok$next \alu_branch0_br_op__imm_data__imm$next } \alu_branch0_br_op__insn$next \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + assign { \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__lk$next { \alu_branch0_br_op__imm_data__ok$next \alu_branch0_br_op__imm_data__data$next } \alu_branch0_br_op__insn$next \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_branch0_br_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_br_op__imm_data__imm_ok$next 1'0 + assign \alu_branch0_br_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_br_op__imm_data__ok$next 1'0 end sync init update \alu_branch0_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 update \alu_branch0_br_op__insn_type 7'0000000 update \alu_branch0_br_op__fn_unit 11'00000000000 update \alu_branch0_br_op__insn 32'00000000000000000000000000000000 - update \alu_branch0_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_branch0_br_op__imm_data__imm_ok 1'0 + update \alu_branch0_br_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_branch0_br_op__imm_data__ok 1'0 update \alu_branch0_br_op__lk 1'0 update \alu_branch0_br_op__is_32bit 1'0 sync posedge \coresync_clk @@ -19200,8 +19598,8 @@ module \branch0 update \alu_branch0_br_op__insn_type \alu_branch0_br_op__insn_type$next update \alu_branch0_br_op__fn_unit \alu_branch0_br_op__fn_unit$next update \alu_branch0_br_op__insn \alu_branch0_br_op__insn$next - update \alu_branch0_br_op__imm_data__imm \alu_branch0_br_op__imm_data__imm$next - update \alu_branch0_br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm_ok$next + update \alu_branch0_br_op__imm_data__data \alu_branch0_br_op__imm_data__data$next + update \alu_branch0_br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok$next update \alu_branch0_br_op__lk \alu_branch0_br_op__lk$next update \alu_branch0_br_op__is_32bit \alu_branch0_br_op__is_32bit$next end @@ -19363,7 +19761,7 @@ module \branch0 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc - connect \S \alu_branch0_br_op__imm_data__imm_ok + connect \S \alu_branch0_br_op__imm_data__ok connect \Y $77 end process $group_42 @@ -19379,8 +19777,8 @@ module \branch0 cell $mux $80 parameter \WIDTH 64 connect \A \src2_i - connect \B \alu_branch0_br_op__imm_data__imm - connect \S \alu_branch0_br_op__imm_data__imm_ok + connect \B \alu_branch0_br_op__imm_data__data + connect \S \alu_branch0_br_op__imm_data__ok connect \Y $79 end process $group_43 @@ -19581,7 +19979,7 @@ module \branch0 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_branch0_br_op__imm_data__imm_ok + connect \A \alu_branch0_br_op__imm_data__ok connect \Y $93 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -19984,7 +20382,7 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 6 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 7 \trap_op__traptype + wire width 7 input 7 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 8 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -20095,7 +20493,7 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 19 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 output 20 \trap_op__traptype$8 + wire width 7 output 20 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 output 21 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -20342,7 +20740,7 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" cell $reduce_or $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \Y $30 @@ -20401,17 +20799,17 @@ module \main$35 case 1'1 assign \nia $34 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 assign \nia { { { } \fast1 [63:2] } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000 @@ -20431,28 +20829,28 @@ module \main$35 case 1'1 assign \nia_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 assign \nia_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \nia_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" wire width 65 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" wire width 65 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" cell $add $40 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -20477,16 +20875,16 @@ module \main$35 case 1'1 assign \fast1$10 \trap_op__cia end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \fast1$10 $38 [63:0] @@ -20506,16 +20904,16 @@ module \main$35 case 1'1 assign \fast1_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \fast1_ok 1'1 @@ -20527,7 +20925,7 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" cell $eq $42 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 @@ -20538,14 +20936,14 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire width 1 $43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - wire width 5 $44 + wire width 7 $44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" cell $and $45 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 5 + parameter \Y_WIDTH 7 connect \A \trap_op__traptype connect \B 2'10 connect \Y $44 @@ -20553,7 +20951,7 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_bool $46 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A $44 connect \Y $43 @@ -20561,14 +20959,14 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire width 1 $47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - wire width 5 $48 + wire width 7 $48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" cell $and $49 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 + parameter \Y_WIDTH 7 connect \A \trap_op__traptype connect \B 1'1 connect \Y $48 @@ -20576,7 +20974,7 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_bool $50 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A $48 connect \Y $47 @@ -20584,14 +20982,14 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire width 1 $51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - wire width 5 $52 + wire width 7 $52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" cell $and $53 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 + parameter \Y_WIDTH 7 connect \A \trap_op__traptype connect \B 4'1000 connect \Y $52 @@ -20599,30 +20997,30 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_bool $54 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A $52 connect \Y $51 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" - wire width 5 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + wire width 7 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" cell $and $57 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \trap_op__traptype - connect \B 5'10000 + connect \B 7'1000000 connect \Y $56 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_bool $58 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A $56 connect \Y $55 @@ -20666,23 +21064,23 @@ module \main$35 case 1'1 assign \fast2$11 [16] 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" case 1'1 assign \fast2$11 [19] 1'1 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -20706,16 +21104,16 @@ module \main$35 assign \fast2_ok 1'1 assign \fast2_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \fast2_ok 1'1 @@ -20732,20 +21130,10 @@ module \main$35 connect \A \trap_op__msr connect \Y $59 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \trap_op__insn [22] \trap_op__insn [21] } - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - cell $eq $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + cell $eq $62 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -20753,12 +21141,12 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $63 + connect \Y $61 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - cell $eq $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" + cell $eq $64 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -20766,12 +21154,12 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $65 + connect \Y $63 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - cell $eq $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + cell $eq $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -20779,45 +21167,45 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $67 + connect \Y $65 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - cell $and $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + cell $and $68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $65 - connect \B $67 - connect \Y $69 + connect \A $63 + connect \B $65 + connect \Y $67 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $not $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + cell $not $70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $71 + connect \Y $69 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" - cell $not $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + cell $not $72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $73 + connect \Y $71 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:280" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:280" - cell $eq $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" + cell $eq $74 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -20825,12 +21213,12 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $75 + connect \Y $73 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - cell $eq $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + cell $eq $76 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -20838,20 +21226,20 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $77 + connect \Y $75 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - cell $and $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + cell $and $78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $75 - connect \B $77 - connect \Y $79 + connect \A $73 + connect \B $75 + connect \Y $77 end process $group_18 assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -20885,32 +21273,32 @@ module \main$35 assign \msr [58] 1'0 assign \msr_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 assign { \msr_ok \msr } $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" + switch { { \trap_op__insn [21] } } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" case 1'1 assign \msr [1] \ra [1] assign \msr [15] \ra [15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:222" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" case 1'1 assign \msr [11:1] \ra [11:1] assign \msr [59:13] \ra [59:13] assign \msr [63:61] \ra [63:61] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + switch { $67 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" case 1'1 assign \msr [34:32] \trap_op__msr [34:32] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" case assign \msr [11:1] \ra [11:1] assign \msr [31:13] \ra [31:13] @@ -20924,9 +21312,9 @@ module \main$35 assign \msr [4] 1'1 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" case 1'1 assign \msr [60] \trap_op__msr [60] assign \msr [12] \trap_op__msr [12] @@ -20935,25 +21323,25 @@ module \main$35 case assign \msr_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 assign \msr [15:0] \fast2 [15:0] assign \msr [26:22] \fast2 [26:22] assign \msr [63:31] \fast2 [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" switch { \trap_op__msr [60] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" case 1'1 assign { \msr_ok \msr } [12] \fast2 [12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:276" case assign { \msr_ok \msr } [12] \trap_op__msr [12] end @@ -20966,9 +21354,9 @@ module \main$35 assign \msr [5] 1'1 assign \msr [4] 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + switch { $77 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" case 1'1 assign \msr [34:32] \trap_op__msr [34:32] end @@ -20976,7 +21364,7 @@ module \main$35 case assign \msr_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 assign \msr \trap_op__msr @@ -21008,17 +21396,17 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 assign \o \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 end @@ -21031,17 +21419,17 @@ module \main$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" attribute \nmigen.decoding "OP_SC/73" case 7'1001001 end @@ -21059,7 +21447,7 @@ module \main$35 assign \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 assign \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 assign \trap_op__is_32bit$7 1'0 - assign \trap_op__traptype$8 5'00000 + assign \trap_op__traptype$8 7'0000000 assign \trap_op__trapaddr$9 13'0000000000000 assign { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } sync init @@ -21068,9 +21456,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" module \pipe$32 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -21176,7 +21564,7 @@ module \pipe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 11 \trap_op__traptype + wire width 7 input 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -21305,9 +21693,9 @@ module \pipe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \trap_op__is_32bit$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 output 26 \trap_op__traptype$8 + wire width 7 output 26 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \trap_op__traptype$8$next + wire width 7 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 output 27 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -21460,7 +21848,7 @@ module \pipe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \main_trap_op__traptype + wire width 7 \main_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \main_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -21571,7 +21959,7 @@ module \pipe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_trap_op__is_32bit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \main_trap_op__traptype$19 + wire width 7 \main_trap_op__traptype$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \main_trap_op__trapaddr$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -21640,7 +22028,7 @@ module \pipe$32 assign \main_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_trap_op__is_32bit 1'0 - assign \main_trap_op__traptype 5'00000 + assign \main_trap_op__traptype 7'0000000 assign \main_trap_op__trapaddr 13'0000000000000 assign { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } sync init @@ -21804,7 +22192,7 @@ module \pipe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \trap_op__is_32bit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \trap_op__traptype$33 + wire width 7 \trap_op__traptype$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$34 process $group_17 @@ -21814,7 +22202,7 @@ module \pipe$32 assign \trap_op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000 assign \trap_op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000 assign \trap_op__is_32bit$32 1'0 - assign \trap_op__traptype$33 5'00000 + assign \trap_op__traptype$33 7'0000000 assign \trap_op__trapaddr$34 13'0000000000000 assign { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } sync init @@ -21935,7 +22323,7 @@ module \pipe$32 update \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 update \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 update \trap_op__is_32bit$7 1'0 - update \trap_op__traptype$8 5'00000 + update \trap_op__traptype$8 7'0000000 update \trap_op__trapaddr$9 13'0000000000000 sync posedge \coresync_clk update \trap_op__insn_type$2 \trap_op__insn_type$2$next @@ -22081,7 +22469,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" module \alu_trap0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -22093,7 +22481,7 @@ module \alu_trap0 wire width 1 output 4 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 5 \msr_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 6 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 7 \n_valid_o @@ -22197,7 +22585,7 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 14 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 15 \trap_op__traptype + wire width 7 input 15 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 16 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -22334,7 +22722,7 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \pipe_trap_op__traptype + wire width 7 \pipe_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \pipe_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -22449,7 +22837,7 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_trap_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \pipe_trap_op__traptype$10 + wire width 7 \pipe_trap_op__traptype$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \pipe_trap_op__trapaddr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -22536,7 +22924,7 @@ module \alu_trap0 assign \pipe_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_trap_op__is_32bit 1'0 - assign \pipe_trap_op__traptype 5'00000 + assign \pipe_trap_op__traptype 7'0000000 assign \pipe_trap_op__trapaddr 13'0000000000000 assign { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } sync init @@ -22676,7 +23064,7 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \trap_op__is_32bit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \trap_op__traptype$21 + wire width 7 \trap_op__traptype$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$22 process $group_18 @@ -22686,7 +23074,7 @@ module \alu_trap0 assign \trap_op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000 assign \trap_op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000 assign \trap_op__is_32bit$20 1'0 - assign \trap_op__traptype$21 5'00000 + assign \trap_op__traptype$21 7'0000000 assign \trap_op__trapaddr$22 13'0000000000000 assign { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } sync init @@ -22726,9 +23114,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" module \src_l$36 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 input 2 \s_src @@ -22871,9 +23259,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" module \opc_l$37 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -23016,9 +23404,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" module \req_l$38 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 output 2 \q_req @@ -23161,9 +23549,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" module \rst_l$39 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -23306,9 +23694,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" module \rok_l$40 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -23451,9 +23839,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" module \alui_l$41 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -23596,9 +23984,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" module \alu_l$42 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -23741,7 +24129,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" module \trap0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23841,7 +24229,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 6 \oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 7 \oper_i_alu_trap0__traptype + wire width 7 input 7 \oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 8 \oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" @@ -23886,7 +24274,7 @@ module \trap0 wire width 1 output 28 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 29 \dest5_o - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 30 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_trap0_n_valid_o @@ -24002,9 +24390,9 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_trap0_trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \alu_trap0_trap_op__traptype + wire width 7 \alu_trap0_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \alu_trap0_trap_op__traptype$next + wire width 7 \alu_trap0_trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \alu_trap0_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -24886,7 +25274,7 @@ module \trap0 update \alu_trap0_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 update \alu_trap0_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 update \alu_trap0_trap_op__is_32bit 1'0 - update \alu_trap0_trap_op__traptype 5'00000 + update \alu_trap0_trap_op__traptype 7'0000000 update \alu_trap0_trap_op__trapaddr 13'0000000000000 sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type \alu_trap0_trap_op__insn_type$next @@ -25825,17 +26213,17 @@ module \input$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -25864,8 +26252,10 @@ module \input$47 wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 22 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -25940,7 +26330,7 @@ module \input$47 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \logical_op__insn_type$2 + wire width 7 output 23 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -25954,47 +26344,49 @@ module \input$47 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \logical_op__fn_unit$3 + wire width 11 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \logical_op__imm_data__imm$4 + wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \logical_op__imm_data__imm_ok$5 + wire width 1 output 26 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__rc__rc$6 + wire width 1 output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc_ok$7 + wire width 1 output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__oe__oe$8 + wire width 1 output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe_ok$9 + wire width 1 output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__invert_in$10 + wire width 1 output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__zero_a$11 + wire width 1 output 32 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \logical_op__input_carry$12 + wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__invert_out$13 + wire width 1 output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__write_cr0$14 + wire width 1 output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__output_carry$15 + wire width 1 output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__is_32bit$16 + wire width 1 output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_signed$17 + wire width 1 output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 38 \logical_op__data_len$18 + wire width 4 output 39 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 39 \logical_op__insn$19 + wire width 32 output 40 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 40 \ra$20 + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \rb$21 + wire width 1 output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a process $group_0 @@ -26010,14 +26402,14 @@ module \input$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - wire width 64 $22 + wire width 64 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $23 + cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $22 + connect \Y $23 end process $group_2 assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -26025,7 +26417,7 @@ module \input$47 switch { \logical_op__invert_in } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" case 1'1 - assign \b $22 + assign \b $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" case assign \b \rb @@ -26038,19 +26430,24 @@ module \input$47 sync init end process $group_4 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_5 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_5 + process $group_6 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -26061,7 +26458,7 @@ module \input$47 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end end @@ -32138,17 +32535,17 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -32177,8 +32574,10 @@ module \main$48 wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 22 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -32253,7 +32652,7 @@ module \main$48 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \logical_op__insn_type$2 + wire width 7 output 23 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -32267,47 +32666,49 @@ module \main$48 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \logical_op__fn_unit$3 + wire width 11 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \logical_op__imm_data__imm$4 + wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \logical_op__imm_data__imm_ok$5 + wire width 1 output 26 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__rc__rc$6 + wire width 1 output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc_ok$7 + wire width 1 output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__oe__oe$8 + wire width 1 output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe_ok$9 + wire width 1 output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__invert_in$10 + wire width 1 output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__zero_a$11 + wire width 1 output 32 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \logical_op__input_carry$12 + wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__invert_out$13 + wire width 1 output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__write_cr0$14 + wire width 1 output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__output_carry$15 + wire width 1 output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__is_32bit$16 + wire width 1 output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_signed$17 + wire width 1 output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 38 \logical_op__data_len$18 + wire width 4 output 39 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 39 \logical_op__insn$19 + wire width 32 output 40 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 41 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 40 \o + wire width 1 output 42 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 41 \o_ok + wire width 1 output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 \bpermd_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" @@ -32339,9 +32740,9 @@ module \main$48 connect \lz \clz_lz end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - wire width 64 $20 + wire width 64 $21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $21 + cell $and $22 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -32349,12 +32750,12 @@ module \main$48 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $20 + connect \Y $21 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - wire width 64 $22 + wire width 64 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $23 + cell $or $24 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -32362,12 +32763,12 @@ module \main$48 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $22 + connect \Y $23 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - wire width 64 $24 + wire width 64 $25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $25 + cell $xor $26 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -32375,12 +32776,12 @@ module \main$48 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $24 + connect \Y $25 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $26 + wire width 1 $27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $27 + cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32388,12 +32789,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $26 + connect \Y $27 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $28 + wire width 1 $29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $29 + cell $eq $30 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32401,12 +32802,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $28 + connect \Y $29 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $30 + wire width 1 $31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $31 + cell $eq $32 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32414,12 +32815,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $30 + connect \Y $31 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $32 + wire width 1 $33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $33 + cell $eq $34 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32427,12 +32828,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $32 + connect \Y $33 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $34 + wire width 1 $35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $35 + cell $eq $36 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32440,12 +32841,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $34 + connect \Y $35 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $36 + wire width 1 $37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $37 + cell $eq $38 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32453,12 +32854,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $36 + connect \Y $37 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $38 + wire width 1 $39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $39 + cell $eq $40 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32466,12 +32867,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $38 + connect \Y $39 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $40 + wire width 1 $41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $41 + cell $eq $42 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32479,12 +32880,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $40 + connect \Y $41 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $42 + wire width 1 $43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $43 + cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32492,12 +32893,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $42 + connect \Y $43 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $44 + wire width 1 $45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $45 + cell $eq $46 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32505,12 +32906,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $44 + connect \Y $45 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $46 + wire width 1 $47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $47 + cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32518,12 +32919,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $46 + connect \Y $47 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $48 + wire width 1 $49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $49 + cell $eq $50 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32531,12 +32932,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $48 + connect \Y $49 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $50 + wire width 1 $51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $51 + cell $eq $52 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32544,12 +32945,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $50 + connect \Y $51 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $52 + wire width 1 $53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $53 + cell $eq $54 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32557,12 +32958,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $52 + connect \Y $53 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $54 + wire width 1 $55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $55 + cell $eq $56 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32570,12 +32971,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $54 + connect \Y $55 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $56 + wire width 1 $57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $57 + cell $eq $58 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32583,12 +32984,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $56 + connect \Y $57 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $58 + wire width 1 $59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $59 + cell $eq $60 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32596,12 +32997,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $58 + connect \Y $59 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $60 + wire width 1 $61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $61 + cell $eq $62 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32609,12 +33010,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $60 + connect \Y $61 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $62 + wire width 1 $63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $63 + cell $eq $64 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32622,12 +33023,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $62 + connect \Y $63 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $64 + wire width 1 $65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $65 + cell $eq $66 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32635,12 +33036,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $64 + connect \Y $65 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $66 + wire width 1 $67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $67 + cell $eq $68 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32648,12 +33049,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $66 + connect \Y $67 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $68 + wire width 1 $69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $69 + cell $eq $70 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32661,12 +33062,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $68 + connect \Y $69 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $70 + wire width 1 $71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $71 + cell $eq $72 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32674,12 +33075,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $70 + connect \Y $71 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $72 + wire width 1 $73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $73 + cell $eq $74 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32687,12 +33088,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $72 + connect \Y $73 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $74 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $75 + cell $eq $76 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32700,12 +33101,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $74 + connect \Y $75 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $76 + wire width 1 $77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $77 + cell $eq $78 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32713,12 +33114,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $76 + connect \Y $77 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $78 + wire width 1 $79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $79 + cell $eq $80 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32726,12 +33127,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $78 + connect \Y $79 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $80 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $81 + cell $eq $82 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32739,12 +33140,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $80 + connect \Y $81 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $82 + wire width 1 $83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $83 + cell $eq $84 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32752,12 +33153,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $82 + connect \Y $83 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $84 + wire width 1 $85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $85 + cell $eq $86 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32765,12 +33166,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $84 + connect \Y $85 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $86 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $87 + cell $eq $88 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32778,12 +33179,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $86 + connect \Y $87 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $88 + wire width 1 $89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $89 + cell $eq $90 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32791,12 +33192,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $88 + connect \Y $89 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $90 + wire width 1 $91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $91 + cell $eq $92 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32804,12 +33205,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $90 + connect \Y $91 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $92 + wire width 1 $93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $93 + cell $eq $94 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32817,12 +33218,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $92 + connect \Y $93 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $94 + wire width 1 $95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $95 + cell $eq $96 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32830,12 +33231,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $94 + connect \Y $95 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $96 + wire width 1 $97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $97 + cell $eq $98 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32843,12 +33244,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $96 + connect \Y $97 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $98 + wire width 1 $99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $99 + cell $eq $100 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32856,12 +33257,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $98 + connect \Y $99 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $100 + wire width 1 $101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $101 + cell $eq $102 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32869,12 +33270,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $100 + connect \Y $101 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $102 + wire width 1 $103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $103 + cell $eq $104 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32882,12 +33283,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $102 + connect \Y $103 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $104 + wire width 1 $105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $105 + cell $eq $106 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32895,12 +33296,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $104 + connect \Y $105 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $106 + wire width 1 $107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $107 + cell $eq $108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32908,12 +33309,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $106 + connect \Y $107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $108 + wire width 1 $109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $109 + cell $eq $110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32921,12 +33322,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $108 + connect \Y $109 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $110 + wire width 1 $111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $111 + cell $eq $112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32934,12 +33335,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $110 + connect \Y $111 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $112 + wire width 1 $113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $113 + cell $eq $114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32947,12 +33348,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $112 + connect \Y $113 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $114 + wire width 1 $115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $115 + cell $eq $116 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32960,12 +33361,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $114 + connect \Y $115 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $116 + wire width 1 $117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $117 + cell $eq $118 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32973,12 +33374,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $116 + connect \Y $117 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $118 + wire width 1 $119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $119 + cell $eq $120 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32986,12 +33387,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $118 + connect \Y $119 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $120 + wire width 1 $121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $121 + cell $eq $122 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -32999,12 +33400,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $120 + connect \Y $121 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $122 + wire width 1 $123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $123 + cell $eq $124 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33012,12 +33413,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $122 + connect \Y $123 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $124 + wire width 1 $125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $125 + cell $eq $126 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33025,12 +33426,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $124 + connect \Y $125 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $126 + wire width 1 $127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $127 + cell $eq $128 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33038,12 +33439,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $126 + connect \Y $127 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $128 + wire width 1 $129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $129 + cell $eq $130 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33051,12 +33452,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $128 + connect \Y $129 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $130 + wire width 1 $131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $131 + cell $eq $132 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33064,12 +33465,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $130 + connect \Y $131 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $132 + wire width 1 $133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $133 + cell $eq $134 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33077,12 +33478,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $132 + connect \Y $133 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $134 + wire width 1 $135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $135 + cell $eq $136 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33090,12 +33491,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $134 + connect \Y $135 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $136 + wire width 1 $137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $137 + cell $eq $138 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33103,12 +33504,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $136 + connect \Y $137 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $138 + wire width 1 $139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $139 + cell $eq $140 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33116,12 +33517,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $138 + connect \Y $139 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $140 + wire width 1 $141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $141 + cell $eq $142 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33129,12 +33530,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $140 + connect \Y $141 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $142 + wire width 1 $143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $143 + cell $eq $144 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33142,12 +33543,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $142 + connect \Y $143 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $144 + wire width 1 $145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $145 + cell $eq $146 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33155,12 +33556,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $144 + connect \Y $145 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $146 + wire width 1 $147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $147 + cell $eq $148 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33168,12 +33569,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $146 + connect \Y $147 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $148 + wire width 1 $149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $149 + cell $eq $150 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33181,12 +33582,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $148 + connect \Y $149 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $150 + wire width 1 $151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $151 + cell $eq $152 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33194,12 +33595,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $150 + connect \Y $151 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $152 + wire width 1 $153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $153 + cell $eq $154 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -33207,12 +33608,12 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $152 + connect \Y $153 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - wire width 1 $154 + wire width 1 $155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $155 + cell $eq $156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -33220,18 +33621,18 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $154 + connect \Y $155 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - wire width 64 $156 + wire width 64 $157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" wire width 1 \par0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" wire width 1 \par1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - wire width 1 $157 + wire width 1 $158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $158 + cell $xor $159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -33239,22 +33640,22 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $157 + connect \Y $158 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $159 + cell $pos $160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 - connect \A $157 - connect \Y $156 + connect \A $158 + connect \Y $157 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - wire width 64 $160 + wire width 64 $161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - wire width 8 $161 + wire width 8 $162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $162 + cell $sub $163 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -33262,35 +33663,35 @@ module \main$48 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $161 + connect \Y $162 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 8 $163 + wire width 8 $164 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $164 + cell $pos $165 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $163 + connect \Y $164 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - wire width 8 $165 + wire width 8 $166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $166 + cell $mux $167 parameter \WIDTH 8 - connect \A $163 - connect \B $161 + connect \A $164 + connect \B $162 connect \S \logical_op__is_32bit - connect \Y $165 + connect \Y $166 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $167 + cell $pos $168 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 - connect \A $165 - connect \Y $160 + connect \A $166 + connect \Y $161 end process $group_1 assign \o_ok 1'0 @@ -33301,19 +33702,19 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" attribute \nmigen.decoding "OP_AND/4" case 7'0000100 - assign \o $20 + assign \o $21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" attribute \nmigen.decoding "OP_OR/53" case 7'0110101 - assign \o $22 + assign \o $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" attribute \nmigen.decoding "OP_XOR/67" case 7'1000011 - assign \o $24 + assign \o $25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" attribute \nmigen.decoding "OP_CMPB/11" case 7'0001011 - assign \o { { $138 $140 $142 $144 $146 $148 $150 $152 } { $122 $124 $126 $128 $130 $132 $134 $136 } { $106 $108 $110 $112 $114 $116 $118 $120 } { $90 $92 $94 $96 $98 $100 $102 $104 } { $74 $76 $78 $80 $82 $84 $86 $88 } { $58 $60 $62 $64 $66 $68 $70 $72 } { $42 $44 $46 $48 $50 $52 $54 $56 } { $26 $28 $30 $32 $34 $36 $38 $40 } } + assign \o { { $139 $141 $143 $145 $147 $149 $151 $153 } { $123 $125 $127 $129 $131 $133 $135 $137 } { $107 $109 $111 $113 $115 $117 $119 $121 } { $91 $93 $95 $97 $99 $101 $103 $105 } { $75 $77 $79 $81 $83 $85 $87 $89 } { $59 $61 $63 $65 $67 $69 $71 $73 } { $43 $45 $47 $49 $51 $53 $55 $57 } { $27 $29 $31 $33 $35 $37 $39 $41 } } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" attribute \nmigen.decoding "OP_POPCNT/54" case 7'0110110 @@ -33322,10 +33723,10 @@ module \main$48 attribute \nmigen.decoding "OP_PRTY/55" case 7'0110111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - switch { $154 } + switch { $155 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" case 1'1 - assign \o $156 + assign \o $157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:90" case assign { \o_ok \o } [0] \par0 @@ -33334,7 +33735,7 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" attribute \nmigen.decoding "OP_CNTZ/14" case 7'0001110 - assign \o $160 + assign \o $161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" attribute \nmigen.decoding "OP_BPERM/9" case 7'0001001 @@ -33419,14 +33820,14 @@ module \main$48 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 $168 + wire width 64 $169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $169 + cell $pos $170 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $168 + connect \Y $169 end process $group_4 assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -33447,7 +33848,7 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" attribute \nmigen.decoding "OP_POPCNT/54" case 7'0110110 - assign \popcount_data_len $168 + assign \popcount_data_len $169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" attribute \nmigen.decoding "OP_PRTY/55" case 7'0110111 @@ -33464,14 +33865,14 @@ module \main$48 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - wire width 1 $170 + wire width 1 $171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $171 + cell $reduce_xor $172 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $170 + connect \Y $171 end process $group_5 assign \par0 1'0 @@ -33495,7 +33896,7 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" attribute \nmigen.decoding "OP_PRTY/55" case 7'0110111 - assign \par0 $170 + assign \par0 $171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" attribute \nmigen.decoding "OP_CNTZ/14" case 7'0001110 @@ -33509,14 +33910,14 @@ module \main$48 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - wire width 1 $172 + wire width 1 $173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $173 + cell $reduce_xor $174 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $172 + connect \Y $173 end process $group_6 assign \par1 1'0 @@ -33540,7 +33941,7 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" attribute \nmigen.decoding "OP_PRTY/55" case 7'0110111 - assign \par1 $172 + assign \par1 $173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" attribute \nmigen.decoding "OP_CNTZ/14" case 7'0001110 @@ -33630,34 +34031,34 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - wire width 64 $174 + wire width 64 $175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - wire width 32 $175 + wire width 32 $176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $176 + cell $mux $177 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $175 + connect \Y $176 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $177 + cell $pos $178 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 - connect \A $175 - connect \Y $174 + connect \A $176 + connect \Y $175 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - wire width 64 $178 + wire width 64 $179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $179 + cell $mux $180 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $178 + connect \Y $179 end process $group_9 assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -33688,10 +34089,10 @@ module \main$48 switch { \logical_op__is_32bit } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" case 1'1 - assign \cntz_i $174 + assign \cntz_i $175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" case - assign \cntz_i $178 + assign \cntz_i $179 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" attribute \nmigen.decoding "OP_BPERM/9" @@ -33808,19 +34209,24 @@ module \main$48 sync init end process $group_13 + assign \xer_so$20 1'0 + assign \xer_so$20 \xer_so + sync init + end + process $group_14 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_14 + process $group_15 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -33831,16 +34237,16 @@ module \main$48 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" module \logical_pipe1 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 2 \n_valid_o @@ -33944,29 +34350,29 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__imm + wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$next + wire width 64 \logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \logical_op__imm_data__imm_ok + wire width 1 output 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$next + wire width 1 \logical_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \logical_op__rc__rc_ok + wire width 1 output 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$next + wire width 1 \logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \logical_op__oe__oe_ok + wire width 1 output 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$next + wire width 1 \logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34028,13 +34434,13 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 27 \xer_ca + wire width 1 output 27 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$next + wire width 1 \xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \xer_ca_ok + wire width 1 output 28 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$next + wire width 1 \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 29 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -34131,17 +34537,17 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 33 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 34 \logical_op__imm_data__imm$4 + wire width 64 input 34 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 35 \logical_op__imm_data__imm_ok$5 + wire width 1 input 35 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 36 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 37 \logical_op__rc__rc_ok$7 + wire width 1 input 37 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 38 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 39 \logical_op__oe__oe_ok$9 + wire width 1 input 39 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 40 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34170,6 +34576,8 @@ module \logical_pipe1 wire width 64 input 50 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 52 \xer_so$20 cell \p$45 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -34270,17 +34678,17 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm + wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok + wire width 1 \input_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok + wire width 1 \input_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok + wire width 1 \input_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34309,8 +34717,10 @@ module \logical_pipe1 wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$20 + wire width 2 \input_muxid$21 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -34385,7 +34795,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type$21 + wire width 7 \input_logical_op__insn_type$22 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -34399,57 +34809,59 @@ module \logical_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_logical_op__fn_unit$22 + wire width 11 \input_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm$23 + wire width 64 \input_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok$24 + wire width 1 \input_logical_op__imm_data__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc$25 + wire width 1 \input_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok$26 + wire width 1 \input_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe$27 + wire width 1 \input_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok$28 + wire width 1 \input_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_in$29 + wire width 1 \input_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__zero_a$30 + wire width 1 \input_logical_op__zero_a$31 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$31 + wire width 2 \input_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_out$32 + wire width 1 \input_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__write_cr0$33 + wire width 1 \input_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__output_carry$34 + wire width 1 \input_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_32bit$35 + wire width 1 \input_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_signed$36 + wire width 1 \input_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$37 + wire width 4 \input_logical_op__data_len$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$38 + wire width 32 \input_logical_op__insn$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$39 + wire width 64 \input_rb$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$40 + wire width 1 \input_xer_so$42 cell \input$47 \input connect \muxid \input_muxid connect \logical_op__insn_type \input_logical_op__insn_type connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok + connect \logical_op__rc__ok \input_logical_op__rc__ok connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok + connect \logical_op__oe__ok \input_logical_op__oe__ok connect \logical_op__invert_in \input_logical_op__invert_in connect \logical_op__zero_a \input_logical_op__zero_a connect \logical_op__input_carry \input_logical_op__input_carry @@ -34462,27 +34874,29 @@ module \logical_pipe1 connect \logical_op__insn \input_logical_op__insn connect \ra \input_ra connect \rb \input_rb - connect \muxid$1 \input_muxid$20 - connect \logical_op__insn_type$2 \input_logical_op__insn_type$21 - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$22 - connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$23 - connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$24 - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$25 - connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$26 - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$27 - connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$28 - connect \logical_op__invert_in$10 \input_logical_op__invert_in$29 - connect \logical_op__zero_a$11 \input_logical_op__zero_a$30 - connect \logical_op__input_carry$12 \input_logical_op__input_carry$31 - connect \logical_op__invert_out$13 \input_logical_op__invert_out$32 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$33 - connect \logical_op__output_carry$15 \input_logical_op__output_carry$34 - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$35 - connect \logical_op__is_signed$17 \input_logical_op__is_signed$36 - connect \logical_op__data_len$18 \input_logical_op__data_len$37 - connect \logical_op__insn$19 \input_logical_op__insn$38 - connect \ra$20 \input_ra$39 - connect \rb$21 \input_rb$40 + connect \xer_so \input_xer_so + connect \muxid$1 \input_muxid$21 + connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 + connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__data_len$18 \input_logical_op__data_len$38 + connect \logical_op__insn$19 \input_logical_op__insn$39 + connect \ra$20 \input_ra$40 + connect \rb$21 \input_rb$41 + connect \xer_so$22 \input_xer_so$42 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid @@ -34576,17 +34990,17 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \main_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__imm + wire width 64 \main_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__imm_data__imm_ok + wire width 1 \main_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc_ok + wire width 1 \main_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe_ok + wire width 1 \main_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34615,8 +35029,10 @@ module \logical_pipe1 wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \main_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$41 + wire width 2 \main_muxid$43 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -34691,7 +35107,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type$42 + wire width 7 \main_logical_op__insn_type$44 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -34705,57 +35121,59 @@ module \logical_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_logical_op__fn_unit$43 + wire width 11 \main_logical_op__fn_unit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__imm$44 + wire width 64 \main_logical_op__imm_data__data$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__imm_data__imm_ok$45 + wire width 1 \main_logical_op__imm_data__ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc$46 + wire width 1 \main_logical_op__rc__rc$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc_ok$47 + wire width 1 \main_logical_op__rc__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe$48 + wire width 1 \main_logical_op__oe__oe$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe_ok$49 + wire width 1 \main_logical_op__oe__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__invert_in$50 + wire width 1 \main_logical_op__invert_in$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__zero_a$51 + wire width 1 \main_logical_op__zero_a$53 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry$52 + wire width 2 \main_logical_op__input_carry$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__invert_out$53 + wire width 1 \main_logical_op__invert_out$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__write_cr0$54 + wire width 1 \main_logical_op__write_cr0$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__output_carry$55 + wire width 1 \main_logical_op__output_carry$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__is_32bit$56 + wire width 1 \main_logical_op__is_32bit$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__is_signed$57 + wire width 1 \main_logical_op__is_signed$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len$58 + wire width 4 \main_logical_op__data_len$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn$59 + wire width 32 \main_logical_op__insn$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_xer_so$62 cell \main$48 \main connect \muxid \main_muxid connect \logical_op__insn_type \main_logical_op__insn_type connect \logical_op__fn_unit \main_logical_op__fn_unit - connect \logical_op__imm_data__imm \main_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \main_logical_op__imm_data__data + connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok connect \logical_op__rc__rc \main_logical_op__rc__rc - connect \logical_op__rc__rc_ok \main_logical_op__rc__rc_ok + connect \logical_op__rc__ok \main_logical_op__rc__ok connect \logical_op__oe__oe \main_logical_op__oe__oe - connect \logical_op__oe__oe_ok \main_logical_op__oe__oe_ok + connect \logical_op__oe__ok \main_logical_op__oe__ok connect \logical_op__invert_in \main_logical_op__invert_in connect \logical_op__zero_a \main_logical_op__zero_a connect \logical_op__input_carry \main_logical_op__input_carry @@ -34768,27 +35186,29 @@ module \logical_pipe1 connect \logical_op__insn \main_logical_op__insn connect \ra \main_ra connect \rb \main_rb - connect \muxid$1 \main_muxid$41 - connect \logical_op__insn_type$2 \main_logical_op__insn_type$42 - connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$43 - connect \logical_op__imm_data__imm$4 \main_logical_op__imm_data__imm$44 - connect \logical_op__imm_data__imm_ok$5 \main_logical_op__imm_data__imm_ok$45 - connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$46 - connect \logical_op__rc__rc_ok$7 \main_logical_op__rc__rc_ok$47 - connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$48 - connect \logical_op__oe__oe_ok$9 \main_logical_op__oe__oe_ok$49 - connect \logical_op__invert_in$10 \main_logical_op__invert_in$50 - connect \logical_op__zero_a$11 \main_logical_op__zero_a$51 - connect \logical_op__input_carry$12 \main_logical_op__input_carry$52 - connect \logical_op__invert_out$13 \main_logical_op__invert_out$53 - connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$54 - connect \logical_op__output_carry$15 \main_logical_op__output_carry$55 - connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$56 - connect \logical_op__is_signed$17 \main_logical_op__is_signed$57 - connect \logical_op__data_len$18 \main_logical_op__data_len$58 - connect \logical_op__insn$19 \main_logical_op__insn$59 + connect \xer_so \main_xer_so + connect \muxid$1 \main_muxid$43 + connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 + connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 + connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 + connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__data_len$18 \main_logical_op__data_len$60 + connect \logical_op__insn$19 \main_logical_op__insn$61 connect \o \main_o connect \o_ok \main_o_ok + connect \xer_so$20 \main_xer_so$62 end process $group_0 assign \input_muxid 2'00 @@ -34798,12 +35218,12 @@ module \logical_pipe1 process $group_1 assign \input_logical_op__insn_type 7'0000000 assign \input_logical_op__fn_unit 11'00000000000 - assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_logical_op__imm_data__imm_ok 1'0 + assign \input_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_logical_op__imm_data__ok 1'0 assign \input_logical_op__rc__rc 1'0 - assign \input_logical_op__rc__rc_ok 1'0 + assign \input_logical_op__rc__ok 1'0 assign \input_logical_op__oe__oe 1'0 - assign \input_logical_op__oe__oe_ok 1'0 + assign \input_logical_op__oe__ok 1'0 assign \input_logical_op__invert_in 1'0 assign \input_logical_op__zero_a 1'0 assign \input_logical_op__input_carry 2'00 @@ -34814,7 +35234,7 @@ module \logical_pipe1 assign \input_logical_op__is_signed 1'0 assign \input_logical_op__data_len 4'0000 assign \input_logical_op__insn 32'00000000000000000000000000000000 - assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } + assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__ok \input_logical_op__oe__oe } { \input_logical_op__rc__ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__ok \input_logical_op__imm_data__data } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } sync init end process $group_19 @@ -34828,19 +35248,24 @@ module \logical_pipe1 sync init end process $group_21 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$20 + assign \input_xer_so 1'0 + assign \input_xer_so \xer_so$20 sync init end process $group_22 + assign \main_muxid 2'00 + assign \main_muxid \input_muxid$21 + sync init + end + process $group_23 assign \main_logical_op__insn_type 7'0000000 assign \main_logical_op__fn_unit 11'00000000000 - assign \main_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_logical_op__imm_data__imm_ok 1'0 + assign \main_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_logical_op__imm_data__ok 1'0 assign \main_logical_op__rc__rc 1'0 - assign \main_logical_op__rc__rc_ok 1'0 + assign \main_logical_op__rc__ok 1'0 assign \main_logical_op__oe__oe 1'0 - assign \main_logical_op__oe__oe_ok 1'0 + assign \main_logical_op__oe__ok 1'0 assign \main_logical_op__invert_in 1'0 assign \main_logical_op__zero_a 1'0 assign \main_logical_op__input_carry 2'00 @@ -34851,29 +35276,34 @@ module \logical_pipe1 assign \main_logical_op__is_signed 1'0 assign \main_logical_op__data_len 4'0000 assign \main_logical_op__insn 32'00000000000000000000000000000000 - assign { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in { \main_logical_op__oe__oe_ok \main_logical_op__oe__oe } { \main_logical_op__rc__rc_ok \main_logical_op__rc__rc } { \main_logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm } \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$38 \input_logical_op__data_len$37 \input_logical_op__is_signed$36 \input_logical_op__is_32bit$35 \input_logical_op__output_carry$34 \input_logical_op__write_cr0$33 \input_logical_op__invert_out$32 \input_logical_op__input_carry$31 \input_logical_op__zero_a$30 \input_logical_op__invert_in$29 { \input_logical_op__oe__oe_ok$28 \input_logical_op__oe__oe$27 } { \input_logical_op__rc__rc_ok$26 \input_logical_op__rc__rc$25 } { \input_logical_op__imm_data__imm_ok$24 \input_logical_op__imm_data__imm$23 } \input_logical_op__fn_unit$22 \input_logical_op__insn_type$21 } + assign { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in { \main_logical_op__oe__ok \main_logical_op__oe__oe } { \main_logical_op__rc__ok \main_logical_op__rc__rc } { \main_logical_op__imm_data__ok \main_logical_op__imm_data__data } \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 { \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 } { \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 } { \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 } \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } sync init end - process $group_40 + process $group_41 assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$39 + assign \main_ra \input_ra$40 sync init end - process $group_41 + process $group_42 assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$40 + assign \main_rb \input_rb$41 + sync init + end + process $group_43 + assign \main_xer_so 1'0 + assign \main_xer_so \input_xer_so$42 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$60 - process $group_42 - assign \p_valid_i$60 1'0 - assign \p_valid_i$60 \p_valid_i + wire width 1 \p_valid_i$63 + process $group_44 + assign \p_valid_i$63 1'0 + assign \p_valid_i$63 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_43 + process $group_45 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -34881,28 +35311,28 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $61 + wire width 1 $64 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $62 + cell $and $65 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$60 + connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $61 + connect \Y $64 end - process $group_44 + process $group_46 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $61 + assign \p_valid_i_p_ready_o $64 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$63 - process $group_45 - assign \muxid$63 2'00 - assign \muxid$63 \main_muxid$41 + wire width 2 \muxid$66 + process $group_47 + assign \muxid$66 2'00 + assign \muxid$66 \main_muxid$43 sync init end attribute \enum_base_type "MicrOp" @@ -34979,7 +35409,7 @@ module \logical_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$64 + wire width 7 \logical_op__insn_type$67 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -34993,108 +35423,106 @@ module \logical_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$65 + wire width 11 \logical_op__fn_unit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$66 + wire width 64 \logical_op__imm_data__data$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$67 + wire width 1 \logical_op__imm_data__ok$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$68 + wire width 1 \logical_op__rc__rc$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$69 + wire width 1 \logical_op__rc__ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$70 + wire width 1 \logical_op__oe__oe$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$71 + wire width 1 \logical_op__oe__ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$72 + wire width 1 \logical_op__invert_in$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$73 + wire width 1 \logical_op__zero_a$76 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$74 + wire width 2 \logical_op__input_carry$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$75 + wire width 1 \logical_op__invert_out$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$76 + wire width 1 \logical_op__write_cr0$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$77 + wire width 1 \logical_op__output_carry$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$78 + wire width 1 \logical_op__is_32bit$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$79 + wire width 1 \logical_op__is_signed$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$80 + wire width 4 \logical_op__data_len$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$81 - process $group_46 - assign \logical_op__insn_type$64 7'0000000 - assign \logical_op__fn_unit$65 11'00000000000 - assign \logical_op__imm_data__imm$66 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$67 1'0 - assign \logical_op__rc__rc$68 1'0 - assign \logical_op__rc__rc_ok$69 1'0 - assign \logical_op__oe__oe$70 1'0 - assign \logical_op__oe__oe_ok$71 1'0 - assign \logical_op__invert_in$72 1'0 - assign \logical_op__zero_a$73 1'0 - assign \logical_op__input_carry$74 2'00 - assign \logical_op__invert_out$75 1'0 - assign \logical_op__write_cr0$76 1'0 - assign \logical_op__output_carry$77 1'0 - assign \logical_op__is_32bit$78 1'0 - assign \logical_op__is_signed$79 1'0 - assign \logical_op__data_len$80 4'0000 - assign \logical_op__insn$81 32'00000000000000000000000000000000 - assign { \logical_op__insn$81 \logical_op__data_len$80 \logical_op__is_signed$79 \logical_op__is_32bit$78 \logical_op__output_carry$77 \logical_op__write_cr0$76 \logical_op__invert_out$75 \logical_op__input_carry$74 \logical_op__zero_a$73 \logical_op__invert_in$72 { \logical_op__oe__oe_ok$71 \logical_op__oe__oe$70 } { \logical_op__rc__rc_ok$69 \logical_op__rc__rc$68 } { \logical_op__imm_data__imm_ok$67 \logical_op__imm_data__imm$66 } \logical_op__fn_unit$65 \logical_op__insn_type$64 } { \main_logical_op__insn$59 \main_logical_op__data_len$58 \main_logical_op__is_signed$57 \main_logical_op__is_32bit$56 \main_logical_op__output_carry$55 \main_logical_op__write_cr0$54 \main_logical_op__invert_out$53 \main_logical_op__input_carry$52 \main_logical_op__zero_a$51 \main_logical_op__invert_in$50 { \main_logical_op__oe__oe_ok$49 \main_logical_op__oe__oe$48 } { \main_logical_op__rc__rc_ok$47 \main_logical_op__rc__rc$46 } { \main_logical_op__imm_data__imm_ok$45 \main_logical_op__imm_data__imm$44 } \main_logical_op__fn_unit$43 \main_logical_op__insn_type$42 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$83 - process $group_64 - assign \o$82 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$83 1'0 - assign { \o_ok$83 \o$82 } { \main_o_ok \main_o } + wire width 32 \logical_op__insn$84 + process $group_48 + assign \logical_op__insn_type$67 7'0000000 + assign \logical_op__fn_unit$68 11'00000000000 + assign \logical_op__imm_data__data$69 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$70 1'0 + assign \logical_op__rc__rc$71 1'0 + assign \logical_op__rc__ok$72 1'0 + assign \logical_op__oe__oe$73 1'0 + assign \logical_op__oe__ok$74 1'0 + assign \logical_op__invert_in$75 1'0 + assign \logical_op__zero_a$76 1'0 + assign \logical_op__input_carry$77 2'00 + assign \logical_op__invert_out$78 1'0 + assign \logical_op__write_cr0$79 1'0 + assign \logical_op__output_carry$80 1'0 + assign \logical_op__is_32bit$81 1'0 + assign \logical_op__is_signed$82 1'0 + assign \logical_op__data_len$83 4'0000 + assign \logical_op__insn$84 32'00000000000000000000000000000000 + assign { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 { \logical_op__oe__ok$74 \logical_op__oe__oe$73 } { \logical_op__rc__ok$72 \logical_op__rc__rc$71 } { \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 } \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 { \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 } { \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 } { \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 } \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$86 + process $group_66 + assign \o$85 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$86 1'0 + assign { \o_ok$86 \o$85 } { \main_o_ok \main_o } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$84 + wire width 4 \cr_a$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$85 + wire width 1 \cr_a_ok$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$86 + wire width 4 \cr_a$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$87 - process $group_66 - assign \cr_a$84 4'0000 - assign \cr_a_ok$85 1'0 - assign { \cr_a_ok$85 \cr_a$84 } { \cr_a_ok$87 \cr_a$86 } + wire width 1 \cr_a_ok$90 + process $group_68 + assign \cr_a$87 4'0000 + assign \cr_a_ok$88 1'0 + assign { \cr_a_ok$88 \cr_a$87 } { \cr_a_ok$90 \cr_a$89 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$89 + wire width 1 \xer_so$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$90 + wire width 1 \xer_so_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$91 - process $group_68 - assign \xer_ca$88 2'00 - assign \xer_ca_ok$89 1'0 - assign { \xer_ca_ok$89 \xer_ca$88 } { \xer_ca_ok$91 \xer_ca$90 } + wire width 1 \xer_so_ok$93 + process $group_70 + assign \xer_so$91 1'0 + assign \xer_so_ok$92 1'0 + assign { \xer_so_ok$92 \xer_so$91 } { \xer_so_ok$93 \main_xer_so$62 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_70 + process $group_72 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -35115,31 +35543,31 @@ module \logical_pipe1 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_71 + process $group_73 assign \muxid$next \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$next \muxid$63 + assign \muxid$next \muxid$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$next \muxid$63 + assign \muxid$next \muxid$66 end sync init update \muxid 2'00 sync posedge \coresync_clk update \muxid \muxid$next end - process $group_72 + process $group_74 assign \logical_op__insn_type$next \logical_op__insn_type assign \logical_op__fn_unit$next \logical_op__fn_unit - assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm - assign \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm_ok + assign \logical_op__imm_data__data$next \logical_op__imm_data__data + assign \logical_op__imm_data__ok$next \logical_op__imm_data__ok assign \logical_op__rc__rc$next \logical_op__rc__rc - assign \logical_op__rc__rc_ok$next \logical_op__rc__rc_ok + assign \logical_op__rc__ok$next \logical_op__rc__ok assign \logical_op__oe__oe$next \logical_op__oe__oe - assign \logical_op__oe__oe_ok$next \logical_op__oe__oe_ok + assign \logical_op__oe__ok$next \logical_op__oe__ok assign \logical_op__invert_in$next \logical_op__invert_in assign \logical_op__zero_a$next \logical_op__zero_a assign \logical_op__input_carry$next \logical_op__input_carry @@ -35154,30 +35582,30 @@ module \logical_pipe1 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$81 \logical_op__data_len$80 \logical_op__is_signed$79 \logical_op__is_32bit$78 \logical_op__output_carry$77 \logical_op__write_cr0$76 \logical_op__invert_out$75 \logical_op__input_carry$74 \logical_op__zero_a$73 \logical_op__invert_in$72 { \logical_op__oe__oe_ok$71 \logical_op__oe__oe$70 } { \logical_op__rc__rc_ok$69 \logical_op__rc__rc$68 } { \logical_op__imm_data__imm_ok$67 \logical_op__imm_data__imm$66 } \logical_op__fn_unit$65 \logical_op__insn_type$64 } + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 { \logical_op__oe__ok$74 \logical_op__oe__oe$73 } { \logical_op__rc__ok$72 \logical_op__rc__rc$71 } { \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 } \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$81 \logical_op__data_len$80 \logical_op__is_signed$79 \logical_op__is_32bit$78 \logical_op__output_carry$77 \logical_op__write_cr0$76 \logical_op__invert_out$75 \logical_op__input_carry$74 \logical_op__zero_a$73 \logical_op__invert_in$72 { \logical_op__oe__oe_ok$71 \logical_op__oe__oe$70 } { \logical_op__rc__rc_ok$69 \logical_op__rc__rc$68 } { \logical_op__imm_data__imm_ok$67 \logical_op__imm_data__imm$66 } \logical_op__fn_unit$65 \logical_op__insn_type$64 } + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 { \logical_op__oe__ok$74 \logical_op__oe__oe$73 } { \logical_op__rc__ok$72 \logical_op__rc__rc$71 } { \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 } \logical_op__fn_unit$68 \logical_op__insn_type$67 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$next 1'0 + assign \logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$next 1'0 assign \logical_op__rc__rc$next 1'0 - assign \logical_op__rc__rc_ok$next 1'0 + assign \logical_op__rc__ok$next 1'0 assign \logical_op__oe__oe$next 1'0 - assign \logical_op__oe__oe_ok$next 1'0 + assign \logical_op__oe__ok$next 1'0 end sync init update \logical_op__insn_type 7'0000000 update \logical_op__fn_unit 11'00000000000 - update \logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok 1'0 + update \logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__ok 1'0 update \logical_op__rc__rc 1'0 - update \logical_op__rc__rc_ok 1'0 + update \logical_op__rc__ok 1'0 update \logical_op__oe__oe 1'0 - update \logical_op__oe__oe_ok 1'0 + update \logical_op__oe__ok 1'0 update \logical_op__invert_in 1'0 update \logical_op__zero_a 1'0 update \logical_op__input_carry 2'00 @@ -35191,12 +35619,12 @@ module \logical_pipe1 sync posedge \coresync_clk update \logical_op__insn_type \logical_op__insn_type$next update \logical_op__fn_unit \logical_op__fn_unit$next - update \logical_op__imm_data__imm \logical_op__imm_data__imm$next - update \logical_op__imm_data__imm_ok \logical_op__imm_data__imm_ok$next + update \logical_op__imm_data__data \logical_op__imm_data__data$next + update \logical_op__imm_data__ok \logical_op__imm_data__ok$next update \logical_op__rc__rc \logical_op__rc__rc$next - update \logical_op__rc__rc_ok \logical_op__rc__rc_ok$next + update \logical_op__rc__ok \logical_op__rc__ok$next update \logical_op__oe__oe \logical_op__oe__oe$next - update \logical_op__oe__oe_ok \logical_op__oe__oe_ok$next + update \logical_op__oe__ok \logical_op__oe__ok$next update \logical_op__invert_in \logical_op__invert_in$next update \logical_op__zero_a \logical_op__zero_a$next update \logical_op__input_carry \logical_op__input_carry$next @@ -35208,17 +35636,17 @@ module \logical_pipe1 update \logical_op__data_len \logical_op__data_len$next update \logical_op__insn \logical_op__insn$next end - process $group_90 + process $group_92 assign \o$next \o assign \o_ok$next \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$83 \o$82 } + assign { \o_ok$next \o$next } { \o_ok$86 \o$85 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$next \o$next } { \o_ok$83 \o$82 } + assign { \o_ok$next \o$next } { \o_ok$86 \o$85 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -35232,17 +35660,17 @@ module \logical_pipe1 update \o \o$next update \o_ok \o_ok$next end - process $group_92 + process $group_94 assign \cr_a$next \cr_a assign \cr_a_ok$next \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$85 \cr_a$84 } + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$88 \cr_a$87 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$85 \cr_a$84 } + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$88 \cr_a$87 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -35256,44 +35684,43 @@ module \logical_pipe1 update \cr_a \cr_a$next update \cr_a_ok \cr_a_ok$next end - process $group_94 - assign \xer_ca$next \xer_ca - assign \xer_ca_ok$next \xer_ca_ok + process $group_96 + assign \xer_so$next \xer_so + assign \xer_so_ok$next \xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$89 \xer_ca$88 } + assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$92 \xer_so$91 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$89 \xer_ca$88 } + assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$92 \xer_so$91 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \xer_ca_ok$next 1'0 + assign \xer_so_ok$next 1'0 end sync init - update \xer_ca 2'00 - update \xer_ca_ok 1'0 + update \xer_so 1'0 + update \xer_so_ok 1'0 sync posedge \coresync_clk - update \xer_ca \xer_ca$next - update \xer_ca_ok \xer_ca_ok$next + update \xer_so \xer_so$next + update \xer_so_ok \xer_so_ok$next end - process $group_96 + process $group_98 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_97 + process $group_99 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end - connect \cr_a$86 4'0000 - connect \cr_a_ok$87 1'0 - connect \xer_ca$90 2'00 - connect \xer_ca_ok$91 1'0 + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.p" @@ -35446,17 +35873,17 @@ module \output$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35488,7 +35915,7 @@ module \output$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 4 input 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ca + wire width 1 input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 23 \muxid$1 attribute \enum_base_type "MicrOp" @@ -35581,17 +36008,17 @@ module \output$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 25 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \logical_op__imm_data__imm$4 + wire width 64 output 26 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__imm_data__imm_ok$5 + wire width 1 output 27 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 28 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__rc__rc_ok$7 + wire width 1 output 29 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 30 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__oe__oe_ok$9 + wire width 1 output 31 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 32 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35624,78 +36051,64 @@ module \output$51 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 46 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $26 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $26 + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $27 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 - connect \A $26 - connect \Y $25 + connect \A $25 + connect \Y $24 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $29 + wire width 65 $28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $30 + cell $pos $29 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $29 + connect \Y $28 end process $group_0 - assign \o$24 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + assign \o$23 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" switch { \logical_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" case 1'1 - assign \o$24 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + assign \o$23 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" case - assign \o$24 $29 + assign \o$23 $28 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target process $group_1 assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$24 [63:0] - sync init - end - process $group_2 - assign \xer_ca$23 2'00 - assign \xer_ca$23 \xer_ca - sync init - end - process $group_3 - assign \xer_ca_ok 1'0 - assign \xer_ca_ok \logical_op__output_carry + assign \target \o$23 [63:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $31 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -35703,19 +36116,19 @@ module \output$51 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $31 + connect \Y $30 end - process $group_4 + process $group_2 assign \is_cmp 1'0 - assign \is_cmp $31 + assign \is_cmp $30 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $33 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -35723,172 +36136,146 @@ module \output$51 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $33 + connect \Y $32 end - process $group_5 + process $group_3 assign \is_cmpeqb 1'0 - assign \is_cmpeqb $33 + assign \is_cmpeqb $32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire width 1 \msb_test - process $group_6 + process $group_4 assign \msb_test 1'0 assign \msb_test \target [63] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_bool $35 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $35 + connect \Y $34 end - process $group_7 + process $group_5 assign \is_nzero 1'0 - assign \is_nzero $35 + assign \is_nzero $34 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire width 1 \is_negative + process $group_6 + assign \is_negative 1'0 + assign \is_negative \msb_test sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $37 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $37 + connect \Y $36 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $39 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \B $37 - connect \Y $39 + connect \B $36 + connect \Y $38 end - process $group_8 + process $group_7 assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $39 - end + assign \is_positive $38 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $41 - connect \Y $43 - end - process $group_9 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $40 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $45 + connect \Y $42 end - process $group_10 + process $group_8 assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch { $40 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" case 1'1 assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" case - assign \cr0 { \is_negative \is_positive $45 1'0 } + assign \cr0 { \is_negative \is_positive $42 \xer_so } end sync init end - process $group_11 + process $group_9 assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$24 [63:0] + assign \o$20 \o$23 [63:0] sync init end - process $group_12 + process $group_10 assign \o_ok$21 1'0 assign \o_ok$21 \o_ok sync init end - process $group_13 + process $group_11 assign \cr_a$22 4'0000 assign \cr_a$22 \cr0 sync init end - process $group_14 + process $group_12 assign \cr_a_ok 1'0 assign \cr_a_ok \logical_op__write_cr0 sync init end - process $group_15 + process $group_13 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_16 + process $group_14 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -35899,16 +36286,16 @@ module \output$51 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2" module \logical_pipe2 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -36006,17 +36393,17 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36050,9 +36437,9 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 input 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 27 \xer_ca + wire width 1 input 27 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 28 \xer_ca_ok + wire width 1 input 28 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 29 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -36155,29 +36542,29 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 34 \logical_op__imm_data__imm$4 + wire width 64 output 34 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next + wire width 64 \logical_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__imm_data__imm_ok$5 + wire width 1 output 35 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next + wire width 1 \logical_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 36 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__rc__rc_ok$7 + wire width 1 output 37 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next + wire width 1 \logical_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 38 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__oe__oe_ok$9 + wire width 1 output 39 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next + wire width 1 \logical_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 40 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36238,14 +36625,6 @@ module \logical_pipe2 wire width 1 output 53 \cr_a_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 54 \xer_ca$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 55 \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$25$next cell \p$49 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -36346,17 +36725,17 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm + wire width 64 \output_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok + wire width 1 \output_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok + wire width 1 \output_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok + wire width 1 \output_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -36388,9 +36767,9 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca + wire width 1 \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$26 + wire width 2 \output_muxid$24 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -36465,7 +36844,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$27 + wire width 7 \output_logical_op__insn_type$25 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -36479,65 +36858,61 @@ module \logical_pipe2 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_logical_op__fn_unit$28 + wire width 11 \output_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm$29 + wire width 64 \output_logical_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok$30 + wire width 1 \output_logical_op__imm_data__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc$31 + wire width 1 \output_logical_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok$32 + wire width 1 \output_logical_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe$33 + wire width 1 \output_logical_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok$34 + wire width 1 \output_logical_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_in$35 + wire width 1 \output_logical_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__zero_a$36 + wire width 1 \output_logical_op__zero_a$34 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$37 + wire width 2 \output_logical_op__input_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_out$38 + wire width 1 \output_logical_op__invert_out$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__write_cr0$39 + wire width 1 \output_logical_op__write_cr0$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__output_carry$40 + wire width 1 \output_logical_op__output_carry$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_32bit$41 + wire width 1 \output_logical_op__is_32bit$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_signed$42 + wire width 1 \output_logical_op__is_signed$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$43 + wire width 4 \output_logical_op__data_len$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$44 + wire width 32 \output_logical_op__insn$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$45 + wire width 64 \output_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$46 + wire width 1 \output_o_ok$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$47 + wire width 4 \output_cr_a$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ca_ok cell \output$51 \output connect \muxid \output_muxid connect \logical_op__insn_type \output_logical_op__insn_type connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok + connect \logical_op__rc__ok \output_logical_op__rc__ok connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok + connect \logical_op__oe__ok \output_logical_op__oe__ok connect \logical_op__invert_in \output_logical_op__invert_in connect \logical_op__zero_a \output_logical_op__zero_a connect \logical_op__input_carry \output_logical_op__input_carry @@ -36551,32 +36926,30 @@ module \logical_pipe2 connect \o \output_o connect \o_ok \output_o_ok connect \cr_a \output_cr_a - connect \xer_ca \output_xer_ca - connect \muxid$1 \output_muxid$26 - connect \logical_op__insn_type$2 \output_logical_op__insn_type$27 - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$28 - connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$29 - connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$30 - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$31 - connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$32 - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$33 - connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$34 - connect \logical_op__invert_in$10 \output_logical_op__invert_in$35 - connect \logical_op__zero_a$11 \output_logical_op__zero_a$36 - connect \logical_op__input_carry$12 \output_logical_op__input_carry$37 - connect \logical_op__invert_out$13 \output_logical_op__invert_out$38 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$39 - connect \logical_op__output_carry$15 \output_logical_op__output_carry$40 - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$41 - connect \logical_op__is_signed$17 \output_logical_op__is_signed$42 - connect \logical_op__data_len$18 \output_logical_op__data_len$43 - connect \logical_op__insn$19 \output_logical_op__insn$44 - connect \o$20 \output_o$45 - connect \o_ok$21 \output_o_ok$46 - connect \cr_a$22 \output_cr_a$47 + connect \xer_so \output_xer_so + connect \muxid$1 \output_muxid$24 + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \o$20 \output_o$43 + connect \o_ok$21 \output_o_ok$44 + connect \cr_a$22 \output_cr_a$45 connect \cr_a_ok \output_cr_a_ok - connect \xer_ca$23 \output_xer_ca$48 - connect \xer_ca_ok \output_xer_ca_ok end process $group_0 assign \output_muxid 2'00 @@ -36586,12 +36959,12 @@ module \logical_pipe2 process $group_1 assign \output_logical_op__insn_type 7'0000000 assign \output_logical_op__fn_unit 11'00000000000 - assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_logical_op__imm_data__imm_ok 1'0 + assign \output_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_logical_op__imm_data__ok 1'0 assign \output_logical_op__rc__rc 1'0 - assign \output_logical_op__rc__rc_ok 1'0 + assign \output_logical_op__rc__ok 1'0 assign \output_logical_op__oe__oe 1'0 - assign \output_logical_op__oe__oe_ok 1'0 + assign \output_logical_op__oe__ok 1'0 assign \output_logical_op__invert_in 1'0 assign \output_logical_op__zero_a 1'0 assign \output_logical_op__input_carry 2'00 @@ -36602,7 +36975,7 @@ module \logical_pipe2 assign \output_logical_op__is_signed 1'0 assign \output_logical_op__data_len 4'0000 assign \output_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__ok \output_logical_op__oe__oe } { \output_logical_op__rc__ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__ok \output_logical_op__imm_data__data } \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end process $group_19 @@ -36612,26 +36985,26 @@ module \logical_pipe2 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$49 + wire width 1 \cr_a_ok$46 process $group_21 assign \output_cr_a 4'0000 - assign \cr_a_ok$49 1'0 - assign { \cr_a_ok$49 \output_cr_a } { \cr_a_ok \cr_a } + assign \cr_a_ok$46 1'0 + assign { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$50 + wire width 1 \xer_so_ok$47 process $group_23 - assign \output_xer_ca 2'00 - assign \xer_ca_ok$50 1'0 - assign { \xer_ca_ok$50 \output_xer_ca } { \xer_ca_ok \xer_ca } + assign \output_xer_so 1'0 + assign \xer_so_ok$47 1'0 + assign { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$51 + wire width 1 \p_valid_i$48 process $group_25 - assign \p_valid_i$51 1'0 - assign \p_valid_i$51 \p_valid_i + assign \p_valid_i$48 1'0 + assign \p_valid_i$48 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" @@ -36644,28 +37017,28 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $52 + wire width 1 $49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $53 + cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$51 + connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $52 + connect \Y $49 end process $group_27 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $52 + assign \p_valid_i_p_ready_o $49 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$54 + wire width 2 \muxid$51 process $group_28 - assign \muxid$54 2'00 - assign \muxid$54 \output_muxid$26 + assign \muxid$51 2'00 + assign \muxid$51 \output_muxid$24 sync init end attribute \enum_base_type "MicrOp" @@ -36742,7 +37115,7 @@ module \logical_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$55 + wire width 7 \logical_op__insn_type$52 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -36756,100 +37129,90 @@ module \logical_pipe2 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$56 + wire width 11 \logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$57 + wire width 64 \logical_op__imm_data__data$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$58 + wire width 1 \logical_op__imm_data__ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$59 + wire width 1 \logical_op__rc__rc$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$60 + wire width 1 \logical_op__rc__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$61 + wire width 1 \logical_op__oe__oe$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$62 + wire width 1 \logical_op__oe__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$63 + wire width 1 \logical_op__invert_in$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$64 + wire width 1 \logical_op__zero_a$61 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$65 + wire width 2 \logical_op__input_carry$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$66 + wire width 1 \logical_op__invert_out$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$67 + wire width 1 \logical_op__write_cr0$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$68 + wire width 1 \logical_op__output_carry$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$69 + wire width 1 \logical_op__is_32bit$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$70 + wire width 1 \logical_op__is_signed$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$71 + wire width 4 \logical_op__data_len$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$72 + wire width 32 \logical_op__insn$69 process $group_29 - assign \logical_op__insn_type$55 7'0000000 - assign \logical_op__fn_unit$56 11'00000000000 - assign \logical_op__imm_data__imm$57 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$58 1'0 - assign \logical_op__rc__rc$59 1'0 - assign \logical_op__rc__rc_ok$60 1'0 - assign \logical_op__oe__oe$61 1'0 - assign \logical_op__oe__oe_ok$62 1'0 - assign \logical_op__invert_in$63 1'0 - assign \logical_op__zero_a$64 1'0 - assign \logical_op__input_carry$65 2'00 - assign \logical_op__invert_out$66 1'0 - assign \logical_op__write_cr0$67 1'0 - assign \logical_op__output_carry$68 1'0 - assign \logical_op__is_32bit$69 1'0 - assign \logical_op__is_signed$70 1'0 - assign \logical_op__data_len$71 4'0000 - assign \logical_op__insn$72 32'00000000000000000000000000000000 - assign { \logical_op__insn$72 \logical_op__data_len$71 \logical_op__is_signed$70 \logical_op__is_32bit$69 \logical_op__output_carry$68 \logical_op__write_cr0$67 \logical_op__invert_out$66 \logical_op__input_carry$65 \logical_op__zero_a$64 \logical_op__invert_in$63 { \logical_op__oe__oe_ok$62 \logical_op__oe__oe$61 } { \logical_op__rc__rc_ok$60 \logical_op__rc__rc$59 } { \logical_op__imm_data__imm_ok$58 \logical_op__imm_data__imm$57 } \logical_op__fn_unit$56 \logical_op__insn_type$55 } { \output_logical_op__insn$44 \output_logical_op__data_len$43 \output_logical_op__is_signed$42 \output_logical_op__is_32bit$41 \output_logical_op__output_carry$40 \output_logical_op__write_cr0$39 \output_logical_op__invert_out$38 \output_logical_op__input_carry$37 \output_logical_op__zero_a$36 \output_logical_op__invert_in$35 { \output_logical_op__oe__oe_ok$34 \output_logical_op__oe__oe$33 } { \output_logical_op__rc__rc_ok$32 \output_logical_op__rc__rc$31 } { \output_logical_op__imm_data__imm_ok$30 \output_logical_op__imm_data__imm$29 } \output_logical_op__fn_unit$28 \output_logical_op__insn_type$27 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$74 + assign \logical_op__insn_type$52 7'0000000 + assign \logical_op__fn_unit$53 11'00000000000 + assign \logical_op__imm_data__data$54 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$55 1'0 + assign \logical_op__rc__rc$56 1'0 + assign \logical_op__rc__ok$57 1'0 + assign \logical_op__oe__oe$58 1'0 + assign \logical_op__oe__ok$59 1'0 + assign \logical_op__invert_in$60 1'0 + assign \logical_op__zero_a$61 1'0 + assign \logical_op__input_carry$62 2'00 + assign \logical_op__invert_out$63 1'0 + assign \logical_op__write_cr0$64 1'0 + assign \logical_op__output_carry$65 1'0 + assign \logical_op__is_32bit$66 1'0 + assign \logical_op__is_signed$67 1'0 + assign \logical_op__data_len$68 4'0000 + assign \logical_op__insn$69 32'00000000000000000000000000000000 + assign { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 { \logical_op__oe__ok$59 \logical_op__oe__oe$58 } { \logical_op__rc__ok$57 \logical_op__rc__rc$56 } { \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 } \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 { \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 } { \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 } { \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 } \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$71 process $group_47 - assign \o$73 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$74 1'0 - assign { \o_ok$74 \o$73 } { \output_o_ok$46 \output_o$45 } + assign \o$70 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$71 1'0 + assign { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$75 + wire width 4 \cr_a$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$76 + wire width 1 \cr_a_ok$73 process $group_49 - assign \cr_a$75 4'0000 - assign \cr_a_ok$76 1'0 - assign { \cr_a_ok$76 \cr_a$75 } { \output_cr_a_ok \output_cr_a$47 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$78 - process $group_51 - assign \xer_ca$77 2'00 - assign \xer_ca_ok$78 1'0 - assign { \xer_ca_ok$78 \xer_ca$77 } { \output_xer_ca_ok \output_xer_ca$48 } + assign \cr_a$72 4'0000 + assign \cr_a_ok$73 1'0 + assign { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_53 + process $group_51 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -36870,31 +37233,31 @@ module \logical_pipe2 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_54 + process $group_52 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$54 + assign \muxid$1$next \muxid$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$54 + assign \muxid$1$next \muxid$51 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_55 + process $group_53 assign \logical_op__insn_type$2$next \logical_op__insn_type$2 assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__imm_data__data$4$next \logical_op__imm_data__data$4 + assign \logical_op__imm_data__ok$5$next \logical_op__imm_data__ok$5 assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__rc__ok$7$next \logical_op__rc__ok$7 assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__oe__ok$9$next \logical_op__oe__ok$9 assign \logical_op__invert_in$10$next \logical_op__invert_in$10 assign \logical_op__zero_a$11$next \logical_op__zero_a$11 assign \logical_op__input_carry$12$next \logical_op__input_carry$12 @@ -36909,30 +37272,30 @@ module \logical_pipe2 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$72 \logical_op__data_len$71 \logical_op__is_signed$70 \logical_op__is_32bit$69 \logical_op__output_carry$68 \logical_op__write_cr0$67 \logical_op__invert_out$66 \logical_op__input_carry$65 \logical_op__zero_a$64 \logical_op__invert_in$63 { \logical_op__oe__oe_ok$62 \logical_op__oe__oe$61 } { \logical_op__rc__rc_ok$60 \logical_op__rc__rc$59 } { \logical_op__imm_data__imm_ok$58 \logical_op__imm_data__imm$57 } \logical_op__fn_unit$56 \logical_op__insn_type$55 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 { \logical_op__oe__ok$59 \logical_op__oe__oe$58 } { \logical_op__rc__ok$57 \logical_op__rc__rc$56 } { \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 } \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$72 \logical_op__data_len$71 \logical_op__is_signed$70 \logical_op__is_32bit$69 \logical_op__output_carry$68 \logical_op__write_cr0$67 \logical_op__invert_out$66 \logical_op__input_carry$65 \logical_op__zero_a$64 \logical_op__invert_in$63 { \logical_op__oe__oe_ok$62 \logical_op__oe__oe$61 } { \logical_op__rc__rc_ok$60 \logical_op__rc__rc$59 } { \logical_op__imm_data__imm_ok$58 \logical_op__imm_data__imm$57 } \logical_op__fn_unit$56 \logical_op__insn_type$55 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 { \logical_op__oe__ok$59 \logical_op__oe__oe$58 } { \logical_op__rc__ok$57 \logical_op__rc__rc$56 } { \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 } \logical_op__fn_unit$53 \logical_op__insn_type$52 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5$next 1'0 assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__rc__ok$7$next 1'0 assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 + assign \logical_op__oe__ok$9$next 1'0 end sync init update \logical_op__insn_type$2 7'0000000 update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__ok$5 1'0 update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__rc__ok$7 1'0 update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__oe__ok$9 1'0 update \logical_op__invert_in$10 1'0 update \logical_op__zero_a$11 1'0 update \logical_op__input_carry$12 2'00 @@ -36946,12 +37309,12 @@ module \logical_pipe2 sync posedge \coresync_clk update \logical_op__insn_type$2 \logical_op__insn_type$2$next update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__imm_data__data$4 \logical_op__imm_data__data$4$next + update \logical_op__imm_data__ok$5 \logical_op__imm_data__ok$5$next update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__rc__ok$7 \logical_op__rc__ok$7$next update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__oe__ok$9 \logical_op__oe__ok$9$next update \logical_op__invert_in$10 \logical_op__invert_in$10$next update \logical_op__zero_a$11 \logical_op__zero_a$11$next update \logical_op__input_carry$12 \logical_op__input_carry$12$next @@ -36963,17 +37326,17 @@ module \logical_pipe2 update \logical_op__data_len$18 \logical_op__data_len$18$next update \logical_op__insn$19 \logical_op__insn$19$next end - process $group_73 + process $group_71 assign \o$20$next \o$20 assign \o_ok$21$next \o_ok$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$21$next \o$20$next } { \o_ok$74 \o$73 } + assign { \o_ok$21$next \o$20$next } { \o_ok$71 \o$70 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$21$next \o$20$next } { \o_ok$74 \o$73 } + assign { \o_ok$21$next \o$20$next } { \o_ok$71 \o$70 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -36987,17 +37350,17 @@ module \logical_pipe2 update \o$20 \o$20$next update \o_ok$21 \o_ok$21$next end - process $group_75 + process $group_73 assign \cr_a$22$next \cr_a$22 assign \cr_a_ok$23$next \cr_a_ok$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$76 \cr_a$75 } + assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$73 \cr_a$72 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$76 \cr_a$75 } + assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$73 \cr_a$72 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -37011,36 +37374,12 @@ module \logical_pipe2 update \cr_a$22 \cr_a$22$next update \cr_a_ok$23 \cr_a_ok$23$next end - process $group_77 - assign \xer_ca$24$next \xer_ca$24 - assign \xer_ca_ok$25$next \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$78 \xer_ca$77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$78 \xer_ca$77 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$25$next 1'0 - end - sync init - update \xer_ca$24 2'00 - update \xer_ca_ok$25 1'0 - sync posedge \coresync_clk - update \xer_ca$24 \xer_ca$24$next - update \xer_ca_ok$25 \xer_ca_ok$25$next - end - process $group_79 + process $group_75 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_80 + process $group_76 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init @@ -37049,20 +37388,18 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" module \alu_logical0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ca_ok - attribute \src "simple/issuer.py:102" - wire width 1 input 4 \coresync_rst + attribute \src "simple/issuer.py:141" + wire width 1 input 3 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o + wire width 1 output 4 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i + wire width 1 input 5 \n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -37137,7 +37474,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \logical_op__insn_type + wire width 7 input 6 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -37151,57 +37488,57 @@ module \alu_logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 8 \logical_op__fn_unit + wire width 11 input 7 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \logical_op__imm_data__imm + wire width 64 input 8 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__imm_data__imm_ok + wire width 1 input 9 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__rc__rc + wire width 1 input 10 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__rc__rc_ok + wire width 1 input 11 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__oe__oe + wire width 1 input 12 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__oe__oe_ok + wire width 1 input 13 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__invert_in + wire width 1 input 14 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__zero_a + wire width 1 input 15 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \logical_op__input_carry + wire width 2 input 16 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__invert_out + wire width 1 input 17 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__write_cr0 + wire width 1 input 18 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__output_carry + wire width 1 input 19 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \logical_op__is_32bit + wire width 1 input 20 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \logical_op__is_signed + wire width 1 input 21 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 23 \logical_op__data_len + wire width 4 input 22 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 24 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 25 \o + wire width 32 input 23 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 26 \cr_a + wire width 64 output 24 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 27 \xer_ca + wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \ra + wire width 64 input 26 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 29 \rb + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 28 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 30 \p_valid_i + wire width 1 input 29 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 31 \p_ready_o + wire width 1 output 30 \p_ready_o cell \p$43 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -37306,17 +37643,17 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_pipe1_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe1_logical_op__imm_data__imm + wire width 64 \logical_pipe1_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe1_logical_op__imm_data__imm_ok + wire width 1 \logical_pipe1_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe1_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe1_logical_op__rc__rc_ok + wire width 1 \logical_pipe1_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe1_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe1_logical_op__oe__oe_ok + wire width 1 \logical_pipe1_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe1_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37350,9 +37687,9 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \logical_pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \logical_pipe1_xer_ca + wire width 1 \logical_pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe1_xer_ca_ok + wire width 1 \logical_pipe1_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 \logical_pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -37449,17 +37786,17 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_pipe1_logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe1_logical_op__imm_data__imm$4 + wire width 64 \logical_pipe1_logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe1_logical_op__imm_data__imm_ok$5 + wire width 1 \logical_pipe1_logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe1_logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe1_logical_op__rc__rc_ok$7 + wire width 1 \logical_pipe1_logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe1_logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe1_logical_op__oe__oe_ok$9 + wire width 1 \logical_pipe1_logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe1_logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37488,6 +37825,8 @@ module \alu_logical0 wire width 64 \logical_pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \logical_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \logical_pipe1_xer_so$20 cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -37496,12 +37835,12 @@ module \alu_logical0 connect \muxid \logical_pipe1_muxid connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit - connect \logical_op__imm_data__imm \logical_pipe1_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \logical_pipe1_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data + connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc - connect \logical_op__rc__rc_ok \logical_pipe1_logical_op__rc__rc_ok + connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe - connect \logical_op__oe__oe_ok \logical_pipe1_logical_op__oe__oe_ok + connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry @@ -37516,19 +37855,19 @@ module \alu_logical0 connect \o_ok \logical_pipe1_o_ok connect \cr_a \logical_pipe1_cr_a connect \cr_a_ok \logical_pipe1_cr_a_ok - connect \xer_ca \logical_pipe1_xer_ca - connect \xer_ca_ok \logical_pipe1_xer_ca_ok + connect \xer_so \logical_pipe1_xer_so + connect \xer_so_ok \logical_pipe1_xer_so_ok connect \p_valid_i \logical_pipe1_p_valid_i connect \p_ready_o \logical_pipe1_p_ready_o connect \muxid$1 \logical_pipe1_muxid$1 connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 - connect \logical_op__imm_data__imm$4 \logical_pipe1_logical_op__imm_data__imm$4 - connect \logical_op__imm_data__imm_ok$5 \logical_pipe1_logical_op__imm_data__imm_ok$5 + connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 + connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 - connect \logical_op__rc__rc_ok$7 \logical_pipe1_logical_op__rc__rc_ok$7 + connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 - connect \logical_op__oe__oe_ok$9 \logical_pipe1_logical_op__oe__oe_ok$9 + connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 @@ -37541,6 +37880,7 @@ module \alu_logical0 connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 connect \ra \logical_pipe1_ra connect \rb \logical_pipe1_rb + connect \xer_so$20 \logical_pipe1_xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 \logical_pipe2_p_valid_i @@ -37638,17 +37978,17 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_pipe2_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe2_logical_op__imm_data__imm + wire width 64 \logical_pipe2_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__imm_data__imm_ok + wire width 1 \logical_pipe2_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe2_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__rc_ok + wire width 1 \logical_pipe2_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe2_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__oe_ok + wire width 1 \logical_pipe2_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_pipe2_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37682,15 +38022,15 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \logical_pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \logical_pipe2_xer_ca + wire width 1 \logical_pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_xer_ca_ok + wire width 1 \logical_pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \logical_pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire width 1 \logical_pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe2_muxid$20 + wire width 2 \logical_pipe2_muxid$21 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -37765,7 +38105,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe2_logical_op__insn_type$21 + wire width 7 \logical_pipe2_logical_op__insn_type$22 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -37779,55 +38119,51 @@ module \alu_logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_pipe2_logical_op__fn_unit$22 + wire width 11 \logical_pipe2_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe2_logical_op__imm_data__imm$23 + wire width 64 \logical_pipe2_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__imm_data__imm_ok$24 + wire width 1 \logical_pipe2_logical_op__imm_data__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__rc$25 + wire width 1 \logical_pipe2_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__rc_ok$26 + wire width 1 \logical_pipe2_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__oe$27 + wire width 1 \logical_pipe2_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__oe_ok$28 + wire width 1 \logical_pipe2_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__invert_in$29 + wire width 1 \logical_pipe2_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__zero_a$30 + wire width 1 \logical_pipe2_logical_op__zero_a$31 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe2_logical_op__input_carry$31 + wire width 2 \logical_pipe2_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__invert_out$32 + wire width 1 \logical_pipe2_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__write_cr0$33 + wire width 1 \logical_pipe2_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__output_carry$34 + wire width 1 \logical_pipe2_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__is_32bit$35 + wire width 1 \logical_pipe2_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__is_signed$36 + wire width 1 \logical_pipe2_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe2_logical_op__data_len$37 + wire width 4 \logical_pipe2_logical_op__data_len$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe2_logical_op__insn$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \logical_pipe2_o$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_o_ok$40 + wire width 32 \logical_pipe2_logical_op__insn$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \logical_pipe2_cr_a$41 + wire width 64 \logical_pipe2_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_cr_a_ok$42 + wire width 1 \logical_pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \logical_pipe2_xer_ca$43 + wire width 4 \logical_pipe2_cr_a$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_xer_ca_ok$44 + wire width 1 \logical_pipe2_cr_a_ok$43 cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -37836,12 +38172,12 @@ module \alu_logical0 connect \muxid \logical_pipe2_muxid connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit - connect \logical_op__imm_data__imm \logical_pipe2_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \logical_pipe2_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data + connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc - connect \logical_op__rc__rc_ok \logical_pipe2_logical_op__rc__rc_ok + connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe - connect \logical_op__oe__oe_ok \logical_pipe2_logical_op__oe__oe_ok + connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry @@ -37856,35 +38192,33 @@ module \alu_logical0 connect \o_ok \logical_pipe2_o_ok connect \cr_a \logical_pipe2_cr_a connect \cr_a_ok \logical_pipe2_cr_a_ok - connect \xer_ca \logical_pipe2_xer_ca - connect \xer_ca_ok \logical_pipe2_xer_ca_ok + connect \xer_so \logical_pipe2_xer_so + connect \xer_so_ok \logical_pipe2_xer_so_ok connect \n_valid_o \logical_pipe2_n_valid_o connect \n_ready_i \logical_pipe2_n_ready_i - connect \muxid$1 \logical_pipe2_muxid$20 - connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$21 - connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$22 - connect \logical_op__imm_data__imm$4 \logical_pipe2_logical_op__imm_data__imm$23 - connect \logical_op__imm_data__imm_ok$5 \logical_pipe2_logical_op__imm_data__imm_ok$24 - connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$25 - connect \logical_op__rc__rc_ok$7 \logical_pipe2_logical_op__rc__rc_ok$26 - connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$27 - connect \logical_op__oe__oe_ok$9 \logical_pipe2_logical_op__oe__oe_ok$28 - connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$29 - connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$30 - connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$31 - connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$32 - connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$33 - connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$34 - connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$35 - connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$36 - connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$37 - connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$38 - connect \o$20 \logical_pipe2_o$39 - connect \o_ok$21 \logical_pipe2_o_ok$40 - connect \cr_a$22 \logical_pipe2_cr_a$41 - connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$42 - connect \xer_ca$24 \logical_pipe2_xer_ca$43 - connect \xer_ca_ok$25 \logical_pipe2_xer_ca_ok$44 + connect \muxid$1 \logical_pipe2_muxid$21 + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 + connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 + connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 + connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 + connect \o$20 \logical_pipe2_o$40 + connect \o_ok$21 \logical_pipe2_o_ok$41 + connect \cr_a$22 \logical_pipe2_cr_a$42 + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 end process $group_0 assign \logical_pipe2_p_valid_i 1'0 @@ -37904,12 +38238,12 @@ module \alu_logical0 process $group_3 assign \logical_pipe2_logical_op__insn_type 7'0000000 assign \logical_pipe2_logical_op__fn_unit 11'00000000000 - assign \logical_pipe2_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe2_logical_op__imm_data__imm_ok 1'0 + assign \logical_pipe2_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe2_logical_op__imm_data__ok 1'0 assign \logical_pipe2_logical_op__rc__rc 1'0 - assign \logical_pipe2_logical_op__rc__rc_ok 1'0 + assign \logical_pipe2_logical_op__rc__ok 1'0 assign \logical_pipe2_logical_op__oe__oe 1'0 - assign \logical_pipe2_logical_op__oe__oe_ok 1'0 + assign \logical_pipe2_logical_op__oe__ok 1'0 assign \logical_pipe2_logical_op__invert_in 1'0 assign \logical_pipe2_logical_op__zero_a 1'0 assign \logical_pipe2_logical_op__input_carry 2'00 @@ -37920,7 +38254,7 @@ module \alu_logical0 assign \logical_pipe2_logical_op__is_signed 1'0 assign \logical_pipe2_logical_op__data_len 4'0000 assign \logical_pipe2_logical_op__insn 32'00000000000000000000000000000000 - assign { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in { \logical_pipe2_logical_op__oe__oe_ok \logical_pipe2_logical_op__oe__oe } { \logical_pipe2_logical_op__rc__rc_ok \logical_pipe2_logical_op__rc__rc } { \logical_pipe2_logical_op__imm_data__imm_ok \logical_pipe2_logical_op__imm_data__imm } \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in { \logical_pipe1_logical_op__oe__oe_ok \logical_pipe1_logical_op__oe__oe } { \logical_pipe1_logical_op__rc__rc_ok \logical_pipe1_logical_op__rc__rc } { \logical_pipe1_logical_op__imm_data__imm_ok \logical_pipe1_logical_op__imm_data__imm } \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } + assign { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in { \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe } { \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc } { \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data } \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in { \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe } { \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc } { \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data } \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } sync init end process $group_21 @@ -37936,9 +38270,9 @@ module \alu_logical0 sync init end process $group_25 - assign \logical_pipe2_xer_ca 2'00 - assign \logical_pipe2_xer_ca_ok 1'0 - assign { \logical_pipe2_xer_ca_ok \logical_pipe2_xer_ca } { \logical_pipe1_xer_ca_ok \logical_pipe1_xer_ca } + assign \logical_pipe2_xer_so 1'0 + assign \logical_pipe2_xer_so_ok 1'0 + assign { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } sync init end process $group_27 @@ -37961,12 +38295,12 @@ module \alu_logical0 process $group_30 assign \logical_pipe1_logical_op__insn_type$2 7'0000000 assign \logical_pipe1_logical_op__fn_unit$3 11'00000000000 - assign \logical_pipe1_logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe1_logical_op__imm_data__imm_ok$5 1'0 + assign \logical_pipe1_logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe1_logical_op__imm_data__ok$5 1'0 assign \logical_pipe1_logical_op__rc__rc$6 1'0 - assign \logical_pipe1_logical_op__rc__rc_ok$7 1'0 + assign \logical_pipe1_logical_op__rc__ok$7 1'0 assign \logical_pipe1_logical_op__oe__oe$8 1'0 - assign \logical_pipe1_logical_op__oe__oe_ok$9 1'0 + assign \logical_pipe1_logical_op__oe__ok$9 1'0 assign \logical_pipe1_logical_op__invert_in$10 1'0 assign \logical_pipe1_logical_op__zero_a$11 1'0 assign \logical_pipe1_logical_op__input_carry$12 2'00 @@ -37977,7 +38311,7 @@ module \alu_logical0 assign \logical_pipe1_logical_op__is_signed$17 1'0 assign \logical_pipe1_logical_op__data_len$18 4'0000 assign \logical_pipe1_logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 { \logical_pipe1_logical_op__oe__oe_ok$9 \logical_pipe1_logical_op__oe__oe$8 } { \logical_pipe1_logical_op__rc__rc_ok$7 \logical_pipe1_logical_op__rc__rc$6 } { \logical_pipe1_logical_op__imm_data__imm_ok$5 \logical_pipe1_logical_op__imm_data__imm$4 } \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 { \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 } { \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 } { \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 } \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end process $group_48 @@ -37991,20 +38325,25 @@ module \alu_logical0 sync init end process $group_50 + assign \logical_pipe1_xer_so$20 1'0 + assign \logical_pipe1_xer_so$20 \xer_so + sync init + end + process $group_51 assign \n_valid_o 1'0 assign \n_valid_o \logical_pipe2_n_valid_o sync init end - process $group_51 + process $group_52 assign \logical_pipe2_n_ready_i 1'0 assign \logical_pipe2_n_ready_i \n_ready_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$45 - process $group_52 - assign \muxid$45 2'00 - assign \muxid$45 \logical_pipe2_muxid$20 + wire width 2 \muxid$44 + process $group_53 + assign \muxid$44 2'00 + assign \muxid$44 \logical_pipe2_muxid$21 sync init end attribute \enum_base_type "MicrOp" @@ -38081,7 +38420,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$46 + wire width 7 \logical_op__insn_type$45 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -38095,81 +38434,75 @@ module \alu_logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$47 + wire width 11 \logical_op__fn_unit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$48 + wire width 64 \logical_op__imm_data__data$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$49 + wire width 1 \logical_op__imm_data__ok$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$50 + wire width 1 \logical_op__rc__rc$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$51 + wire width 1 \logical_op__rc__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$52 + wire width 1 \logical_op__oe__oe$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$53 + wire width 1 \logical_op__oe__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$54 + wire width 1 \logical_op__invert_in$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$55 + wire width 1 \logical_op__zero_a$54 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$56 + wire width 2 \logical_op__input_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$57 + wire width 1 \logical_op__invert_out$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$58 + wire width 1 \logical_op__write_cr0$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$59 + wire width 1 \logical_op__output_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$60 + wire width 1 \logical_op__is_32bit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$61 + wire width 1 \logical_op__is_signed$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$62 + wire width 4 \logical_op__data_len$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$63 - process $group_53 - assign \logical_op__insn_type$46 7'0000000 - assign \logical_op__fn_unit$47 11'00000000000 - assign \logical_op__imm_data__imm$48 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$49 1'0 - assign \logical_op__rc__rc$50 1'0 - assign \logical_op__rc__rc_ok$51 1'0 - assign \logical_op__oe__oe$52 1'0 - assign \logical_op__oe__oe_ok$53 1'0 - assign \logical_op__invert_in$54 1'0 - assign \logical_op__zero_a$55 1'0 - assign \logical_op__input_carry$56 2'00 - assign \logical_op__invert_out$57 1'0 - assign \logical_op__write_cr0$58 1'0 - assign \logical_op__output_carry$59 1'0 - assign \logical_op__is_32bit$60 1'0 - assign \logical_op__is_signed$61 1'0 - assign \logical_op__data_len$62 4'0000 - assign \logical_op__insn$63 32'00000000000000000000000000000000 - assign { \logical_op__insn$63 \logical_op__data_len$62 \logical_op__is_signed$61 \logical_op__is_32bit$60 \logical_op__output_carry$59 \logical_op__write_cr0$58 \logical_op__invert_out$57 \logical_op__input_carry$56 \logical_op__zero_a$55 \logical_op__invert_in$54 { \logical_op__oe__oe_ok$53 \logical_op__oe__oe$52 } { \logical_op__rc__rc_ok$51 \logical_op__rc__rc$50 } { \logical_op__imm_data__imm_ok$49 \logical_op__imm_data__imm$48 } \logical_op__fn_unit$47 \logical_op__insn_type$46 } { \logical_pipe2_logical_op__insn$38 \logical_pipe2_logical_op__data_len$37 \logical_pipe2_logical_op__is_signed$36 \logical_pipe2_logical_op__is_32bit$35 \logical_pipe2_logical_op__output_carry$34 \logical_pipe2_logical_op__write_cr0$33 \logical_pipe2_logical_op__invert_out$32 \logical_pipe2_logical_op__input_carry$31 \logical_pipe2_logical_op__zero_a$30 \logical_pipe2_logical_op__invert_in$29 { \logical_pipe2_logical_op__oe__oe_ok$28 \logical_pipe2_logical_op__oe__oe$27 } { \logical_pipe2_logical_op__rc__rc_ok$26 \logical_pipe2_logical_op__rc__rc$25 } { \logical_pipe2_logical_op__imm_data__imm_ok$24 \logical_pipe2_logical_op__imm_data__imm$23 } \logical_pipe2_logical_op__fn_unit$22 \logical_pipe2_logical_op__insn_type$21 } + wire width 32 \logical_op__insn$62 + process $group_54 + assign \logical_op__insn_type$45 7'0000000 + assign \logical_op__fn_unit$46 11'00000000000 + assign \logical_op__imm_data__data$47 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$48 1'0 + assign \logical_op__rc__rc$49 1'0 + assign \logical_op__rc__ok$50 1'0 + assign \logical_op__oe__oe$51 1'0 + assign \logical_op__oe__ok$52 1'0 + assign \logical_op__invert_in$53 1'0 + assign \logical_op__zero_a$54 1'0 + assign \logical_op__input_carry$55 2'00 + assign \logical_op__invert_out$56 1'0 + assign \logical_op__write_cr0$57 1'0 + assign \logical_op__output_carry$58 1'0 + assign \logical_op__is_32bit$59 1'0 + assign \logical_op__is_signed$60 1'0 + assign \logical_op__data_len$61 4'0000 + assign \logical_op__insn$62 32'00000000000000000000000000000000 + assign { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 { \logical_op__oe__ok$52 \logical_op__oe__oe$51 } { \logical_op__rc__ok$50 \logical_op__rc__rc$49 } { \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 } \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 { \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 } { \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 } { \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 } \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } sync init end - process $group_71 + process $group_72 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o_ok 1'0 - assign { \o_ok \o } { \logical_pipe2_o_ok$40 \logical_pipe2_o$39 } + assign { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } sync init end - process $group_73 + process $group_74 assign \cr_a 4'0000 assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$42 \logical_pipe2_cr_a$41 } - sync init - end - process $group_75 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \logical_pipe2_xer_ca_ok$44 \logical_pipe2_xer_ca$43 } + assign { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } sync init end connect \muxid 2'00 @@ -38177,52 +38510,52 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" module \src_l$52 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 input 2 \s_src + wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 input 3 \r_src + wire width 3 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 output 4 \q_src + wire width 3 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int + wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int$next + wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $1 + wire width 3 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \r_src connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $3 + wire width 3 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $5 + wire width 3 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A $3 connect \B \s_src connect \Y $5 @@ -38233,88 +38566,88 @@ module \src_l$52 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 2'00 + assign \q_int$next 3'000 end sync init - update \q_int 2'00 + update \q_int 3'000 sync posedge \coresync_clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $7 + wire width 3 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \r_src connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $9 + wire width 3 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $11 + wire width 3 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A $9 connect \B \s_src connect \Y $11 end process $group_1 - assign \q_src 2'00 + assign \q_src 3'000 assign \q_src $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 2 \qn_src + wire width 3 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 2 $13 + wire width 3 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \q_src connect \Y $13 end process $group_2 - assign \qn_src 2'00 + assign \qn_src 3'000 assign \qn_src $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 2 \qlq_src + wire width 3 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 2 $15 + wire width 3 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_src 2'00 + assign \qlq_src 3'000 assign \qlq_src $15 sync init end @@ -38322,9 +38655,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" module \opc_l$53 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -38467,52 +38800,52 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" module \req_l$54 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req + wire width 2 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req + wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req + wire width 2 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int + wire width 2 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next + wire width 2 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \r_req connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 + wire width 2 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 + wire width 2 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A $3 connect \B \s_req connect \Y $5 @@ -38523,88 +38856,88 @@ module \req_l$54 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 3'000 + assign \q_int$next 2'00 end sync init - update \q_int 3'000 + update \q_int 2'00 sync posedge \coresync_clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 + wire width 2 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \r_req connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 + wire width 2 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 + wire width 2 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A $9 connect \B \s_req connect \Y $11 end process $group_1 - assign \q_req 3'000 + assign \q_req 2'00 assign \q_req $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req + wire width 2 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 + wire width 2 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_req connect \Y $13 end process $group_2 - assign \qn_req 3'000 + assign \qn_req 2'00 assign \qn_req $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req + wire width 2 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 + wire width 2 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_req 3'000 + assign \qlq_req 2'00 assign \qlq_req $15 sync init end @@ -38612,9 +38945,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" module \rst_l$55 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -38757,9 +39090,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" module \rok_l$56 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -38902,9 +39235,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" module \alui_l$57 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -39047,9 +39380,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" module \alu_l$58 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -39192,7 +39525,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" module \logical0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -39284,17 +39617,17 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_logical0__imm_data__imm + wire width 64 input 3 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_logical0__imm_data__imm_ok + wire width 1 input 4 \oper_i_alu_logical0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_logical0__rc__rc_ok + wire width 1 input 6 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_logical0__oe__oe_ok + wire width 1 input 8 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -39324,33 +39657,31 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire width 1 output 20 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 2 input 21 \cu_rdmaskn_i + wire width 3 input 21 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 22 \cu_rd__rel_o + wire width 3 output 22 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 23 \cu_rd__go_i + wire width 3 input 23 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 24 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 26 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \o_ok + wire width 1 output 27 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 27 \cu_wr__rel_o + wire width 2 output 28 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 28 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 29 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \cr_a_ok + wire width 2 input 29 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 31 \dest2_o + wire width 64 output 30 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \xer_ca_ok + wire width 1 output 31 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 33 \dest3_o - attribute \src "simple/issuer.py:102" - wire width 1 input 34 \coresync_rst + wire width 4 output 32 \dest2_o + attribute \src "simple/issuer.py:141" + wire width 1 input 33 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_logical0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -39449,29 +39780,29 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_logical0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_logical0_logical_op__imm_data__imm + wire width 64 \alu_logical0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_logical0_logical_op__imm_data__imm$next + wire width 64 \alu_logical0_logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__imm_data__imm_ok + wire width 1 \alu_logical0_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__imm_data__imm_ok$next + wire width 1 \alu_logical0_logical_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_logical0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_logical0_logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__rc__rc_ok + wire width 1 \alu_logical0_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__rc__rc_ok$next + wire width 1 \alu_logical0_logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_logical0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_logical0_logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__oe_ok + wire width 1 \alu_logical0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__oe_ok$next + wire width 1 \alu_logical0_logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_logical0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -39520,12 +39851,12 @@ module \logical0 wire width 64 \alu_logical0_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 4 \alu_logical0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_logical0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_logical0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \alu_logical0_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 \alu_logical0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -39534,18 +39865,17 @@ module \logical0 connect \coresync_clk \coresync_clk connect \o_ok \o_ok connect \cr_a_ok \cr_a_ok - connect \xer_ca_ok \xer_ca_ok connect \coresync_rst \coresync_rst connect \n_valid_o \alu_logical0_n_valid_o connect \n_ready_i \alu_logical0_n_ready_i connect \logical_op__insn_type \alu_logical0_logical_op__insn_type connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit - connect \logical_op__imm_data__imm \alu_logical0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc_ok + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe_ok + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok connect \logical_op__invert_in \alu_logical0_logical_op__invert_in connect \logical_op__zero_a \alu_logical0_logical_op__zero_a connect \logical_op__input_carry \alu_logical0_logical_op__input_carry @@ -39558,22 +39888,22 @@ module \logical0 connect \logical_op__insn \alu_logical0_logical_op__insn connect \o \alu_logical0_o connect \cr_a \alu_logical0_cr_a - connect \xer_ca \alu_logical0_xer_ca connect \ra \alu_logical0_ra connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so connect \p_valid_i \alu_logical0_p_valid_i connect \p_ready_o \alu_logical0_p_ready_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_s_src + wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_s_src$next + wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \src_l_r_src + wire width 3 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \src_l_r_src$next + wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 \src_l_q_src + wire width 3 \src_l_q_src cell \src_l$52 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -39599,15 +39929,15 @@ module \logical0 connect \q_opc \opc_l_q_opc end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req + wire width 2 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req + wire width 2 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next + wire width 2 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req + wire width 2 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next + wire width 2 \req_l_r_req$next cell \req_l$54 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -39694,24 +40024,24 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 $3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 2 $4 + wire width 3 $4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o connect \Y $4 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 2 $6 + wire width 3 $6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $7 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A $4 connect \B \cu_rd__go_i connect \Y $6 @@ -39719,7 +40049,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A $6 connect \Y $3 @@ -39848,27 +40178,27 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 3 \alu_pulsem + wire width 2 \alu_pulsem process $group_8 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + assign \alu_pulsem 2'00 + assign \alu_pulsem { \alu_pulse \alu_pulse } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go + wire width 2 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next + wire width 2 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 3 $19 + wire width 2 $19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $20 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \B { \cu_busy_o \cu_busy_o } connect \Y $19 end process $group_9 @@ -39877,10 +40207,10 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \prev_wr_go$next 3'000 + assign \prev_wr_go$next 2'00 end sync init - update \prev_wr_go 3'000 + update \prev_wr_go 2'00 sync posedge \coresync_clk update \prev_wr_go \prev_wr_go$next end @@ -39891,26 +40221,26 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 1 $22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $23 + wire width 2 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o + wire width 2 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $24 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_wrmask_o connect \Y $23 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $25 + wire width 2 $25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $26 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B $23 connect \Y $25 @@ -39918,7 +40248,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_bool $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A $25 connect \Y $22 @@ -39956,7 +40286,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_bool $32 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $31 @@ -39966,7 +40296,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_bool $34 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $33 @@ -40015,14 +40345,14 @@ module \logical0 connect \Y $39 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $41 + wire width 2 $41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $42 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $41 @@ -40032,7 +40362,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $44 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 @@ -40058,7 +40388,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $48 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 @@ -40159,42 +40489,42 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w + wire width 2 \reset_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 $59 + wire width 2 $59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $60 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \B { \cu_go_die_i \cu_go_die_i } connect \Y $59 end process $group_15 - assign \reset_w 3'000 + assign \reset_w 2'00 assign \reset_w $59 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 2 \reset_r + wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 2 $61 + wire width 3 $61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $62 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i } + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $61 end process $group_16 - assign \reset_r 2'00 + assign \reset_r 3'000 assign \reset_r $61 sync init end @@ -40291,14 +40621,14 @@ module \logical0 end process $group_23 assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i } + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_s_src$next 2'00 + assign \src_l_s_src$next 3'000 end sync init - update \src_l_s_src 2'00 + update \src_l_s_src 3'000 sync posedge \coresync_clk update \src_l_s_src \src_l_s_src$next end @@ -40308,22 +40638,22 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_r_src$next 2'11 + assign \src_l_r_src$next 3'111 end sync init - update \src_l_r_src 2'11 + update \src_l_r_src 3'111 sync posedge \coresync_clk update \src_l_r_src \src_l_r_src$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 3 $65 + wire width 2 $65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $66 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $65 @@ -40334,22 +40664,22 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \req_l_s_req$next 3'000 + assign \req_l_s_req$next 2'00 end sync init - update \req_l_s_req 3'000 + update \req_l_s_req 2'00 sync posedge \coresync_clk update \req_l_s_req \req_l_s_req$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 3 $67 + wire width 2 $67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $68 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go connect \Y $67 @@ -40360,22 +40690,22 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \req_l_r_req$next 3'111 + assign \req_l_r_req$next 2'11 end sync init - update \req_l_r_req 3'111 + update \req_l_r_req 2'11 sync posedge \coresync_clk update \req_l_r_req \req_l_r_req$next end process $group_27 assign \alu_logical0_logical_op__insn_type$next \alu_logical0_logical_op__insn_type assign \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__fn_unit - assign \alu_logical0_logical_op__imm_data__imm$next \alu_logical0_logical_op__imm_data__imm - assign \alu_logical0_logical_op__imm_data__imm_ok$next \alu_logical0_logical_op__imm_data__imm_ok + assign \alu_logical0_logical_op__imm_data__data$next \alu_logical0_logical_op__imm_data__data + assign \alu_logical0_logical_op__imm_data__ok$next \alu_logical0_logical_op__imm_data__ok assign \alu_logical0_logical_op__rc__rc$next \alu_logical0_logical_op__rc__rc - assign \alu_logical0_logical_op__rc__rc_ok$next \alu_logical0_logical_op__rc__rc_ok + assign \alu_logical0_logical_op__rc__ok$next \alu_logical0_logical_op__rc__ok assign \alu_logical0_logical_op__oe__oe$next \alu_logical0_logical_op__oe__oe - assign \alu_logical0_logical_op__oe__oe_ok$next \alu_logical0_logical_op__oe__oe_ok + assign \alu_logical0_logical_op__oe__ok$next \alu_logical0_logical_op__oe__ok assign \alu_logical0_logical_op__invert_in$next \alu_logical0_logical_op__invert_in assign \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__zero_a assign \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__input_carry @@ -40390,27 +40720,27 @@ module \logical0 switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_logical0_logical_op__insn$next \alu_logical0_logical_op__data_len$next \alu_logical0_logical_op__is_signed$next \alu_logical0_logical_op__is_32bit$next \alu_logical0_logical_op__output_carry$next \alu_logical0_logical_op__write_cr0$next \alu_logical0_logical_op__invert_out$next \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__invert_in$next { \alu_logical0_logical_op__oe__oe_ok$next \alu_logical0_logical_op__oe__oe$next } { \alu_logical0_logical_op__rc__rc_ok$next \alu_logical0_logical_op__rc__rc$next } { \alu_logical0_logical_op__imm_data__imm_ok$next \alu_logical0_logical_op__imm_data__imm$next } \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { \alu_logical0_logical_op__insn$next \alu_logical0_logical_op__data_len$next \alu_logical0_logical_op__is_signed$next \alu_logical0_logical_op__is_32bit$next \alu_logical0_logical_op__output_carry$next \alu_logical0_logical_op__write_cr0$next \alu_logical0_logical_op__invert_out$next \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__invert_in$next { \alu_logical0_logical_op__oe__ok$next \alu_logical0_logical_op__oe__oe$next } { \alu_logical0_logical_op__rc__ok$next \alu_logical0_logical_op__rc__rc$next } { \alu_logical0_logical_op__imm_data__ok$next \alu_logical0_logical_op__imm_data__data$next } \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in { \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_logical0_logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_logical_op__imm_data__imm_ok$next 1'0 + assign \alu_logical0_logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_logical_op__imm_data__ok$next 1'0 assign \alu_logical0_logical_op__rc__rc$next 1'0 - assign \alu_logical0_logical_op__rc__rc_ok$next 1'0 + assign \alu_logical0_logical_op__rc__ok$next 1'0 assign \alu_logical0_logical_op__oe__oe$next 1'0 - assign \alu_logical0_logical_op__oe__oe_ok$next 1'0 + assign \alu_logical0_logical_op__oe__ok$next 1'0 end sync init update \alu_logical0_logical_op__insn_type 7'0000000 update \alu_logical0_logical_op__fn_unit 11'00000000000 - update \alu_logical0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_logical0_logical_op__imm_data__imm_ok 1'0 + update \alu_logical0_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_logical0_logical_op__imm_data__ok 1'0 update \alu_logical0_logical_op__rc__rc 1'0 - update \alu_logical0_logical_op__rc__rc_ok 1'0 + update \alu_logical0_logical_op__rc__ok 1'0 update \alu_logical0_logical_op__oe__oe 1'0 - update \alu_logical0_logical_op__oe__oe_ok 1'0 + update \alu_logical0_logical_op__oe__ok 1'0 update \alu_logical0_logical_op__invert_in 1'0 update \alu_logical0_logical_op__zero_a 1'0 update \alu_logical0_logical_op__input_carry 2'00 @@ -40424,12 +40754,12 @@ module \logical0 sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type \alu_logical0_logical_op__insn_type$next update \alu_logical0_logical_op__fn_unit \alu_logical0_logical_op__fn_unit$next - update \alu_logical0_logical_op__imm_data__imm \alu_logical0_logical_op__imm_data__imm$next - update \alu_logical0_logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm_ok$next + update \alu_logical0_logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data$next + update \alu_logical0_logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok$next update \alu_logical0_logical_op__rc__rc \alu_logical0_logical_op__rc__rc$next - update \alu_logical0_logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc_ok$next + update \alu_logical0_logical_op__rc__ok \alu_logical0_logical_op__rc__ok$next update \alu_logical0_logical_op__oe__oe \alu_logical0_logical_op__oe__oe$next - update \alu_logical0_logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe_ok$next + update \alu_logical0_logical_op__oe__ok \alu_logical0_logical_op__oe__ok$next update \alu_logical0_logical_op__invert_in \alu_logical0_logical_op__invert_in$next update \alu_logical0_logical_op__zero_a \alu_logical0_logical_op__zero_a$next update \alu_logical0_logical_op__input_carry \alu_logical0_logical_op__input_carry$next @@ -40511,41 +40841,6 @@ module \logical0 update \data_r1__cr_a \data_r1__cr_a$next update \data_r1__cr_a_ok \data_r1__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ca_ok$next - process $group_49 - assign \data_r2__xer_ca$next \data_r2__xer_ca - assign \data_r2__xer_ca_ok$next \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } { \xer_ca_ok \alu_logical0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__xer_ca_ok$next 1'0 - end - sync init - update \data_r2__xer_ca 2'00 - update \data_r2__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r2__xer_ca \data_r2__xer_ca$next - update \data_r2__xer_ca_ok \data_r2__xer_ca_ok$next - end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire width 1 $69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" @@ -40572,90 +40867,77 @@ module \logical0 connect \B \cu_busy_o connect \Y $71 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $73 - end - process $group_51 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $73 $71 $69 } + process $group_49 + assign \cu_wrmask_o 2'00 + assign \cu_wrmask_o { $71 $69 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire width 1 \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $75 + wire width 1 $73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $76 + cell $mux $74 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $75 + connect \Y $73 end - process $group_52 + process $group_50 assign \src_sel 1'0 - assign \src_sel $75 + assign \src_sel $73 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $77 + wire width 64 $75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $78 + cell $mux $76 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $77 + connect \Y $75 end - process $group_53 + process $group_51 assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $77 + assign \src_or_imm $75 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel$79 + wire width 1 \src_sel$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $80 + wire width 1 $78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $81 + cell $mux $79 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__imm_data__imm_ok - connect \Y $80 + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $78 end - process $group_54 - assign \src_sel$79 1'0 - assign \src_sel$79 $80 + process $group_52 + assign \src_sel$77 1'0 + assign \src_sel$77 $78 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm$82 + wire width 64 \src_or_imm$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $83 + wire width 64 $81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $84 + cell $mux $82 parameter \WIDTH 64 connect \A \src2_i - connect \B \alu_logical0_logical_op__imm_data__imm - connect \S \alu_logical0_logical_op__imm_data__imm_ok - connect \Y $83 + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $81 end - process $group_55 - assign \src_or_imm$82 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$82 $83 + process $group_53 + assign \src_or_imm$80 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$80 $81 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" @@ -40663,21 +40945,21 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $85 + wire width 64 $83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $86 + cell $mux $84 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $85 + connect \Y $83 end - process $group_56 + process $group_54 assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_ra $85 + assign \alu_logical0_ra $83 sync init end - process $group_57 + process $group_55 assign \src_r0$next \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_sel } @@ -40695,33 +40977,65 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $87 + wire width 64 $85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 + cell $mux $86 parameter \WIDTH 64 connect \A \src_r1 - connect \B \src_or_imm$82 - connect \S \src_sel$79 - connect \Y $87 + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $85 end - process $group_58 + process $group_56 assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_rb $87 + assign \alu_logical0_rb $85 sync init end - process $group_59 + process $group_57 assign \src_r1$next \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$79 } + switch { \src_sel$77 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r1$next \src_or_imm$82 + assign \src_r1$next \src_or_imm$80 end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk update \src_r1 \src_r1$next end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $88 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $87 + end + process $group_58 + assign \alu_logical0_xer_so 1'0 + assign \alu_logical0_xer_so $87 + sync init + end + process $group_59 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 1'0 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end process $group_60 assign \alu_logical0_p_valid_i 1'0 assign \alu_logical0_p_valid_i \alui_l_q_alui @@ -40800,16 +41114,16 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 2 $93 + wire width 3 $93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $94 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o } + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $93 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -40829,47 +41143,47 @@ module \logical0 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_logical0_logical_op__imm_data__imm_ok + connect \A \alu_logical0_logical_op__imm_data__ok connect \Y $97 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 2 $99 + wire width 3 $99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $100 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A $93 - connect \B { $97 $95 } + connect \B { 1'1 $97 $95 } connect \Y $99 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 2 $101 + wire width 3 $101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $102 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i connect \Y $101 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 2 $103 + wire width 3 $103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $104 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 connect \A $99 connect \B $101 connect \Y $103 end process $group_67 - assign \cu_rd__rel_o 2'00 + assign \cu_rd__rel_o 3'000 assign \cu_rd__rel_o $103 sync init end @@ -40901,54 +41215,41 @@ module \logical0 connect \B \cu_shadown_i connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $109 - end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $111 + wire width 2 $109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $112 + cell $and $110 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \req_l_q_req - connect \B { $105 $107 $109 } - connect \Y $111 + connect \B { $105 $107 } + connect \Y $109 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $113 + wire width 2 $111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $114 + cell $and $112 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $111 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $109 connect \B \cu_wrmask_o - connect \Y $113 + connect \Y $111 end process $group_68 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $113 + assign \cu_wr__rel_o 2'00 + assign \cu_wr__rel_o $111 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $115 + wire width 1 $113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $116 + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40956,12 +41257,12 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $115 + connect \Y $113 end process $group_69 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $115 } + switch { $113 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] @@ -40969,9 +41270,9 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $117 + wire width 1 $115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $118 + cell $and $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40979,41 +41280,18 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $117 + connect \Y $115 end process $group_70 assign \dest2_o 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $117 } + switch { $115 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $119 - end - process $group_71 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $119 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] - end - sync init - end connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 end @@ -41230,15 +41508,17 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 6 \fast1 + wire width 64 input 6 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 7 \xer_so + wire width 64 input 7 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 8 \xer_ov + wire width 1 input 8 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 9 \xer_ca + wire width 2 input 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 10 \xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 10 \muxid$1 + wire width 2 output 11 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -41313,7 +41593,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 11 \spr_op__insn_type$2 + wire width 7 output 12 \spr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -41327,31 +41607,35 @@ module \spr_main attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 12 \spr_op__fn_unit$3 + wire width 11 output 13 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \spr_op__insn$4 + wire width 32 output 14 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \spr_op__is_32bit$5 + wire width 1 output 15 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 15 \o + wire width 64 output 16 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 16 \o_ok + wire width 1 output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 17 \fast1$6 + wire width 64 output 18 \spr1$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 18 \fast1_ok + wire width 1 output 19 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \xer_so$7 + wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 20 \xer_so_ok + wire width 1 output 21 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 21 \xer_ov$8 + wire width 1 output 22 \xer_so$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \xer_ov_ok + wire width 1 output 23 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 24 \xer_ov$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 23 \xer_ca$9 + wire width 1 output 25 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \xer_ca_ok + wire width 2 output 26 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 27 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" wire width 10 \spr process $group_0 @@ -41360,7 +41644,7 @@ module \spr_main sync init end process $group_1 - assign \fast1$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" switch \spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" @@ -41368,13 +41652,13 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - assign \fast1$6 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + assign \fast1$7 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end @@ -41389,20 +41673,33 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 assign \fast1_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $11 + end process $group_3 - assign \xer_so$7 1'0 + assign \xer_so$8 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" switch \spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" @@ -41410,18 +41707,36 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_so$7 \ra [31] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + case 1'1 + assign \xer_so$8 \ra [31] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $13 + end process $group_4 assign \xer_so_ok 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" @@ -41431,20 +41746,38 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_so_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + case 1'1 + assign \xer_so_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $15 + end process $group_5 - assign \xer_ov$8 2'00 + assign \xer_ov$9 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" switch \spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" @@ -41452,19 +41785,37 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ov$8 [0] \ra [30] - assign \xer_ov$8 [1] \ra [19] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch { $15 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + case 1'1 + assign \xer_ov$9 [0] \ra [30] + assign \xer_ov$9 [1] \ra [19] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $17 + end process $group_6 assign \xer_ov_ok 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" @@ -41474,20 +41825,38 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ov_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch { $17 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + case 1'1 + assign \xer_ov_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $19 + end process $group_7 - assign \xer_ca$9 2'00 + assign \xer_ca$10 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" switch \spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" @@ -41495,19 +41864,37 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ca$9 [0] \ra [29] - assign \xer_ca$9 [1] \ra [18] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + case 1'1 + assign \xer_ca$10 [0] \ra [29] + assign \xer_ca$10 [1] \ra [18] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $21 + end process $group_8 assign \xer_ca_ok 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" @@ -41517,19 +41904,79 @@ module \spr_main case 7'0110001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ca_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + case 1'1 + assign \xer_ca_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_9 + assign \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case + assign \spr1$6 \ra + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 end sync init end process $group_10 + assign \spr1_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + case + assign \spr1_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + cell $eq $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $23 + end + process $group_12 assign \o_ok 1'0 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" @@ -41537,32 +41984,43 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" attribute \nmigen.decoding "OP_MTSPR/49" case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:72" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:74" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:80" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110, 10'0100001100 assign \o \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" - case 10'0000000001 - assign { \o_ok \o } [31] \xer_so - assign { \o_ok \o } [30] \xer_ov [0] - assign { \o_ok \o } [19] \xer_ov [1] - assign { \o_ok \o } [29] \xer_ca [0] - assign { \o_ok \o } [18] \xer_ca [1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + switch { $23 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + case 1'1 + assign { \o_ok \o } [63:32] 32'00000000000000000000000000000000 + assign { \o_ok \o } [28:20] 9'000000000 + assign { \o_ok \o } [31] \xer_so + assign { \o_ok \o } [30] \xer_ov [0] + assign { \o_ok \o } [19] \xer_ov [1] + assign { \o_ok \o } [29] \xer_ca [0] + assign { \o_ok \o } [18] \xer_ca [1] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:95" + case 10'0100001101 + assign \o [31:0] \fast1 [63:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:99" + case + assign \o \spr1 end end sync init end - process $group_11 + process $group_13 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_12 + process $group_14 assign \spr_op__insn_type$2 7'0000000 assign \spr_op__fn_unit$3 11'00000000000 assign \spr_op__insn$4 32'00000000000000000000000000000000 @@ -41574,9 +42032,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" module \pipe$61 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -41952,6 +42410,8 @@ module \pipe$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 1 \spr_main_xer_so @@ -42059,19 +42519,23 @@ module \pipe$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_fast1$16 + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr_main_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_fast1$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \spr_main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_so$17 + wire width 1 \spr_main_xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \spr_main_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ov$18 + wire width 2 \spr_main_xer_ov$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \spr_main_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ca$19 + wire width 2 \spr_main_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \spr_main_xer_ca_ok cell \spr_main \spr_main @@ -42081,6 +42545,7 @@ module \pipe$61 connect \spr_op__insn \spr_main_spr_op__insn connect \spr_op__is_32bit \spr_main_spr_op__is_32bit connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 connect \fast1 \spr_main_fast1 connect \xer_so \spr_main_xer_so connect \xer_ov \spr_main_xer_ov @@ -42092,13 +42557,15 @@ module \pipe$61 connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 connect \o \spr_main_o connect \o_ok \spr_main_o_ok - connect \fast1$6 \spr_main_fast1$16 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \fast1$7 \spr_main_fast1$17 connect \fast1_ok \spr_main_fast1_ok - connect \xer_so$7 \spr_main_xer_so$17 + connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok - connect \xer_ov$8 \spr_main_xer_ov$18 + connect \xer_ov$9 \spr_main_xer_ov$19 connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_ca$9 \spr_main_xer_ca$19 + connect \xer_ca$10 \spr_main_xer_ca$20 connect \xer_ca_ok \spr_main_xer_ca_ok end process $group_0 @@ -42119,11 +42586,9 @@ module \pipe$61 assign \spr_main_ra \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr1$20 process $group_6 - assign \spr1$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1$20 \spr1 + assign \spr_main_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr_main_spr1 \spr1 sync init end process $group_7 @@ -42302,54 +42767,50 @@ module \pipe$61 wire width 64 \spr1$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \spr1_ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$34 process $group_21 assign \spr1$31 64'0000000000000000000000000000000000000000000000000000000000000000 assign \spr1_ok$32 1'0 - assign { \spr1_ok$32 \spr1$31 } { \spr1_ok$34 \spr1$33 } + assign { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$35 + wire width 64 \fast1$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$36 + wire width 1 \fast1_ok$34 process $group_23 - assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok$36 1'0 - assign { \fast1_ok$36 \fast1$35 } { \spr_main_fast1_ok \spr_main_fast1$16 } + assign \fast1$33 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok$34 1'0 + assign { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$37 + wire width 1 \xer_so$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$38 + wire width 1 \xer_so_ok$36 process $group_25 - assign \xer_so$37 1'0 - assign \xer_so_ok$38 1'0 - assign { \xer_so_ok$38 \xer_so$37 } { \spr_main_xer_so_ok \spr_main_xer_so$17 } + assign \xer_so$35 1'0 + assign \xer_so_ok$36 1'0 + assign { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$39 + wire width 2 \xer_ov$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$40 + wire width 1 \xer_ov_ok$38 process $group_27 - assign \xer_ov$39 2'00 - assign \xer_ov_ok$40 1'0 - assign { \xer_ov_ok$40 \xer_ov$39 } { \spr_main_xer_ov_ok \spr_main_xer_ov$18 } + assign \xer_ov$37 2'00 + assign \xer_ov_ok$38 1'0 + assign { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$41 + wire width 2 \xer_ca$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$42 + wire width 1 \xer_ca_ok$40 process $group_29 - assign \xer_ca$41 2'00 - assign \xer_ca_ok$42 1'0 - assign { \xer_ca_ok$42 \xer_ca$41 } { \spr_main_xer_ca_ok \spr_main_xer_ca$19 } + assign \xer_ca$39 2'00 + assign \xer_ca_ok$40 1'0 + assign { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" @@ -42473,10 +42934,10 @@ module \pipe$61 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } + assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$34 \fast1$33 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } + assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$34 \fast1$33 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -42497,10 +42958,10 @@ module \pipe$61 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } + assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$36 \xer_so$35 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } + assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$36 \xer_so$35 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -42521,10 +42982,10 @@ module \pipe$61 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } + assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } + assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$38 \xer_ov$37 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -42545,10 +43006,10 @@ module \pipe$61 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } + assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } + assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$40 \xer_ca$39 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -42572,13 +43033,11 @@ module \pipe$61 assign \p_ready_o \n_i_rdy_data sync init end - connect \spr1$33 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \spr1_ok$34 1'0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" module \alu_spr0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -42592,7 +43051,7 @@ module \alu_spr0 wire width 1 output 5 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 6 \spr1_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 7 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 8 \n_valid_o @@ -43211,9 +43670,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" module \src_l$64 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 6 input 2 \s_src @@ -43356,9 +43815,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" module \opc_l$65 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -43501,9 +43960,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" module \req_l$66 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 output 2 \q_req @@ -43646,9 +44105,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" module \rst_l$67 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -43791,9 +44250,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" module \rok_l$68 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -43936,9 +44395,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" module \alui_l$69 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -44081,9 +44540,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" module \alu_l$70 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -44226,7 +44685,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" module \spr0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -44371,7 +44830,7 @@ module \spr0 wire width 1 output 28 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 29 \dest2_o - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 30 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_spr0_n_valid_o @@ -46436,17 +46895,17 @@ module \input$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -46569,17 +47028,17 @@ module \input$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__imm$4 + wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__imm_data__imm_ok$5 + wire width 1 output 26 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__rc_ok$7 + wire width 1 output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__oe_ok$9 + wire width 1 output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -46655,12 +47114,7 @@ module \input$75 end process $group_4 assign \xer_so$22 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" - switch { \logical_op__oe__oe_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" - case 1'1 - assign \xer_so$22 \xer_so - end + assign \xer_so$22 \xer_so sync init end process $group_5 @@ -46671,12 +47125,12 @@ module \input$75 process $group_6 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -46687,7 +47141,7 @@ module \input$75 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end end @@ -46786,17 +47240,17 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -46919,17 +47373,17 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__imm$4 + wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__imm_data__imm_ok$5 + wire width 1 output 26 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__rc_ok$7 + wire width 1 output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__oe_ok$9 + wire width 1 output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -47324,12 +47778,12 @@ module \setup_stage process $group_12 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -47340,16 +47794,16 @@ module \setup_stage assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" module \pipe_start - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 2 \n_valid_o @@ -47453,29 +47907,29 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__imm + wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$next + wire width 64 \logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \logical_op__imm_data__imm_ok + wire width 1 output 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$next + wire width 1 \logical_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \logical_op__rc__rc_ok + wire width 1 output 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$next + wire width 1 \logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \logical_op__oe__oe_ok + wire width 1 output 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$next + wire width 1 \logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -47660,17 +48114,17 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 38 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 39 \logical_op__imm_data__imm$4 + wire width 64 input 39 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 40 \logical_op__imm_data__imm_ok$5 + wire width 1 input 40 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 41 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 42 \logical_op__rc__rc_ok$7 + wire width 1 input 42 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 43 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 44 \logical_op__oe__oe_ok$9 + wire width 1 input 44 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 45 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -47801,17 +48255,17 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm + wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok + wire width 1 \input_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok + wire width 1 \input_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok + wire width 1 \input_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -47934,17 +48388,17 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_logical_op__fn_unit$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm$26 + wire width 64 \input_logical_op__imm_data__data$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok$27 + wire width 1 \input_logical_op__imm_data__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__rc__rc$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok$29 + wire width 1 \input_logical_op__rc__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__oe__oe$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok$31 + wire width 1 \input_logical_op__oe__ok$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_logical_op__invert_in$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -47979,12 +48433,12 @@ module \pipe_start connect \muxid \input_muxid connect \logical_op__insn_type \input_logical_op__insn_type connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok + connect \logical_op__rc__ok \input_logical_op__rc__ok connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok + connect \logical_op__oe__ok \input_logical_op__oe__ok connect \logical_op__invert_in \input_logical_op__invert_in connect \logical_op__zero_a \input_logical_op__zero_a connect \logical_op__input_carry \input_logical_op__input_carry @@ -48001,12 +48455,12 @@ module \pipe_start connect \muxid$1 \input_muxid$23 connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 - connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$26 - connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$27 + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 - connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$29 + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 - connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$31 + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 @@ -48113,17 +48567,17 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \setup_stage_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__imm + wire width 64 \setup_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__imm_data__imm_ok + wire width 1 \setup_stage_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \setup_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc_ok + wire width 1 \setup_stage_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \setup_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe_ok + wire width 1 \setup_stage_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \setup_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -48246,17 +48700,17 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \setup_stage_logical_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__imm$48 + wire width 64 \setup_stage_logical_op__imm_data__data$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__imm_data__imm_ok$49 + wire width 1 \setup_stage_logical_op__imm_data__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \setup_stage_logical_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc_ok$51 + wire width 1 \setup_stage_logical_op__rc__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \setup_stage_logical_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe_ok$53 + wire width 1 \setup_stage_logical_op__oe__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \setup_stage_logical_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -48303,12 +48757,12 @@ module \pipe_start connect \muxid \setup_stage_muxid connect \logical_op__insn_type \setup_stage_logical_op__insn_type connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit - connect \logical_op__imm_data__imm \setup_stage_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc - connect \logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc_ok + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe - connect \logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe_ok + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok connect \logical_op__invert_in \setup_stage_logical_op__invert_in connect \logical_op__zero_a \setup_stage_logical_op__zero_a connect \logical_op__input_carry \setup_stage_logical_op__input_carry @@ -48325,12 +48779,12 @@ module \pipe_start connect \muxid$1 \setup_stage_muxid$45 connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 - connect \logical_op__imm_data__imm$4 \setup_stage_logical_op__imm_data__imm$48 - connect \logical_op__imm_data__imm_ok$5 \setup_stage_logical_op__imm_data__imm_ok$49 + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 - connect \logical_op__rc__rc_ok$7 \setup_stage_logical_op__rc__rc_ok$51 + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 - connect \logical_op__oe__oe_ok$9 \setup_stage_logical_op__oe__oe_ok$53 + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 @@ -48359,12 +48813,12 @@ module \pipe_start process $group_1 assign \input_logical_op__insn_type 7'0000000 assign \input_logical_op__fn_unit 11'00000000000 - assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_logical_op__imm_data__imm_ok 1'0 + assign \input_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_logical_op__imm_data__ok 1'0 assign \input_logical_op__rc__rc 1'0 - assign \input_logical_op__rc__rc_ok 1'0 + assign \input_logical_op__rc__ok 1'0 assign \input_logical_op__oe__oe 1'0 - assign \input_logical_op__oe__oe_ok 1'0 + assign \input_logical_op__oe__ok 1'0 assign \input_logical_op__invert_in 1'0 assign \input_logical_op__zero_a 1'0 assign \input_logical_op__input_carry 2'00 @@ -48375,7 +48829,7 @@ module \pipe_start assign \input_logical_op__is_signed 1'0 assign \input_logical_op__data_len 4'0000 assign \input_logical_op__insn 32'00000000000000000000000000000000 - assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } + assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__ok \input_logical_op__oe__oe } { \input_logical_op__rc__ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__ok \input_logical_op__imm_data__data } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } sync init end process $group_19 @@ -48401,12 +48855,12 @@ module \pipe_start process $group_23 assign \setup_stage_logical_op__insn_type 7'0000000 assign \setup_stage_logical_op__fn_unit 11'00000000000 - assign \setup_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_logical_op__imm_data__imm_ok 1'0 + assign \setup_stage_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_logical_op__imm_data__ok 1'0 assign \setup_stage_logical_op__rc__rc 1'0 - assign \setup_stage_logical_op__rc__rc_ok 1'0 + assign \setup_stage_logical_op__rc__ok 1'0 assign \setup_stage_logical_op__oe__oe 1'0 - assign \setup_stage_logical_op__oe__oe_ok 1'0 + assign \setup_stage_logical_op__oe__ok 1'0 assign \setup_stage_logical_op__invert_in 1'0 assign \setup_stage_logical_op__zero_a 1'0 assign \setup_stage_logical_op__input_carry 2'00 @@ -48417,7 +48871,7 @@ module \pipe_start assign \setup_stage_logical_op__is_signed 1'0 assign \setup_stage_logical_op__data_len 4'0000 assign \setup_stage_logical_op__insn 32'00000000000000000000000000000000 - assign { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in { \setup_stage_logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe } { \setup_stage_logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc } { \setup_stage_logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm } \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 { \input_logical_op__oe__oe_ok$31 \input_logical_op__oe__oe$30 } { \input_logical_op__rc__rc_ok$29 \input_logical_op__rc__rc$28 } { \input_logical_op__imm_data__imm_ok$27 \input_logical_op__imm_data__imm$26 } \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + assign { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in { \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe } { \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc } { \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data } \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 { \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 } { \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 } { \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 } \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } sync init end process $group_41 @@ -48566,17 +49020,17 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$71 + wire width 64 \logical_op__imm_data__data$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$72 + wire width 1 \logical_op__imm_data__ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$74 + wire width 1 \logical_op__rc__ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$76 + wire width 1 \logical_op__oe__ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__invert_in$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -48604,12 +49058,12 @@ module \pipe_start process $group_48 assign \logical_op__insn_type$69 7'0000000 assign \logical_op__fn_unit$70 11'00000000000 - assign \logical_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$72 1'0 + assign \logical_op__imm_data__data$71 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$72 1'0 assign \logical_op__rc__rc$73 1'0 - assign \logical_op__rc__rc_ok$74 1'0 + assign \logical_op__rc__ok$74 1'0 assign \logical_op__oe__oe$75 1'0 - assign \logical_op__oe__oe_ok$76 1'0 + assign \logical_op__oe__ok$76 1'0 assign \logical_op__invert_in$77 1'0 assign \logical_op__zero_a$78 1'0 assign \logical_op__input_carry$79 2'00 @@ -48620,7 +49074,7 @@ module \pipe_start assign \logical_op__is_signed$84 1'0 assign \logical_op__data_len$85 4'0000 assign \logical_op__insn$86 32'00000000000000000000000000000000 - assign { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 { \setup_stage_logical_op__oe__oe_ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__rc_ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__imm_ok$49 \setup_stage_logical_op__imm_data__imm$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + assign { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 { \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -48748,12 +49202,12 @@ module \pipe_start process $group_79 assign \logical_op__insn_type$next \logical_op__insn_type assign \logical_op__fn_unit$next \logical_op__fn_unit - assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm - assign \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm_ok + assign \logical_op__imm_data__data$next \logical_op__imm_data__data + assign \logical_op__imm_data__ok$next \logical_op__imm_data__ok assign \logical_op__rc__rc$next \logical_op__rc__rc - assign \logical_op__rc__rc_ok$next \logical_op__rc__rc_ok + assign \logical_op__rc__ok$next \logical_op__rc__ok assign \logical_op__oe__oe$next \logical_op__oe__oe - assign \logical_op__oe__oe_ok$next \logical_op__oe__oe_ok + assign \logical_op__oe__ok$next \logical_op__oe__ok assign \logical_op__invert_in$next \logical_op__invert_in assign \logical_op__zero_a$next \logical_op__zero_a assign \logical_op__input_carry$next \logical_op__input_carry @@ -48768,30 +49222,30 @@ module \pipe_start switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$next 1'0 + assign \logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$next 1'0 assign \logical_op__rc__rc$next 1'0 - assign \logical_op__rc__rc_ok$next 1'0 + assign \logical_op__rc__ok$next 1'0 assign \logical_op__oe__oe$next 1'0 - assign \logical_op__oe__oe_ok$next 1'0 + assign \logical_op__oe__ok$next 1'0 end sync init update \logical_op__insn_type 7'0000000 update \logical_op__fn_unit 11'00000000000 - update \logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok 1'0 + update \logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__ok 1'0 update \logical_op__rc__rc 1'0 - update \logical_op__rc__rc_ok 1'0 + update \logical_op__rc__ok 1'0 update \logical_op__oe__oe 1'0 - update \logical_op__oe__oe_ok 1'0 + update \logical_op__oe__ok 1'0 update \logical_op__invert_in 1'0 update \logical_op__zero_a 1'0 update \logical_op__input_carry 2'00 @@ -48805,12 +49259,12 @@ module \pipe_start sync posedge \coresync_clk update \logical_op__insn_type \logical_op__insn_type$next update \logical_op__fn_unit \logical_op__fn_unit$next - update \logical_op__imm_data__imm \logical_op__imm_data__imm$next - update \logical_op__imm_data__imm_ok \logical_op__imm_data__imm_ok$next + update \logical_op__imm_data__data \logical_op__imm_data__data$next + update \logical_op__imm_data__ok \logical_op__imm_data__ok$next update \logical_op__rc__rc \logical_op__rc__rc$next - update \logical_op__rc__rc_ok \logical_op__rc__rc_ok$next + update \logical_op__rc__ok \logical_op__rc__ok$next update \logical_op__oe__oe \logical_op__oe__oe$next - update \logical_op__oe__oe_ok \logical_op__oe__oe_ok$next + update \logical_op__oe__ok \logical_op__oe__ok$next update \logical_op__invert_in \logical_op__invert_in$next update \logical_op__zero_a \logical_op__zero_a$next update \logical_op__input_carry \logical_op__input_carry$next @@ -49243,9 +49697,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" module \pipe_middle_0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -49343,17 +49797,17 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -49496,17 +49950,17 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 38 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 39 \logical_op__imm_data__imm$4 + wire width 64 output 39 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__imm_data__imm_ok$5 + wire width 1 output 40 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 41 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__rc__rc_ok$7 + wire width 1 output 42 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 43 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__oe__oe_ok$9 + wire width 1 output 44 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 45 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -49695,29 +50149,29 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$30$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$31 + wire width 64 \logical_op__imm_data__data$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$31$next + wire width 64 \logical_op__imm_data__data$31$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$32 + wire width 1 \logical_op__imm_data__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$32$next + wire width 1 \logical_op__imm_data__ok$32$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$33$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$34 + wire width 1 \logical_op__rc__ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$34$next + wire width 1 \logical_op__rc__ok$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$35$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$36 + wire width 1 \logical_op__oe__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$36$next + wire width 1 \logical_op__oe__ok$36$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__invert_in$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -49765,12 +50219,12 @@ module \pipe_middle_0 process $group_2 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -49781,7 +50235,7 @@ module \pipe_middle_0 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 { \logical_op__oe__oe_ok$36 \logical_op__oe__oe$35 } { \logical_op__rc__rc_ok$34 \logical_op__rc__rc$33 } { \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm$31 } \logical_op__fn_unit$30 \logical_op__insn_type$29 } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 { \logical_op__oe__ok$36 \logical_op__oe__oe$35 } { \logical_op__rc__ok$34 \logical_op__rc__rc$33 } { \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 } \logical_op__fn_unit$30 \logical_op__insn_type$29 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -49861,14 +50315,27 @@ module \pipe_middle_0 assign \quotient_root \div_state_next_o_dividend_quotient [63:0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" wire width 192 $55 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" + wire width 191 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" + cell $sshl $57 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \Y_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $56 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" + cell $pos $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A $56 connect \Y $55 end process $group_29 @@ -49876,24 +50343,24 @@ module \pipe_middle_0 assign \remainder $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" + wire width 1 $59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" wire width 1 \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" wire width 1 \empty$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - cell $not $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" + cell $not $60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $57 + connect \Y $59 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $59 + wire width 1 $61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $60 + cell $eq $62 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -49901,24 +50368,24 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \div_state_next_o_q_bits_known connect \B 7'1000000 - connect \Y $59 + connect \Y $61 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - cell $and $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" + cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $57 - connect \B $59 - connect \Y $61 + connect \A $59 + connect \B $61 + connect \Y $63 end process $group_30 assign \n_valid_o 1'0 - assign \n_valid_o $61 + assign \n_valid_o $63 sync init end process $group_31 @@ -49962,12 +50429,12 @@ module \pipe_middle_0 end process $group_34 assign \div_state_next_i_q_bits_known 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 assign \div_state_next_i_q_bits_known \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case assign \div_state_next_i_q_bits_known \saved_state_q_bits_known end @@ -49975,38 +50442,38 @@ module \pipe_middle_0 end process $group_35 assign \div_state_next_i_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 assign \div_state_next_i_dividend_quotient \div_state_init_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case assign \div_state_next_i_dividend_quotient \saved_state_dividend_quotient end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$63 + wire width 64 \divisor_radicand$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$63$next + wire width 64 \divisor_radicand$65$next process $group_36 assign \div_state_next_divisor 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 assign \div_state_next_divisor \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case - assign \div_state_next_divisor \divisor_radicand$63 + assign \div_state_next_divisor \divisor_radicand$65 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - cell $and $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" + wire width 1 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" + cell $and $67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50014,25 +50481,25 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $64 + connect \Y $66 end process $group_37 assign \empty$next \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \empty$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - switch { $64 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" + switch { $66 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" case 1'1 assign \empty$next 1'1 end @@ -50049,17 +50516,17 @@ module \pipe_middle_0 end process $group_38 assign \muxid$28$next \muxid$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \muxid$28$next \muxid end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50070,12 +50537,12 @@ module \pipe_middle_0 process $group_39 assign \logical_op__insn_type$29$next \logical_op__insn_type$29 assign \logical_op__fn_unit$30$next \logical_op__fn_unit$30 - assign \logical_op__imm_data__imm$31$next \logical_op__imm_data__imm$31 - assign \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm_ok$32 + assign \logical_op__imm_data__data$31$next \logical_op__imm_data__data$31 + assign \logical_op__imm_data__ok$32$next \logical_op__imm_data__ok$32 assign \logical_op__rc__rc$33$next \logical_op__rc__rc$33 - assign \logical_op__rc__rc_ok$34$next \logical_op__rc__rc_ok$34 + assign \logical_op__rc__ok$34$next \logical_op__rc__ok$34 assign \logical_op__oe__oe$35$next \logical_op__oe__oe$35 - assign \logical_op__oe__oe_ok$36$next \logical_op__oe__oe_ok$36 + assign \logical_op__oe__ok$36$next \logical_op__oe__ok$36 assign \logical_op__invert_in$37$next \logical_op__invert_in$37 assign \logical_op__zero_a$38$next \logical_op__zero_a$38 assign \logical_op__input_carry$39$next \logical_op__input_carry$39 @@ -50086,38 +50553,38 @@ module \pipe_middle_0 assign \logical_op__is_signed$44$next \logical_op__is_signed$44 assign \logical_op__data_len$45$next \logical_op__data_len$45 assign \logical_op__insn$46$next \logical_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 - assign { \logical_op__insn$46$next \logical_op__data_len$45$next \logical_op__is_signed$44$next \logical_op__is_32bit$43$next \logical_op__output_carry$42$next \logical_op__write_cr0$41$next \logical_op__invert_out$40$next \logical_op__input_carry$39$next \logical_op__zero_a$38$next \logical_op__invert_in$37$next { \logical_op__oe__oe_ok$36$next \logical_op__oe__oe$35$next } { \logical_op__rc__rc_ok$34$next \logical_op__rc__rc$33$next } { \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm$31$next } \logical_op__fn_unit$30$next \logical_op__insn_type$29$next } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$46$next \logical_op__data_len$45$next \logical_op__is_signed$44$next \logical_op__is_32bit$43$next \logical_op__output_carry$42$next \logical_op__write_cr0$41$next \logical_op__invert_out$40$next \logical_op__input_carry$39$next \logical_op__zero_a$38$next \logical_op__invert_in$37$next { \logical_op__oe__ok$36$next \logical_op__oe__oe$35$next } { \logical_op__rc__ok$34$next \logical_op__rc__rc$33$next } { \logical_op__imm_data__ok$32$next \logical_op__imm_data__data$31$next } \logical_op__fn_unit$30$next \logical_op__insn_type$29$next } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \logical_op__imm_data__imm$31$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$32$next 1'0 + assign \logical_op__imm_data__data$31$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$32$next 1'0 assign \logical_op__rc__rc$33$next 1'0 - assign \logical_op__rc__rc_ok$34$next 1'0 + assign \logical_op__rc__ok$34$next 1'0 assign \logical_op__oe__oe$35$next 1'0 - assign \logical_op__oe__oe_ok$36$next 1'0 + assign \logical_op__oe__ok$36$next 1'0 end sync init update \logical_op__insn_type$29 7'0000000 update \logical_op__fn_unit$30 11'00000000000 - update \logical_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$32 1'0 + update \logical_op__imm_data__data$31 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__ok$32 1'0 update \logical_op__rc__rc$33 1'0 - update \logical_op__rc__rc_ok$34 1'0 + update \logical_op__rc__ok$34 1'0 update \logical_op__oe__oe$35 1'0 - update \logical_op__oe__oe_ok$36 1'0 + update \logical_op__oe__ok$36 1'0 update \logical_op__invert_in$37 1'0 update \logical_op__zero_a$38 1'0 update \logical_op__input_carry$39 2'00 @@ -50131,12 +50598,12 @@ module \pipe_middle_0 sync posedge \coresync_clk update \logical_op__insn_type$29 \logical_op__insn_type$29$next update \logical_op__fn_unit$30 \logical_op__fn_unit$30$next - update \logical_op__imm_data__imm$31 \logical_op__imm_data__imm$31$next - update \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm_ok$32$next + update \logical_op__imm_data__data$31 \logical_op__imm_data__data$31$next + update \logical_op__imm_data__ok$32 \logical_op__imm_data__ok$32$next update \logical_op__rc__rc$33 \logical_op__rc__rc$33$next - update \logical_op__rc__rc_ok$34 \logical_op__rc__rc_ok$34$next + update \logical_op__rc__ok$34 \logical_op__rc__ok$34$next update \logical_op__oe__oe$35 \logical_op__oe__oe$35$next - update \logical_op__oe__oe_ok$36 \logical_op__oe__oe_ok$36$next + update \logical_op__oe__ok$36 \logical_op__oe__ok$36$next update \logical_op__invert_in$37 \logical_op__invert_in$37$next update \logical_op__zero_a$38 \logical_op__zero_a$38$next update \logical_op__input_carry$39 \logical_op__input_carry$39$next @@ -50150,17 +50617,17 @@ module \pipe_middle_0 end process $group_57 assign \ra$47$next \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \ra$47$next \ra end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50170,17 +50637,17 @@ module \pipe_middle_0 end process $group_58 assign \rb$48$next \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \rb$48$next \rb end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50190,17 +50657,17 @@ module \pipe_middle_0 end process $group_59 assign \xer_so$49$next \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \xer_so$49$next \xer_so end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50210,17 +50677,17 @@ module \pipe_middle_0 end process $group_60 assign \divisor_neg$50$next \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \divisor_neg$50$next \divisor_neg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50230,17 +50697,17 @@ module \pipe_middle_0 end process $group_61 assign \dividend_neg$51$next \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \dividend_neg$51$next \dividend_neg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50250,17 +50717,17 @@ module \pipe_middle_0 end process $group_62 assign \dive_abs_ov32$52$next \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \dive_abs_ov32$52$next \dive_abs_ov32 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50270,17 +50737,17 @@ module \pipe_middle_0 end process $group_63 assign \dive_abs_ov64$53$next \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \dive_abs_ov64$53$next \dive_abs_ov64 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50290,17 +50757,17 @@ module \pipe_middle_0 end process $group_64 assign \div_by_zero$54$next \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 assign \div_by_zero$54$next \div_by_zero end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init @@ -50309,72 +50776,72 @@ module \pipe_middle_0 update \div_by_zero$54 \div_by_zero$54$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$66 + wire width 128 \dividend$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$66$next + wire width 128 \dividend$68$next process $group_65 - assign \dividend$66$next \dividend$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + assign \dividend$68$next \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 - assign \dividend$66$next \dividend + assign \dividend$68$next \dividend end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init - update \dividend$66 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + update \dividend$68 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \dividend$66 \dividend$66$next + update \dividend$68 \dividend$68$next end process $group_66 - assign \divisor_radicand$63$next \divisor_radicand$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + assign \divisor_radicand$65$next \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 - assign \divisor_radicand$63$next \divisor_radicand + assign \divisor_radicand$65$next \divisor_radicand end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init - update \divisor_radicand$63 64'0000000000000000000000000000000000000000000000000000000000000000 + update \divisor_radicand$65 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \divisor_radicand$63 \divisor_radicand$63$next + update \divisor_radicand$65 \divisor_radicand$65$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$67 + wire width 2 \operation$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$67$next + wire width 2 \operation$69$next process $group_67 - assign \operation$67$next \operation$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + assign \operation$69$next \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" case 1'1 - assign \operation$67$next \operation + assign \operation$69$next \operation end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" case end sync init - update \operation$67 2'00 + update \operation$69 2'00 sync posedge \coresync_clk - update \operation$67 \operation$67$next + update \operation$69 \operation$69$next end end attribute \generator "nMigen" @@ -50528,17 +50995,17 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -50671,17 +51138,17 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 29 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \logical_op__imm_data__imm$4 + wire width 64 output 30 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__imm_data__imm_ok$5 + wire width 1 output 31 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 32 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__rc__rc_ok$7 + wire width 1 output 33 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 34 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__oe__oe_ok$9 + wire width 1 output 35 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 36 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -51076,12 +51543,12 @@ module \output_stage process $group_11 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -51092,7 +51559,7 @@ module \output_stage assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end end @@ -51191,17 +51658,17 @@ module \output$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -51328,17 +51795,17 @@ module \output$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 26 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 27 \logical_op__imm_data__imm$4 + wire width 64 output 27 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__imm_data__imm_ok$5 + wire width 1 output 28 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 29 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__rc__rc_ok$7 + wire width 1 output 30 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 31 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__oe__oe_ok$9 + wire width 1 output 32 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 33 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -51379,64 +51846,99 @@ module \output$80 wire width 1 output 49 \xer_so$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $25 + end + process $group_0 + assign \oe 1'0 + assign \oe $25 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire width 1 \so + process $group_1 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + case 1'1 + assign \so \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" + case + assign \so \xer_so + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $30 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $27 + connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $31 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 - connect \A $27 - connect \Y $26 + connect \A $29 + connect \Y $28 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $30 + wire width 65 $32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $31 + cell $pos $33 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $30 + connect \Y $32 end - process $group_0 - assign \o$25 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + process $group_2 + assign \o$27 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" switch { \logical_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" case 1'1 - assign \o$25 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + assign \o$27 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" case - assign \o$25 $30 + assign \o$27 $32 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - process $group_1 + process $group_3 assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$25 [63:0] + assign \target \o$27 [63:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $35 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -51444,19 +51946,19 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $32 + connect \Y $34 end - process $group_2 + process $group_4 assign \is_cmp 1'0 - assign \is_cmp $32 + assign \is_cmp $34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $37 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -51464,118 +51966,92 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $34 + connect \Y $36 end - process $group_3 + process $group_5 assign \is_cmpeqb 1'0 - assign \is_cmpeqb $34 + assign \is_cmpeqb $36 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire width 1 \msb_test - process $group_4 + process $group_6 assign \msb_test 1'0 assign \msb_test \target [63] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_bool $39 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $36 + connect \Y $38 end - process $group_5 + process $group_7 assign \is_nzero 1'0 - assign \is_nzero $36 + assign \is_nzero $38 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire width 1 \is_negative + process $group_8 + assign \is_negative 1'0 + assign \is_negative \msb_test sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $38 + connect \Y $40 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \B $38 - connect \Y $40 + connect \B $40 + connect \Y $42 end - process $group_6 + process $group_9 assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $40 - end + assign \is_positive $42 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $42 + connect \A \is_cmpeqb + connect \B \is_cmp connect \Y $44 end - process $group_7 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -51583,53 +52059,53 @@ module \output$80 connect \A \is_nzero connect \Y $46 end - process $group_8 + process $group_10 assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch { $44 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" case 1'1 assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" case - assign \cr0 { \is_negative \is_positive $46 \xer_so$24 } + assign \cr0 { \is_negative \is_positive $46 \so } end sync init end - process $group_9 + process $group_11 assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$25 [63:0] + assign \o$20 \o$27 [63:0] sync init end - process $group_10 + process $group_12 assign \o_ok$21 1'0 assign \o_ok$21 \o_ok sync init end - process $group_11 + process $group_13 assign \cr_a$22 4'0000 assign \cr_a$22 \cr0 sync init end - process $group_12 + process $group_14 assign \cr_a_ok 1'0 assign \cr_a_ok \logical_op__write_cr0 sync init end - process $group_13 + process $group_15 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_14 + process $group_16 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5 1'0 assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__rc__ok$7 1'0 assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__oe__ok$9 1'0 assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 @@ -51640,35 +52116,33 @@ module \output$80 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $49 + wire width 1 \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe - connect \B \logical_op__oe__oe_ok - connect \Y $48 + connect \B \logical_op__oe__ok + connect \Y $49 end - process $group_32 - assign \oe 1'0 - assign \oe $48 + process $group_34 + assign \oe$48 1'0 + assign \oe$48 $49 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51676,53 +52150,43 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $50 - end - process $group_33 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $50 - end - sync init + connect \Y $51 end - process $group_34 + process $group_35 assign \xer_so$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$48 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 - assign \xer_so$24 \so + assign \xer_so$24 $51 end sync init end - process $group_35 + process $group_36 assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$48 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_so_ok 1'1 end sync init end - process $group_36 + process $group_37 assign \xer_ov$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$48 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_ov$23 \xer_ov end sync init end - process $group_37 + process $group_38 assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$48 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_ov_ok 1'1 end @@ -51732,9 +52196,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" module \pipe_end - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -51832,17 +52296,17 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -51989,29 +52453,29 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \logical_op__imm_data__imm$4 + wire width 64 output 38 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next + wire width 64 \logical_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__imm_data__imm_ok$5 + wire width 1 output 39 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next + wire width 1 \logical_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 40 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__rc__rc_ok$7 + wire width 1 output 41 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next + wire width 1 \logical_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 42 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__oe__oe_ok$9 + wire width 1 output 43 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next + wire width 1 \logical_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 44 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -52188,17 +52652,17 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_stage_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__imm + wire width 64 \output_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__imm_data__imm_ok + wire width 1 \output_stage_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc_ok + wire width 1 \output_stage_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe_ok + wire width 1 \output_stage_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -52331,17 +52795,17 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_stage_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__imm$24 + wire width 64 \output_stage_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__imm_data__imm_ok$25 + wire width 1 \output_stage_logical_op__imm_data__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_stage_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc_ok$27 + wire width 1 \output_stage_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_stage_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe_ok$29 + wire width 1 \output_stage_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_stage_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -52380,12 +52844,12 @@ module \pipe_end connect \muxid \output_stage_muxid connect \logical_op__insn_type \output_stage_logical_op__insn_type connect \logical_op__fn_unit \output_stage_logical_op__fn_unit - connect \logical_op__imm_data__imm \output_stage_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok connect \logical_op__rc__rc \output_stage_logical_op__rc__rc - connect \logical_op__rc__rc_ok \output_stage_logical_op__rc__rc_ok + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok connect \logical_op__oe__oe \output_stage_logical_op__oe__oe - connect \logical_op__oe__oe_ok \output_stage_logical_op__oe__oe_ok + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok connect \logical_op__invert_in \output_stage_logical_op__invert_in connect \logical_op__zero_a \output_stage_logical_op__zero_a connect \logical_op__input_carry \output_stage_logical_op__input_carry @@ -52407,12 +52871,12 @@ module \pipe_end connect \muxid$1 \output_stage_muxid$21 connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__imm$4 \output_stage_logical_op__imm_data__imm$24 - connect \logical_op__imm_data__imm_ok$5 \output_stage_logical_op__imm_data__imm_ok$25 + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 - connect \logical_op__rc__rc_ok$7 \output_stage_logical_op__rc__rc_ok$27 + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 - connect \logical_op__oe__oe_ok$9 \output_stage_logical_op__oe__oe_ok$29 + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 @@ -52521,17 +52985,17 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm + wire width 64 \output_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok + wire width 1 \output_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok + wire width 1 \output_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok + wire width 1 \output_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -52658,17 +53122,17 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_logical_op__fn_unit$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm$44 + wire width 64 \output_logical_op__imm_data__data$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok$45 + wire width 1 \output_logical_op__imm_data__ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__rc__rc$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok$47 + wire width 1 \output_logical_op__rc__ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__oe__oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok$49 + wire width 1 \output_logical_op__oe__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_logical_op__invert_in$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -52713,12 +53177,12 @@ module \pipe_end connect \muxid \output_muxid connect \logical_op__insn_type \output_logical_op__insn_type connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok + connect \logical_op__rc__ok \output_logical_op__rc__ok connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok + connect \logical_op__oe__ok \output_logical_op__oe__ok connect \logical_op__invert_in \output_logical_op__invert_in connect \logical_op__zero_a \output_logical_op__zero_a connect \logical_op__input_carry \output_logical_op__input_carry @@ -52737,12 +53201,12 @@ module \pipe_end connect \muxid$1 \output_muxid$41 connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 - connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$44 - connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$45 + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 - connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$47 + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 - connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$49 + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 @@ -52770,12 +53234,12 @@ module \pipe_end process $group_1 assign \output_stage_logical_op__insn_type 7'0000000 assign \output_stage_logical_op__fn_unit 11'00000000000 - assign \output_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_stage_logical_op__imm_data__imm_ok 1'0 + assign \output_stage_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_logical_op__imm_data__ok 1'0 assign \output_stage_logical_op__rc__rc 1'0 - assign \output_stage_logical_op__rc__rc_ok 1'0 + assign \output_stage_logical_op__rc__ok 1'0 assign \output_stage_logical_op__oe__oe 1'0 - assign \output_stage_logical_op__oe__oe_ok 1'0 + assign \output_stage_logical_op__oe__ok 1'0 assign \output_stage_logical_op__invert_in 1'0 assign \output_stage_logical_op__zero_a 1'0 assign \output_stage_logical_op__input_carry 2'00 @@ -52786,7 +53250,7 @@ module \pipe_end assign \output_stage_logical_op__is_signed 1'0 assign \output_stage_logical_op__data_len 4'0000 assign \output_stage_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in { \output_stage_logical_op__oe__oe_ok \output_stage_logical_op__oe__oe } { \output_stage_logical_op__rc__rc_ok \output_stage_logical_op__rc__rc } { \output_stage_logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm } \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in { \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe } { \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc } { \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data } \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -52851,12 +53315,12 @@ module \pipe_end process $group_30 assign \output_logical_op__insn_type 7'0000000 assign \output_logical_op__fn_unit 11'00000000000 - assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_logical_op__imm_data__imm_ok 1'0 + assign \output_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_logical_op__imm_data__ok 1'0 assign \output_logical_op__rc__rc 1'0 - assign \output_logical_op__rc__rc_ok 1'0 + assign \output_logical_op__rc__ok 1'0 assign \output_logical_op__oe__oe 1'0 - assign \output_logical_op__oe__oe_ok 1'0 + assign \output_logical_op__oe__ok 1'0 assign \output_logical_op__invert_in 1'0 assign \output_logical_op__zero_a 1'0 assign \output_logical_op__input_carry 2'00 @@ -52867,7 +53331,7 @@ module \pipe_end assign \output_logical_op__is_signed 1'0 assign \output_logical_op__data_len 4'0000 assign \output_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 { \output_stage_logical_op__oe__oe_ok$29 \output_stage_logical_op__oe__oe$28 } { \output_stage_logical_op__rc__rc_ok$27 \output_stage_logical_op__rc__rc$26 } { \output_stage_logical_op__imm_data__imm_ok$25 \output_stage_logical_op__imm_data__imm$24 } \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__ok \output_logical_op__oe__oe } { \output_logical_op__rc__ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__ok \output_logical_op__imm_data__data } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 { \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 } { \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 } { \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 } \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } sync init end process $group_48 @@ -53037,17 +53501,17 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$79 + wire width 64 \logical_op__imm_data__data$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$80 + wire width 1 \logical_op__imm_data__ok$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$82 + wire width 1 \logical_op__rc__ok$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$84 + wire width 1 \logical_op__oe__ok$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__invert_in$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -53075,12 +53539,12 @@ module \pipe_end process $group_60 assign \logical_op__insn_type$77 7'0000000 assign \logical_op__fn_unit$78 11'00000000000 - assign \logical_op__imm_data__imm$79 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$80 1'0 + assign \logical_op__imm_data__data$79 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$80 1'0 assign \logical_op__rc__rc$81 1'0 - assign \logical_op__rc__rc_ok$82 1'0 + assign \logical_op__rc__ok$82 1'0 assign \logical_op__oe__oe$83 1'0 - assign \logical_op__oe__oe_ok$84 1'0 + assign \logical_op__oe__ok$84 1'0 assign \logical_op__invert_in$85 1'0 assign \logical_op__zero_a$86 1'0 assign \logical_op__input_carry$87 2'00 @@ -53091,7 +53555,7 @@ module \pipe_end assign \logical_op__is_signed$92 1'0 assign \logical_op__data_len$93 4'0000 assign \logical_op__insn$94 32'00000000000000000000000000000000 - assign { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 { \output_logical_op__oe__oe_ok$49 \output_logical_op__oe__oe$48 } { \output_logical_op__rc__rc_ok$47 \output_logical_op__rc__rc$46 } { \output_logical_op__imm_data__imm_ok$45 \output_logical_op__imm_data__imm$44 } \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + assign { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 { \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 } { \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 } { \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 } \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -53178,12 +53642,12 @@ module \pipe_end process $group_88 assign \logical_op__insn_type$2$next \logical_op__insn_type$2 assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__imm_data__data$4$next \logical_op__imm_data__data$4 + assign \logical_op__imm_data__ok$5$next \logical_op__imm_data__ok$5 assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__rc__ok$7$next \logical_op__rc__ok$7 assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__oe__ok$9$next \logical_op__oe__ok$9 assign \logical_op__invert_in$10$next \logical_op__invert_in$10 assign \logical_op__zero_a$11$next \logical_op__zero_a$11 assign \logical_op__input_carry$12$next \logical_op__input_carry$12 @@ -53198,30 +53662,30 @@ module \pipe_end switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$5$next 1'0 assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__rc__ok$7$next 1'0 assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 + assign \logical_op__oe__ok$9$next 1'0 end sync init update \logical_op__insn_type$2 7'0000000 update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__ok$5 1'0 update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__rc__ok$7 1'0 update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__oe__ok$9 1'0 update \logical_op__invert_in$10 1'0 update \logical_op__zero_a$11 1'0 update \logical_op__input_carry$12 2'00 @@ -53235,12 +53699,12 @@ module \pipe_end sync posedge \coresync_clk update \logical_op__insn_type$2 \logical_op__insn_type$2$next update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__imm_data__data$4 \logical_op__imm_data__data$4$next + update \logical_op__imm_data__ok$5 \logical_op__imm_data__ok$5$next update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__rc__ok$7 \logical_op__rc__ok$7$next update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__oe__ok$9 \logical_op__oe__ok$9$next update \logical_op__invert_in$10 \logical_op__invert_in$10$next update \logical_op__zero_a$11 \logical_op__zero_a$11$next update \logical_op__input_carry$12 \logical_op__input_carry$12$next @@ -53365,7 +53829,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" module \alu_div0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -53375,7 +53839,7 @@ module \alu_div0 wire width 1 output 3 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 4 \xer_so_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 5 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 6 \n_valid_o @@ -53471,17 +53935,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 9 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \logical_op__imm_data__imm + wire width 64 input 10 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__imm_data__imm_ok + wire width 1 input 11 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 12 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__rc__rc_ok + wire width 1 input 13 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 14 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__oe__oe_ok + wire width 1 input 15 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 16 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -53628,17 +54092,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe_start_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__imm + wire width 64 \pipe_start_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__imm_data__imm_ok + wire width 1 \pipe_start_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_start_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc_ok + wire width 1 \pipe_start_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_start_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe_ok + wire width 1 \pipe_start_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_start_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -53781,17 +54245,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe_start_logical_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__imm$5 + wire width 64 \pipe_start_logical_op__imm_data__data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__imm_data__imm_ok$6 + wire width 1 \pipe_start_logical_op__imm_data__ok$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_start_logical_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc_ok$8 + wire width 1 \pipe_start_logical_op__rc__ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_start_logical_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe_ok$10 + wire width 1 \pipe_start_logical_op__oe__ok$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_start_logical_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -53830,12 +54294,12 @@ module \alu_div0 connect \muxid \pipe_start_muxid connect \logical_op__insn_type \pipe_start_logical_op__insn_type connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_start_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data + connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc_ok + connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe_ok + connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok connect \logical_op__invert_in \pipe_start_logical_op__invert_in connect \logical_op__zero_a \pipe_start_logical_op__zero_a connect \logical_op__input_carry \pipe_start_logical_op__input_carry @@ -53862,12 +54326,12 @@ module \alu_div0 connect \muxid$1 \pipe_start_muxid$2 connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 - connect \logical_op__imm_data__imm$4 \pipe_start_logical_op__imm_data__imm$5 - connect \logical_op__imm_data__imm_ok$5 \pipe_start_logical_op__imm_data__imm_ok$6 + connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 + connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 - connect \logical_op__rc__rc_ok$7 \pipe_start_logical_op__rc__rc_ok$8 + connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 - connect \logical_op__oe__oe_ok$9 \pipe_start_logical_op__oe__oe_ok$10 + connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 @@ -53978,17 +54442,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe_middle_0_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__imm + wire width 64 \pipe_middle_0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok + wire width 1 \pipe_middle_0_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_middle_0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc_ok + wire width 1 \pipe_middle_0_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_middle_0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe_ok + wire width 1 \pipe_middle_0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_middle_0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -54131,17 +54595,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe_middle_0_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__imm$27 + wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok$28 + wire width 1 \pipe_middle_0_logical_op__imm_data__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_middle_0_logical_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc_ok$30 + wire width 1 \pipe_middle_0_logical_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_middle_0_logical_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe_ok$32 + wire width 1 \pipe_middle_0_logical_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_middle_0_logical_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -54194,12 +54658,12 @@ module \alu_div0 connect \muxid \pipe_middle_0_muxid connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc_ok + connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe_ok + connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry @@ -54226,12 +54690,12 @@ module \alu_div0 connect \muxid$1 \pipe_middle_0_muxid$24 connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 - connect \logical_op__imm_data__imm$4 \pipe_middle_0_logical_op__imm_data__imm$27 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_0_logical_op__imm_data__imm_ok$28 + connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 - connect \logical_op__rc__rc_ok$7 \pipe_middle_0_logical_op__rc__rc_ok$30 + connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 - connect \logical_op__oe__oe_ok$9 \pipe_middle_0_logical_op__oe__oe_ok$32 + connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 @@ -54349,17 +54813,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe_end_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__imm + wire width 64 \pipe_end_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__imm_ok + wire width 1 \pipe_end_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_end_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc_ok + wire width 1 \pipe_end_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_end_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe_ok + wire width 1 \pipe_end_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_end_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -54500,17 +54964,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe_end_logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__imm$54 + wire width 64 \pipe_end_logical_op__imm_data__data$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__imm_ok$55 + wire width 1 \pipe_end_logical_op__imm_data__ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_end_logical_op__rc__rc$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc_ok$57 + wire width 1 \pipe_end_logical_op__rc__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_end_logical_op__oe__oe$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe_ok$59 + wire width 1 \pipe_end_logical_op__oe__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe_end_logical_op__invert_in$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -54559,12 +55023,12 @@ module \alu_div0 connect \muxid \pipe_end_muxid connect \logical_op__insn_type \pipe_end_logical_op__insn_type connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_end_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data + connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc_ok + connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe_ok + connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok connect \logical_op__invert_in \pipe_end_logical_op__invert_in connect \logical_op__zero_a \pipe_end_logical_op__zero_a connect \logical_op__input_carry \pipe_end_logical_op__input_carry @@ -54590,12 +55054,12 @@ module \alu_div0 connect \muxid$1 \pipe_end_muxid$51 connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 - connect \logical_op__imm_data__imm$4 \pipe_end_logical_op__imm_data__imm$54 - connect \logical_op__imm_data__imm_ok$5 \pipe_end_logical_op__imm_data__imm_ok$55 + connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 + connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 - connect \logical_op__rc__rc_ok$7 \pipe_end_logical_op__rc__rc_ok$57 + connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 - connect \logical_op__oe__oe_ok$9 \pipe_end_logical_op__oe__oe_ok$59 + connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 @@ -54633,12 +55097,12 @@ module \alu_div0 process $group_3 assign \pipe_middle_0_logical_op__insn_type 7'0000000 assign \pipe_middle_0_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_0_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_logical_op__imm_data__ok 1'0 assign \pipe_middle_0_logical_op__rc__rc 1'0 - assign \pipe_middle_0_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_0_logical_op__rc__ok 1'0 assign \pipe_middle_0_logical_op__oe__oe 1'0 - assign \pipe_middle_0_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_0_logical_op__oe__ok 1'0 assign \pipe_middle_0_logical_op__invert_in 1'0 assign \pipe_middle_0_logical_op__zero_a 1'0 assign \pipe_middle_0_logical_op__input_carry 2'00 @@ -54649,7 +55113,7 @@ module \alu_div0 assign \pipe_middle_0_logical_op__is_signed 1'0 assign \pipe_middle_0_logical_op__data_len 4'0000 assign \pipe_middle_0_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in { \pipe_middle_0_logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe } { \pipe_middle_0_logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc } { \pipe_middle_0_logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm } \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in { \pipe_start_logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe } { \pipe_start_logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc } { \pipe_start_logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm } \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + assign { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in { \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe } { \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc } { \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data } \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in { \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe } { \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc } { \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data } \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } sync init end process $group_21 @@ -54725,12 +55189,12 @@ module \alu_div0 process $group_35 assign \pipe_end_logical_op__insn_type 7'0000000 assign \pipe_end_logical_op__fn_unit 11'00000000000 - assign \pipe_end_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_logical_op__imm_data__imm_ok 1'0 + assign \pipe_end_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_logical_op__imm_data__ok 1'0 assign \pipe_end_logical_op__rc__rc 1'0 - assign \pipe_end_logical_op__rc__rc_ok 1'0 + assign \pipe_end_logical_op__rc__ok 1'0 assign \pipe_end_logical_op__oe__oe 1'0 - assign \pipe_end_logical_op__oe__oe_ok 1'0 + assign \pipe_end_logical_op__oe__ok 1'0 assign \pipe_end_logical_op__invert_in 1'0 assign \pipe_end_logical_op__zero_a 1'0 assign \pipe_end_logical_op__input_carry 2'00 @@ -54741,7 +55205,7 @@ module \alu_div0 assign \pipe_end_logical_op__is_signed 1'0 assign \pipe_end_logical_op__data_len 4'0000 assign \pipe_end_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in { \pipe_end_logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 { \pipe_middle_0_logical_op__oe__oe_ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__rc_ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__imm_ok$28 \pipe_middle_0_logical_op__imm_data__imm$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in { \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 { \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } sync init end process $group_53 @@ -54814,12 +55278,12 @@ module \alu_div0 process $group_66 assign \pipe_start_logical_op__insn_type$3 7'0000000 assign \pipe_start_logical_op__fn_unit$4 11'00000000000 - assign \pipe_start_logical_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_logical_op__imm_data__imm_ok$6 1'0 + assign \pipe_start_logical_op__imm_data__data$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_logical_op__imm_data__ok$6 1'0 assign \pipe_start_logical_op__rc__rc$7 1'0 - assign \pipe_start_logical_op__rc__rc_ok$8 1'0 + assign \pipe_start_logical_op__rc__ok$8 1'0 assign \pipe_start_logical_op__oe__oe$9 1'0 - assign \pipe_start_logical_op__oe__oe_ok$10 1'0 + assign \pipe_start_logical_op__oe__ok$10 1'0 assign \pipe_start_logical_op__invert_in$11 1'0 assign \pipe_start_logical_op__zero_a$12 1'0 assign \pipe_start_logical_op__input_carry$13 2'00 @@ -54830,7 +55294,7 @@ module \alu_div0 assign \pipe_start_logical_op__is_signed$18 1'0 assign \pipe_start_logical_op__data_len$19 4'0000 assign \pipe_start_logical_op__insn$20 32'00000000000000000000000000000000 - assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 { \pipe_start_logical_op__oe__oe_ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__rc_ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__imm_ok$6 \pipe_start_logical_op__imm_data__imm$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 { \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } sync init end process $group_84 @@ -54955,17 +55419,17 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \logical_op__fn_unit$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$74 + wire width 64 \logical_op__imm_data__data$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$75 + wire width 1 \logical_op__imm_data__ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__rc__rc$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$77 + wire width 1 \logical_op__rc__ok$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__oe__oe$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$79 + wire width 1 \logical_op__oe__ok$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \logical_op__invert_in$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -54993,12 +55457,12 @@ module \alu_div0 process $group_90 assign \logical_op__insn_type$72 7'0000000 assign \logical_op__fn_unit$73 11'00000000000 - assign \logical_op__imm_data__imm$74 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$75 1'0 + assign \logical_op__imm_data__data$74 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__ok$75 1'0 assign \logical_op__rc__rc$76 1'0 - assign \logical_op__rc__rc_ok$77 1'0 + assign \logical_op__rc__ok$77 1'0 assign \logical_op__oe__oe$78 1'0 - assign \logical_op__oe__oe_ok$79 1'0 + assign \logical_op__oe__ok$79 1'0 assign \logical_op__invert_in$80 1'0 assign \logical_op__zero_a$81 1'0 assign \logical_op__input_carry$82 2'00 @@ -55009,7 +55473,7 @@ module \alu_div0 assign \logical_op__is_signed$87 1'0 assign \logical_op__data_len$88 4'0000 assign \logical_op__insn$89 32'00000000000000000000000000000000 - assign { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 { \logical_op__oe__oe_ok$79 \logical_op__oe__oe$78 } { \logical_op__rc__rc_ok$77 \logical_op__rc__rc$76 } { \logical_op__imm_data__imm_ok$75 \logical_op__imm_data__imm$74 } \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 { \pipe_end_logical_op__oe__oe_ok$59 \pipe_end_logical_op__oe__oe$58 } { \pipe_end_logical_op__rc__rc_ok$57 \pipe_end_logical_op__rc__rc$56 } { \pipe_end_logical_op__imm_data__imm_ok$55 \pipe_end_logical_op__imm_data__imm$54 } \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } + assign { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 { \logical_op__oe__ok$79 \logical_op__oe__oe$78 } { \logical_op__rc__ok$77 \logical_op__rc__rc$76 } { \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 } \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 { \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 } { \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 } { \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 } \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } sync init end process $group_108 @@ -55041,9 +55505,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" module \src_l$81 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src @@ -55186,9 +55650,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" module \opc_l$82 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -55331,9 +55795,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" module \req_l$83 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 output 2 \q_req @@ -55476,9 +55940,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" module \rst_l$84 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -55621,9 +56085,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" module \rok_l$85 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -55766,9 +56230,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" module \alui_l$86 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -55911,9 +56375,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" module \alu_l$87 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -56056,7 +56520,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0" module \div0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -56148,17 +56612,17 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_div0__imm_data__imm + wire width 64 input 3 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_div0__imm_data__imm_ok + wire width 1 input 4 \oper_i_alu_div0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_div0__rc__rc_ok + wire width 1 input 6 \oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_div0__oe__oe_ok + wire width 1 input 8 \oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -56219,7 +56683,7 @@ module \div0 wire width 1 output 35 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 1 output 36 \dest4_o - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 37 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_div0_n_valid_o @@ -56319,29 +56783,29 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_div0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__imm + wire width 64 \alu_div0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__imm$next + wire width 64 \alu_div0_logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__imm_data__imm_ok + wire width 1 \alu_div0_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__imm_data__imm_ok$next + wire width 1 \alu_div0_logical_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_div0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_div0_logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__rc_ok + wire width 1 \alu_div0_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__rc_ok$next + wire width 1 \alu_div0_logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_div0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_div0_logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__oe_ok + wire width 1 \alu_div0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__oe_ok$next + wire width 1 \alu_div0_logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_div0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -56415,12 +56879,12 @@ module \div0 connect \n_ready_i \alu_div0_n_ready_i connect \logical_op__insn_type \alu_div0_logical_op__insn_type connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit - connect \logical_op__imm_data__imm \alu_div0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm_ok + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc_ok + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe_ok + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok connect \logical_op__invert_in \alu_div0_logical_op__invert_in connect \logical_op__zero_a \alu_div0_logical_op__zero_a connect \logical_op__input_carry \alu_div0_logical_op__input_carry @@ -57247,12 +57711,12 @@ module \div0 process $group_27 assign \alu_div0_logical_op__insn_type$next \alu_div0_logical_op__insn_type assign \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__fn_unit - assign \alu_div0_logical_op__imm_data__imm$next \alu_div0_logical_op__imm_data__imm - assign \alu_div0_logical_op__imm_data__imm_ok$next \alu_div0_logical_op__imm_data__imm_ok + assign \alu_div0_logical_op__imm_data__data$next \alu_div0_logical_op__imm_data__data + assign \alu_div0_logical_op__imm_data__ok$next \alu_div0_logical_op__imm_data__ok assign \alu_div0_logical_op__rc__rc$next \alu_div0_logical_op__rc__rc - assign \alu_div0_logical_op__rc__rc_ok$next \alu_div0_logical_op__rc__rc_ok + assign \alu_div0_logical_op__rc__ok$next \alu_div0_logical_op__rc__ok assign \alu_div0_logical_op__oe__oe$next \alu_div0_logical_op__oe__oe - assign \alu_div0_logical_op__oe__oe_ok$next \alu_div0_logical_op__oe__oe_ok + assign \alu_div0_logical_op__oe__ok$next \alu_div0_logical_op__oe__ok assign \alu_div0_logical_op__invert_in$next \alu_div0_logical_op__invert_in assign \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__zero_a assign \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__input_carry @@ -57267,27 +57731,27 @@ module \div0 switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_div0_logical_op__insn$next \alu_div0_logical_op__data_len$next \alu_div0_logical_op__is_signed$next \alu_div0_logical_op__is_32bit$next \alu_div0_logical_op__output_carry$next \alu_div0_logical_op__write_cr0$next \alu_div0_logical_op__invert_out$next \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__invert_in$next { \alu_div0_logical_op__oe__oe_ok$next \alu_div0_logical_op__oe__oe$next } { \alu_div0_logical_op__rc__rc_ok$next \alu_div0_logical_op__rc__rc$next } { \alu_div0_logical_op__imm_data__imm_ok$next \alu_div0_logical_op__imm_data__imm$next } \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__insn_type$next } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in { \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { \alu_div0_logical_op__insn$next \alu_div0_logical_op__data_len$next \alu_div0_logical_op__is_signed$next \alu_div0_logical_op__is_32bit$next \alu_div0_logical_op__output_carry$next \alu_div0_logical_op__write_cr0$next \alu_div0_logical_op__invert_out$next \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__invert_in$next { \alu_div0_logical_op__oe__ok$next \alu_div0_logical_op__oe__oe$next } { \alu_div0_logical_op__rc__ok$next \alu_div0_logical_op__rc__rc$next } { \alu_div0_logical_op__imm_data__ok$next \alu_div0_logical_op__imm_data__data$next } \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__insn_type$next } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in { \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_div0_logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_logical_op__imm_data__imm_ok$next 1'0 + assign \alu_div0_logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_div0_logical_op__imm_data__ok$next 1'0 assign \alu_div0_logical_op__rc__rc$next 1'0 - assign \alu_div0_logical_op__rc__rc_ok$next 1'0 + assign \alu_div0_logical_op__rc__ok$next 1'0 assign \alu_div0_logical_op__oe__oe$next 1'0 - assign \alu_div0_logical_op__oe__oe_ok$next 1'0 + assign \alu_div0_logical_op__oe__ok$next 1'0 end sync init update \alu_div0_logical_op__insn_type 7'0000000 update \alu_div0_logical_op__fn_unit 11'00000000000 - update \alu_div0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_div0_logical_op__imm_data__imm_ok 1'0 + update \alu_div0_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_div0_logical_op__imm_data__ok 1'0 update \alu_div0_logical_op__rc__rc 1'0 - update \alu_div0_logical_op__rc__rc_ok 1'0 + update \alu_div0_logical_op__rc__ok 1'0 update \alu_div0_logical_op__oe__oe 1'0 - update \alu_div0_logical_op__oe__oe_ok 1'0 + update \alu_div0_logical_op__oe__ok 1'0 update \alu_div0_logical_op__invert_in 1'0 update \alu_div0_logical_op__zero_a 1'0 update \alu_div0_logical_op__input_carry 2'00 @@ -57301,12 +57765,12 @@ module \div0 sync posedge \coresync_clk update \alu_div0_logical_op__insn_type \alu_div0_logical_op__insn_type$next update \alu_div0_logical_op__fn_unit \alu_div0_logical_op__fn_unit$next - update \alu_div0_logical_op__imm_data__imm \alu_div0_logical_op__imm_data__imm$next - update \alu_div0_logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm_ok$next + update \alu_div0_logical_op__imm_data__data \alu_div0_logical_op__imm_data__data$next + update \alu_div0_logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok$next update \alu_div0_logical_op__rc__rc \alu_div0_logical_op__rc__rc$next - update \alu_div0_logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc_ok$next + update \alu_div0_logical_op__rc__ok \alu_div0_logical_op__rc__ok$next update \alu_div0_logical_op__oe__oe \alu_div0_logical_op__oe__oe$next - update \alu_div0_logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe_ok$next + update \alu_div0_logical_op__oe__ok \alu_div0_logical_op__oe__ok$next update \alu_div0_logical_op__invert_in \alu_div0_logical_op__invert_in$next update \alu_div0_logical_op__zero_a \alu_div0_logical_op__zero_a$next update \alu_div0_logical_op__input_carry \alu_div0_logical_op__input_carry$next @@ -57558,7 +58022,7 @@ module \div0 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__imm_data__imm_ok + connect \S \alu_div0_logical_op__imm_data__ok connect \Y $83 end process $group_56 @@ -57574,8 +58038,8 @@ module \div0 cell $mux $87 parameter \WIDTH 64 connect \A \src2_i - connect \B \alu_div0_logical_op__imm_data__imm - connect \S \alu_div0_logical_op__imm_data__imm_ok + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok connect \Y $86 end process $group_57 @@ -57786,7 +58250,7 @@ module \div0 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__imm_data__imm_ok + connect \A \alu_div0_logical_op__imm_data__ok connect \Y $102 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -58217,17 +58681,17 @@ module \input$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -58334,17 +58798,17 @@ module \input$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__imm$4 + wire width 64 output 19 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \mul_op__imm_data__imm_ok$5 + wire width 1 output 20 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__rc__rc_ok$7 + wire width 1 output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__oe__oe_ok$9 + wire width 1 output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -58386,12 +58850,7 @@ module \input$92 end process $group_4 assign \xer_so$16 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" - switch { \mul_op__oe__oe_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" - case 1'1 - assign \xer_so$16 \xer_so - end + assign \xer_so$16 \xer_so sync init end process $group_5 @@ -58402,17 +58861,17 @@ module \input$92 process $group_6 assign \mul_op__insn_type$2 7'0000000 assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5 1'0 assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__rc__ok$7 1'0 assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__oe__ok$9 1'0 assign \mul_op__write_cr0$10 1'0 assign \mul_op__is_32bit$11 1'0 assign \mul_op__is_signed$12 1'0 assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end end @@ -58511,17 +58970,17 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -58628,17 +59087,17 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__imm$4 + wire width 64 output 19 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \mul_op__imm_data__imm_ok$5 + wire width 1 output 20 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__rc__rc_ok$7 + wire width 1 output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__oe__oe_ok$9 + wire width 1 output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -58925,26 +59384,26 @@ module \mul1 process $group_13 assign \mul_op__insn_type$2 7'0000000 assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5 1'0 assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__rc__ok$7 1'0 assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__oe__ok$9 1'0 assign \mul_op__write_cr0$10 1'0 assign \mul_op__is_32bit$11 1'0 assign \mul_op__is_signed$12 1'0 assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" module \mul_pipe1 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 2 \n_valid_o @@ -59048,29 +59507,29 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \mul_op__imm_data__imm + wire width 64 output 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$next + wire width 64 \mul_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \mul_op__imm_data__imm_ok + wire width 1 output 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$next + wire width 1 \mul_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 9 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \mul_op__rc__rc_ok + wire width 1 output 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$next + wire width 1 \mul_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \mul_op__oe__oe_ok + wire width 1 output 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$next + wire width 1 \mul_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -59203,17 +59662,17 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 26 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 27 \mul_op__imm_data__imm$4 + wire width 64 input 27 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 28 \mul_op__imm_data__imm_ok$5 + wire width 1 input 28 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 29 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 30 \mul_op__rc__rc_ok$7 + wire width 1 input 30 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 31 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 32 \mul_op__oe__oe_ok$9 + wire width 1 input 32 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 33 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -59328,17 +59787,17 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__imm + wire width 64 \input_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__imm_data__imm_ok + wire width 1 \input_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__rc__rc_ok + wire width 1 \input_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__oe__oe_ok + wire width 1 \input_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -59445,17 +59904,17 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__imm$20 + wire width 64 \input_mul_op__imm_data__data$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__imm_data__imm_ok$21 + wire width 1 \input_mul_op__imm_data__ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_mul_op__rc__rc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__rc__rc_ok$23 + wire width 1 \input_mul_op__rc__ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_mul_op__oe__oe$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__oe__oe_ok$25 + wire width 1 \input_mul_op__oe__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_mul_op__write_cr0$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -59474,12 +59933,12 @@ module \mul_pipe1 connect \muxid \input_muxid connect \mul_op__insn_type \input_mul_op__insn_type connect \mul_op__fn_unit \input_mul_op__fn_unit - connect \mul_op__imm_data__imm \input_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok connect \mul_op__rc__rc \input_mul_op__rc__rc - connect \mul_op__rc__rc_ok \input_mul_op__rc__rc_ok + connect \mul_op__rc__ok \input_mul_op__rc__ok connect \mul_op__oe__oe \input_mul_op__oe__oe - connect \mul_op__oe__oe_ok \input_mul_op__oe__oe_ok + connect \mul_op__oe__ok \input_mul_op__oe__ok connect \mul_op__write_cr0 \input_mul_op__write_cr0 connect \mul_op__is_32bit \input_mul_op__is_32bit connect \mul_op__is_signed \input_mul_op__is_signed @@ -59490,12 +59949,12 @@ module \mul_pipe1 connect \muxid$1 \input_muxid$17 connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 - connect \mul_op__imm_data__imm$4 \input_mul_op__imm_data__imm$20 - connect \mul_op__imm_data__imm_ok$5 \input_mul_op__imm_data__imm_ok$21 + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 - connect \mul_op__rc__rc_ok$7 \input_mul_op__rc__rc_ok$23 + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 - connect \mul_op__oe__oe_ok$9 \input_mul_op__oe__oe_ok$25 + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 @@ -59596,17 +60055,17 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul1_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__imm + wire width 64 \mul1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__imm_data__imm_ok + wire width 1 \mul1_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul1_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__rc__rc_ok + wire width 1 \mul1_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul1_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__oe_ok + wire width 1 \mul1_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul1_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -59713,17 +60172,17 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul1_mul_op__fn_unit$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__imm$36 + wire width 64 \mul1_mul_op__imm_data__data$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__imm_data__imm_ok$37 + wire width 1 \mul1_mul_op__imm_data__ok$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul1_mul_op__rc__rc$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__rc__rc_ok$39 + wire width 1 \mul1_mul_op__rc__ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul1_mul_op__oe__oe$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__oe_ok$41 + wire width 1 \mul1_mul_op__oe__ok$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul1_mul_op__write_cr0$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -59746,12 +60205,12 @@ module \mul_pipe1 connect \muxid \mul1_muxid connect \mul_op__insn_type \mul1_mul_op__insn_type connect \mul_op__fn_unit \mul1_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul1_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok connect \mul_op__rc__rc \mul1_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul1_mul_op__rc__rc_ok + connect \mul_op__rc__ok \mul1_mul_op__rc__ok connect \mul_op__oe__oe \mul1_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul1_mul_op__oe__oe_ok + connect \mul_op__oe__ok \mul1_mul_op__oe__ok connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 connect \mul_op__is_32bit \mul1_mul_op__is_32bit connect \mul_op__is_signed \mul1_mul_op__is_signed @@ -59762,12 +60221,12 @@ module \mul_pipe1 connect \muxid$1 \mul1_muxid$33 connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 - connect \mul_op__imm_data__imm$4 \mul1_mul_op__imm_data__imm$36 - connect \mul_op__imm_data__imm_ok$5 \mul1_mul_op__imm_data__imm_ok$37 + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 - connect \mul_op__rc__rc_ok$7 \mul1_mul_op__rc__rc_ok$39 + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 - connect \mul_op__oe__oe_ok$9 \mul1_mul_op__oe__oe_ok$41 + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 @@ -59786,17 +60245,17 @@ module \mul_pipe1 process $group_1 assign \input_mul_op__insn_type 7'0000000 assign \input_mul_op__fn_unit 11'00000000000 - assign \input_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_mul_op__imm_data__imm_ok 1'0 + assign \input_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_mul_op__imm_data__ok 1'0 assign \input_mul_op__rc__rc 1'0 - assign \input_mul_op__rc__rc_ok 1'0 + assign \input_mul_op__rc__ok 1'0 assign \input_mul_op__oe__oe 1'0 - assign \input_mul_op__oe__oe_ok 1'0 + assign \input_mul_op__oe__ok 1'0 assign \input_mul_op__write_cr0 1'0 assign \input_mul_op__is_32bit 1'0 assign \input_mul_op__is_signed 1'0 assign \input_mul_op__insn 32'00000000000000000000000000000000 - assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 { \input_mul_op__oe__oe_ok \input_mul_op__oe__oe } { \input_mul_op__rc__rc_ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } + assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 { \input_mul_op__oe__ok \input_mul_op__oe__oe } { \input_mul_op__rc__ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__ok \input_mul_op__imm_data__data } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } sync init end process $group_13 @@ -59822,17 +60281,17 @@ module \mul_pipe1 process $group_17 assign \mul1_mul_op__insn_type 7'0000000 assign \mul1_mul_op__fn_unit 11'00000000000 - assign \mul1_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_mul_op__imm_data__imm_ok 1'0 + assign \mul1_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul1_mul_op__imm_data__ok 1'0 assign \mul1_mul_op__rc__rc 1'0 - assign \mul1_mul_op__rc__rc_ok 1'0 + assign \mul1_mul_op__rc__ok 1'0 assign \mul1_mul_op__oe__oe 1'0 - assign \mul1_mul_op__oe__oe_ok 1'0 + assign \mul1_mul_op__oe__ok 1'0 assign \mul1_mul_op__write_cr0 1'0 assign \mul1_mul_op__is_32bit 1'0 assign \mul1_mul_op__is_signed 1'0 assign \mul1_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 { \mul1_mul_op__oe__oe_ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__rc_ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 { \input_mul_op__oe__oe_ok$25 \input_mul_op__oe__oe$24 } { \input_mul_op__rc__rc_ok$23 \input_mul_op__rc__rc$22 } { \input_mul_op__imm_data__imm_ok$21 \input_mul_op__imm_data__imm$20 } \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 { \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 { \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 } { \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 } { \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 } \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } sync init end process $group_29 @@ -59981,17 +60440,17 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_op__fn_unit$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$55 + wire width 64 \mul_op__imm_data__data$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$56 + wire width 1 \mul_op__imm_data__ok$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__rc__rc$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$58 + wire width 1 \mul_op__rc__ok$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__oe__oe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$60 + wire width 1 \mul_op__oe__ok$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__write_cr0$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -60003,17 +60462,17 @@ module \mul_pipe1 process $group_36 assign \mul_op__insn_type$53 7'0000000 assign \mul_op__fn_unit$54 11'00000000000 - assign \mul_op__imm_data__imm$55 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$56 1'0 + assign \mul_op__imm_data__data$55 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$56 1'0 assign \mul_op__rc__rc$57 1'0 - assign \mul_op__rc__rc_ok$58 1'0 + assign \mul_op__rc__ok$58 1'0 assign \mul_op__oe__oe$59 1'0 - assign \mul_op__oe__oe_ok$60 1'0 + assign \mul_op__oe__ok$60 1'0 assign \mul_op__write_cr0$61 1'0 assign \mul_op__is_32bit$62 1'0 assign \mul_op__is_signed$63 1'0 assign \mul_op__insn$64 32'00000000000000000000000000000000 - assign { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__oe_ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__rc_ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__imm_ok$56 \mul_op__imm_data__imm$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 { \mul1_mul_op__oe__oe_ok$41 \mul1_mul_op__oe__oe$40 } { \mul1_mul_op__rc__rc_ok$39 \mul1_mul_op__rc__rc$38 } { \mul1_mul_op__imm_data__imm_ok$37 \mul1_mul_op__imm_data__imm$36 } \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + assign { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 { \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 } { \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 } { \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 } \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -60095,12 +60554,12 @@ module \mul_pipe1 process $group_55 assign \mul_op__insn_type$next \mul_op__insn_type assign \mul_op__fn_unit$next \mul_op__fn_unit - assign \mul_op__imm_data__imm$next \mul_op__imm_data__imm - assign \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm_ok + assign \mul_op__imm_data__data$next \mul_op__imm_data__data + assign \mul_op__imm_data__ok$next \mul_op__imm_data__ok assign \mul_op__rc__rc$next \mul_op__rc__rc - assign \mul_op__rc__rc_ok$next \mul_op__rc__rc_ok + assign \mul_op__rc__ok$next \mul_op__rc__ok assign \mul_op__oe__oe$next \mul_op__oe__oe - assign \mul_op__oe__oe_ok$next \mul_op__oe__oe_ok + assign \mul_op__oe__ok$next \mul_op__oe__ok assign \mul_op__write_cr0$next \mul_op__write_cr0 assign \mul_op__is_32bit$next \mul_op__is_32bit assign \mul_op__is_signed$next \mul_op__is_signed @@ -60109,30 +60568,30 @@ module \mul_pipe1 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__oe_ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__rc_ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__imm_ok$56 \mul_op__imm_data__imm$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__ok$next \mul_op__oe__oe$next } { \mul_op__rc__ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__ok$next \mul_op__imm_data__data$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__oe_ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__rc_ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__imm_ok$56 \mul_op__imm_data__imm$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__ok$next \mul_op__oe__oe$next } { \mul_op__rc__ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__ok$next \mul_op__imm_data__data$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$next 1'0 + assign \mul_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$next 1'0 assign \mul_op__rc__rc$next 1'0 - assign \mul_op__rc__rc_ok$next 1'0 + assign \mul_op__rc__ok$next 1'0 assign \mul_op__oe__oe$next 1'0 - assign \mul_op__oe__oe_ok$next 1'0 + assign \mul_op__oe__ok$next 1'0 end sync init update \mul_op__insn_type 7'0000000 update \mul_op__fn_unit 11'00000000000 - update \mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__imm_ok 1'0 + update \mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \mul_op__imm_data__ok 1'0 update \mul_op__rc__rc 1'0 - update \mul_op__rc__rc_ok 1'0 + update \mul_op__rc__ok 1'0 update \mul_op__oe__oe 1'0 - update \mul_op__oe__oe_ok 1'0 + update \mul_op__oe__ok 1'0 update \mul_op__write_cr0 1'0 update \mul_op__is_32bit 1'0 update \mul_op__is_signed 1'0 @@ -60140,12 +60599,12 @@ module \mul_pipe1 sync posedge \coresync_clk update \mul_op__insn_type \mul_op__insn_type$next update \mul_op__fn_unit \mul_op__fn_unit$next - update \mul_op__imm_data__imm \mul_op__imm_data__imm$next - update \mul_op__imm_data__imm_ok \mul_op__imm_data__imm_ok$next + update \mul_op__imm_data__data \mul_op__imm_data__data$next + update \mul_op__imm_data__ok \mul_op__imm_data__ok$next update \mul_op__rc__rc \mul_op__rc__rc$next - update \mul_op__rc__rc_ok \mul_op__rc__rc_ok$next + update \mul_op__rc__ok \mul_op__rc__ok$next update \mul_op__oe__oe \mul_op__oe__oe$next - update \mul_op__oe__oe_ok \mul_op__oe__oe_ok$next + update \mul_op__oe__ok \mul_op__oe__ok$next update \mul_op__write_cr0 \mul_op__write_cr0$next update \mul_op__is_32bit \mul_op__is_32bit$next update \mul_op__is_signed \mul_op__is_signed$next @@ -60393,17 +60852,17 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -60514,17 +60973,17 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 21 \mul_op__imm_data__imm$4 + wire width 64 output 21 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__imm_data__imm_ok$5 + wire width 1 output 22 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 23 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__rc_ok$7 + wire width 1 output 24 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 25 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__oe_ok$9 + wire width 1 output 26 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 27 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -60592,26 +61051,26 @@ module \mul2 process $group_5 assign \mul_op__insn_type$2 7'0000000 assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5 1'0 assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__rc__ok$7 1'0 assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__oe__ok$9 1'0 assign \mul_op__write_cr0$10 1'0 assign \mul_op__is_32bit$11 1'0 assign \mul_op__is_signed$12 1'0 assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" module \mul_pipe2 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -60709,17 +61168,17 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__imm + wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__imm_data__imm_ok + wire width 1 input 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__rc__rc_ok + wire width 1 input 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__oe__oe_ok + wire width 1 input 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -60840,29 +61299,29 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 27 \mul_op__imm_data__imm$4 + wire width 64 output 27 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$4$next + wire width 64 \mul_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__imm_data__imm_ok$5 + wire width 1 output 28 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$5$next + wire width 1 \mul_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 29 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__rc__rc_ok$7 + wire width 1 output 30 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$7$next + wire width 1 \mul_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 31 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__oe__oe_ok$9 + wire width 1 output 32 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$9$next + wire width 1 \mul_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 33 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -60995,17 +61454,17 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul2_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__imm + wire width 64 \mul2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__imm_data__imm_ok + wire width 1 \mul2_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul2_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc_ok + wire width 1 \mul2_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul2_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe_ok + wire width 1 \mul2_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul2_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -61116,17 +61575,17 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul2_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__imm$20 + wire width 64 \mul2_mul_op__imm_data__data$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__imm_data__imm_ok$21 + wire width 1 \mul2_mul_op__imm_data__ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul2_mul_op__rc__rc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc_ok$23 + wire width 1 \mul2_mul_op__rc__ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul2_mul_op__oe__oe$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe_ok$25 + wire width 1 \mul2_mul_op__oe__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul2_mul_op__write_cr0$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -61147,12 +61606,12 @@ module \mul_pipe2 connect \muxid \mul2_muxid connect \mul_op__insn_type \mul2_mul_op__insn_type connect \mul_op__fn_unit \mul2_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul2_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok connect \mul_op__rc__rc \mul2_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul2_mul_op__rc__rc_ok + connect \mul_op__rc__ok \mul2_mul_op__rc__ok connect \mul_op__oe__oe \mul2_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul2_mul_op__oe__oe_ok + connect \mul_op__oe__ok \mul2_mul_op__oe__ok connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 connect \mul_op__is_32bit \mul2_mul_op__is_32bit connect \mul_op__is_signed \mul2_mul_op__is_signed @@ -61165,12 +61624,12 @@ module \mul_pipe2 connect \muxid$1 \mul2_muxid$17 connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 - connect \mul_op__imm_data__imm$4 \mul2_mul_op__imm_data__imm$20 - connect \mul_op__imm_data__imm_ok$5 \mul2_mul_op__imm_data__imm_ok$21 + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 - connect \mul_op__rc__rc_ok$7 \mul2_mul_op__rc__rc_ok$23 + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 - connect \mul_op__oe__oe_ok$9 \mul2_mul_op__oe__oe_ok$25 + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 @@ -61188,17 +61647,17 @@ module \mul_pipe2 process $group_1 assign \mul2_mul_op__insn_type 7'0000000 assign \mul2_mul_op__fn_unit 11'00000000000 - assign \mul2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_mul_op__imm_data__imm_ok 1'0 + assign \mul2_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul2_mul_op__imm_data__ok 1'0 assign \mul2_mul_op__rc__rc 1'0 - assign \mul2_mul_op__rc__rc_ok 1'0 + assign \mul2_mul_op__rc__ok 1'0 assign \mul2_mul_op__oe__oe 1'0 - assign \mul2_mul_op__oe__oe_ok 1'0 + assign \mul2_mul_op__oe__ok 1'0 assign \mul2_mul_op__write_cr0 1'0 assign \mul2_mul_op__is_32bit 1'0 assign \mul2_mul_op__is_signed 1'0 assign \mul2_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 { \mul2_mul_op__oe__oe_ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__rc_ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 { \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end process $group_13 @@ -61357,17 +61816,17 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_op__fn_unit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$39 + wire width 64 \mul_op__imm_data__data$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$40 + wire width 1 \mul_op__imm_data__ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__rc__rc$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$42 + wire width 1 \mul_op__rc__ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__oe__oe$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$44 + wire width 1 \mul_op__oe__ok$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__write_cr0$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -61379,17 +61838,17 @@ module \mul_pipe2 process $group_22 assign \mul_op__insn_type$37 7'0000000 assign \mul_op__fn_unit$38 11'00000000000 - assign \mul_op__imm_data__imm$39 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$40 1'0 + assign \mul_op__imm_data__data$39 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$40 1'0 assign \mul_op__rc__rc$41 1'0 - assign \mul_op__rc__rc_ok$42 1'0 + assign \mul_op__rc__ok$42 1'0 assign \mul_op__oe__oe$43 1'0 - assign \mul_op__oe__oe_ok$44 1'0 + assign \mul_op__oe__ok$44 1'0 assign \mul_op__write_cr0$45 1'0 assign \mul_op__is_32bit$46 1'0 assign \mul_op__is_signed$47 1'0 assign \mul_op__insn$48 32'00000000000000000000000000000000 - assign { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__oe_ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__rc_ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__imm_ok$40 \mul_op__imm_data__imm$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 { \mul2_mul_op__oe__oe_ok$25 \mul2_mul_op__oe__oe$24 } { \mul2_mul_op__rc__rc_ok$23 \mul2_mul_op__rc__rc$22 } { \mul2_mul_op__imm_data__imm_ok$21 \mul2_mul_op__imm_data__imm$20 } \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + assign { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 { \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 } { \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 } { \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 } \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -61464,12 +61923,12 @@ module \mul_pipe2 process $group_40 assign \mul_op__insn_type$2$next \mul_op__insn_type$2 assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 - assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4 - assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5 + assign \mul_op__imm_data__data$4$next \mul_op__imm_data__data$4 + assign \mul_op__imm_data__ok$5$next \mul_op__imm_data__ok$5 assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 - assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7 + assign \mul_op__rc__ok$7$next \mul_op__rc__ok$7 assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 - assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9 + assign \mul_op__oe__ok$9$next \mul_op__oe__ok$9 assign \mul_op__write_cr0$10$next \mul_op__write_cr0$10 assign \mul_op__is_32bit$11$next \mul_op__is_32bit$11 assign \mul_op__is_signed$12$next \mul_op__is_signed$12 @@ -61478,30 +61937,30 @@ module \mul_pipe2 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__oe_ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__rc_ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__imm_ok$40 \mul_op__imm_data__imm$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__oe_ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__rc_ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__imm_ok$40 \mul_op__imm_data__imm$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5$next 1'0 + assign \mul_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5$next 1'0 assign \mul_op__rc__rc$6$next 1'0 - assign \mul_op__rc__rc_ok$7$next 1'0 + assign \mul_op__rc__ok$7$next 1'0 assign \mul_op__oe__oe$8$next 1'0 - assign \mul_op__oe__oe_ok$9$next 1'0 + assign \mul_op__oe__ok$9$next 1'0 end sync init update \mul_op__insn_type$2 7'0000000 update \mul_op__fn_unit$3 11'00000000000 - update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__imm_ok$5 1'0 + update \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \mul_op__imm_data__ok$5 1'0 update \mul_op__rc__rc$6 1'0 - update \mul_op__rc__rc_ok$7 1'0 + update \mul_op__rc__ok$7 1'0 update \mul_op__oe__oe$8 1'0 - update \mul_op__oe__oe_ok$9 1'0 + update \mul_op__oe__ok$9 1'0 update \mul_op__write_cr0$10 1'0 update \mul_op__is_32bit$11 1'0 update \mul_op__is_signed$12 1'0 @@ -61509,12 +61968,12 @@ module \mul_pipe2 sync posedge \coresync_clk update \mul_op__insn_type$2 \mul_op__insn_type$2$next update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next - update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next - update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next + update \mul_op__imm_data__data$4 \mul_op__imm_data__data$4$next + update \mul_op__imm_data__ok$5 \mul_op__imm_data__ok$5$next update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next - update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next + update \mul_op__rc__ok$7 \mul_op__rc__ok$7$next update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next - update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next + update \mul_op__oe__ok$9 \mul_op__oe__ok$9$next update \mul_op__write_cr0$10 \mul_op__write_cr0$10$next update \mul_op__is_32bit$11 \mul_op__is_32bit$11$next update \mul_op__is_signed$12 \mul_op__is_signed$12$next @@ -61746,17 +62205,17 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -61863,17 +62322,17 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__imm$4 + wire width 64 output 19 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \mul_op__imm_data__imm_ok$5 + wire width 1 output 20 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__rc__rc_ok$7 + wire width 1 output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__oe__oe_ok$9 + wire width 1 output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -61892,6 +62351,8 @@ module \mul3 wire width 1 output 32 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire width 1 \is_32bit process $group_0 @@ -61939,19 +62400,11 @@ module \mul3 assign \mul_o $16 [128:0] sync init end - wire width 1 $verilog_initial_trigger process $group_2 - assign \o_ok 1'0 - assign \o_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_3 assign \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" attribute \nmigen.decoding "OP_MUL_H32/52" case 7'0110100 assign \o$14 { \mul_o [63:32] \mul_o [63:32] } @@ -61959,18 +62412,37 @@ module \mul3 attribute \nmigen.decoding "OP_MUL_H64/51" case 7'0110011 assign \o$14 \mul_o [127:64] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" + attribute \nmigen.decoding "OP_MUL_L64/50" + case 7'0110010 assign \o$14 \mul_o [63:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:58" + process $group_3 + assign \o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" + attribute \nmigen.decoding "OP_MUL_H32/52" + case 7'0110100 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" + attribute \nmigen.decoding "OP_MUL_H64/51" + case 7'0110011 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" + attribute \nmigen.decoding "OP_MUL_L64/50" + case 7'0110010 + assign \o_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" wire width 1 \mul_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $reduce_bool $24 parameter \A_SIGNED 0 parameter \A_WIDTH 33 @@ -61978,11 +62450,11 @@ module \mul3 connect \A \mul_o [63:31] connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $reduce_and $27 parameter \A_SIGNED 0 parameter \A_WIDTH 33 @@ -61990,7 +62462,7 @@ module \mul3 connect \A \mul_o [63:31] connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -61998,9 +62470,9 @@ module \mul3 connect \A $26 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62011,9 +62483,9 @@ module \mul3 connect \B $25 connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 65 @@ -62021,11 +62493,11 @@ module \mul3 connect \A \mul_o [127:63] connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $reduce_and $35 parameter \A_SIGNED 0 parameter \A_WIDTH 65 @@ -62033,7 +62505,7 @@ module \mul3 connect \A \mul_o [127:63] connect \Y $34 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $not $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62041,9 +62513,9 @@ module \mul3 connect \A $34 connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $and $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62056,23 +62528,23 @@ module \mul3 end process $group_4 assign \mul_ov 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" attribute \nmigen.decoding "OP_MUL_H32/52" case 7'0110100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" attribute \nmigen.decoding "OP_MUL_H64/51" case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" + attribute \nmigen.decoding "OP_MUL_L64/50" + case 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" case 1'1 assign \mul_ov $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:66" case assign \mul_ov $37 end @@ -62081,62 +62553,73 @@ module \mul3 end process $group_5 assign \xer_ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" attribute \nmigen.decoding "OP_MUL_H32/52" case 7'0110100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" attribute \nmigen.decoding "OP_MUL_H64/51" case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" + attribute \nmigen.decoding "OP_MUL_L64/50" + case 7'0110010 assign \xer_ov { \mul_ov \mul_ov } end sync init end process $group_6 assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" attribute \nmigen.decoding "OP_MUL_H32/52" case 7'0110100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" attribute \nmigen.decoding "OP_MUL_H64/51" case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" + attribute \nmigen.decoding "OP_MUL_L64/50" + case 7'0110010 assign \xer_ov_ok 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $39 + end process $group_7 assign \xer_so$15 1'0 - assign \xer_so$15 \xer_so + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so$15 } $39 sync init end - process $group_8 + process $group_9 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_9 + process $group_10 assign \mul_op__insn_type$2 7'0000000 assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5 1'0 assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__rc__ok$7 1'0 assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__oe__ok$9 1'0 assign \mul_op__write_cr0$10 1'0 assign \mul_op__is_32bit$11 1'0 assign \mul_op__is_signed$12 1'0 assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end end @@ -62235,17 +62718,17 @@ module \output$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62356,17 +62839,17 @@ module \output$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 21 \mul_op__imm_data__imm$4 + wire width 64 output 21 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__imm_data__imm_ok$5 + wire width 1 output 22 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 23 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__rc_ok$7 + wire width 1 output 24 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 25 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__oe_ok$9 + wire width 1 output 26 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 27 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62391,36 +62874,71 @@ module \output$97 wire width 1 output 37 \xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 38 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $19 + end + process $group_0 + assign \oe 1'0 + assign \oe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire width 1 \so + process $group_1 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + case 1'1 + assign \so \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" + case + assign \so \xer_so + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $20 + wire width 65 $22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $21 + cell $pos $23 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $20 + connect \Y $22 end - process $group_0 - assign \o$19 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \o$19 $20 + process $group_2 + assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000 + assign \o$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - process $group_1 + process $group_3 assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$19 [63:0] + assign \target \o$21 [63:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $25 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -62428,19 +62946,19 @@ module \output$97 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $22 + connect \Y $24 end - process $group_2 + process $group_4 assign \is_cmp 1'0 - assign \is_cmp $22 + assign \is_cmp $24 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $27 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -62448,118 +62966,92 @@ module \output$97 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $24 + connect \Y $26 end - process $group_3 + process $group_5 assign \is_cmpeqb 1'0 - assign \is_cmpeqb $24 + assign \is_cmpeqb $26 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire width 1 \msb_test - process $group_4 + process $group_6 assign \msb_test 1'0 assign \msb_test \target [63] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_bool $29 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $26 + connect \Y $28 end - process $group_5 + process $group_7 assign \is_nzero 1'0 - assign \is_nzero $26 + assign \is_nzero $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire width 1 \is_negative + process $group_8 + assign \is_negative 1'0 + assign \is_negative \msb_test sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $28 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \B $28 - connect \Y $30 + connect \B $30 + connect \Y $32 end - process $group_6 + process $group_9 assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $30 - end + assign \is_positive $32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $32 + connect \A \is_cmpeqb + connect \B \is_cmp connect \Y $34 end - process $group_7 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $37 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62567,86 +63059,84 @@ module \output$97 connect \A \is_nzero connect \Y $36 end - process $group_8 + process $group_10 assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch { $34 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" case 1'1 assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" case - assign \cr0 { \is_negative \is_positive $36 \xer_so$18 } + assign \cr0 { \is_negative \is_positive $36 \so } end sync init end - process $group_9 + process $group_11 assign \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$14 \o$19 [63:0] + assign \o$14 \o$21 [63:0] sync init end - process $group_10 + process $group_12 assign \o_ok$15 1'0 assign \o_ok$15 \o_ok sync init end - process $group_11 + process $group_13 assign \cr_a$16 4'0000 assign \cr_a$16 \cr0 sync init end - process $group_12 + process $group_14 assign \cr_a_ok 1'0 assign \cr_a_ok \mul_op__write_cr0 sync init end - process $group_13 + process $group_15 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_14 + process $group_16 assign \mul_op__insn_type$2 7'0000000 assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5 1'0 assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__rc__ok$7 1'0 assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__oe__ok$9 1'0 assign \mul_op__write_cr0$10 1'0 assign \mul_op__is_32bit$11 1'0 assign \mul_op__is_signed$12 1'0 assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $39 + wire width 1 \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe - connect \B \mul_op__oe__oe_ok - connect \Y $38 + connect \B \mul_op__oe__ok + connect \Y $39 end - process $group_26 - assign \oe 1'0 - assign \oe $38 + process $group_28 + assign \oe$38 1'0 + assign \oe$38 $39 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62654,53 +63144,43 @@ module \output$97 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $40 - end - process $group_27 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $40 - end - sync init + connect \Y $41 end - process $group_28 + process $group_29 assign \xer_so$18 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$38 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 - assign \xer_so$18 \so + assign \xer_so$18 $41 end sync init end - process $group_29 + process $group_30 assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$38 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_so_ok 1'1 end sync init end - process $group_30 + process $group_31 assign \xer_ov$17 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$38 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_ov$17 \xer_ov end sync init end - process $group_31 + process $group_32 assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch { \oe$38 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" case 1'1 assign \xer_ov_ok 1'1 end @@ -62710,9 +63190,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" module \mul_pipe3 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -62810,17 +63290,17 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__imm + wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__imm_data__imm_ok + wire width 1 input 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__rc__rc_ok + wire width 1 input 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__oe__oe_ok + wire width 1 input 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -62939,29 +63419,29 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \mul_op__imm_data__imm$4 + wire width 64 output 26 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$4$next + wire width 64 \mul_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__imm_data__imm_ok$5 + wire width 1 output 27 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$5$next + wire width 1 \mul_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 28 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__rc__rc_ok$7 + wire width 1 output 29 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$7$next + wire width 1 \mul_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 30 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__oe__oe_ok$9 + wire width 1 output 31 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$9$next + wire width 1 \mul_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 32 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63110,17 +63590,17 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul3_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__imm + wire width 64 \mul3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__imm_data__imm_ok + wire width 1 \mul3_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul3_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__rc__rc_ok + wire width 1 \mul3_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul3_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__oe__oe_ok + wire width 1 \mul3_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63227,17 +63707,17 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul3_mul_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__imm$19 + wire width 64 \mul3_mul_op__imm_data__data$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__imm_data__imm_ok$20 + wire width 1 \mul3_mul_op__imm_data__ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul3_mul_op__rc__rc$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__rc__rc_ok$22 + wire width 1 \mul3_mul_op__rc__ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul3_mul_op__oe__oe$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__oe__oe_ok$24 + wire width 1 \mul3_mul_op__oe__ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul3_mul_op__write_cr0$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63256,16 +63736,18 @@ module \mul_pipe3 wire width 1 \mul3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \mul3_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul3_xer_so_ok cell \mul3 \mul3 connect \muxid \mul3_muxid connect \mul_op__insn_type \mul3_mul_op__insn_type connect \mul_op__fn_unit \mul3_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul3_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok connect \mul_op__rc__rc \mul3_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul3_mul_op__rc__rc_ok + connect \mul_op__rc__ok \mul3_mul_op__rc__ok connect \mul_op__oe__oe \mul3_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul3_mul_op__oe__oe_ok + connect \mul_op__oe__ok \mul3_mul_op__oe__ok connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 connect \mul_op__is_32bit \mul3_mul_op__is_32bit connect \mul_op__is_signed \mul3_mul_op__is_signed @@ -63276,12 +63758,12 @@ module \mul_pipe3 connect \muxid$1 \mul3_muxid$16 connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 - connect \mul_op__imm_data__imm$4 \mul3_mul_op__imm_data__imm$19 - connect \mul_op__imm_data__imm_ok$5 \mul3_mul_op__imm_data__imm_ok$20 + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 - connect \mul_op__rc__rc_ok$7 \mul3_mul_op__rc__rc_ok$22 + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 - connect \mul_op__oe__oe_ok$9 \mul3_mul_op__oe__oe_ok$24 + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 @@ -63291,6 +63773,7 @@ module \mul_pipe3 connect \xer_ov \mul3_xer_ov connect \xer_ov_ok \mul3_xer_ov_ok connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \output_muxid @@ -63384,17 +63867,17 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__imm + wire width 64 \output_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__imm_data__imm_ok + wire width 1 \output_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__rc__rc_ok + wire width 1 \output_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__oe__oe_ok + wire width 1 \output_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63505,17 +63988,17 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_mul_op__fn_unit$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__imm$34 + wire width 64 \output_mul_op__imm_data__data$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__imm_data__imm_ok$35 + wire width 1 \output_mul_op__imm_data__ok$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_mul_op__rc__rc$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__rc__rc_ok$37 + wire width 1 \output_mul_op__rc__ok$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_mul_op__oe__oe$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__oe__oe_ok$39 + wire width 1 \output_mul_op__oe__ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_mul_op__write_cr0$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -63544,12 +64027,12 @@ module \mul_pipe3 connect \muxid \output_muxid connect \mul_op__insn_type \output_mul_op__insn_type connect \mul_op__fn_unit \output_mul_op__fn_unit - connect \mul_op__imm_data__imm \output_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok connect \mul_op__rc__rc \output_mul_op__rc__rc - connect \mul_op__rc__rc_ok \output_mul_op__rc__rc_ok + connect \mul_op__rc__ok \output_mul_op__rc__ok connect \mul_op__oe__oe \output_mul_op__oe__oe - connect \mul_op__oe__oe_ok \output_mul_op__oe__oe_ok + connect \mul_op__oe__ok \output_mul_op__oe__ok connect \mul_op__write_cr0 \output_mul_op__write_cr0 connect \mul_op__is_32bit \output_mul_op__is_32bit connect \mul_op__is_signed \output_mul_op__is_signed @@ -63562,12 +64045,12 @@ module \mul_pipe3 connect \muxid$1 \output_muxid$31 connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 - connect \mul_op__imm_data__imm$4 \output_mul_op__imm_data__imm$34 - connect \mul_op__imm_data__imm_ok$5 \output_mul_op__imm_data__imm_ok$35 + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 - connect \mul_op__rc__rc_ok$7 \output_mul_op__rc__rc_ok$37 + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 - connect \mul_op__oe__oe_ok$9 \output_mul_op__oe__oe_ok$39 + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 @@ -63589,17 +64072,17 @@ module \mul_pipe3 process $group_1 assign \mul3_mul_op__insn_type 7'0000000 assign \mul3_mul_op__fn_unit 11'00000000000 - assign \mul3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul3_mul_op__imm_data__imm_ok 1'0 + assign \mul3_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul3_mul_op__imm_data__ok 1'0 assign \mul3_mul_op__rc__rc 1'0 - assign \mul3_mul_op__rc__rc_ok 1'0 + assign \mul3_mul_op__rc__ok 1'0 assign \mul3_mul_op__oe__oe 1'0 - assign \mul3_mul_op__oe__oe_ok 1'0 + assign \mul3_mul_op__oe__ok 1'0 assign \mul3_mul_op__write_cr0 1'0 assign \mul3_mul_op__is_32bit 1'0 assign \mul3_mul_op__is_signed 1'0 assign \mul3_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 { \mul3_mul_op__oe__oe_ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__rc_ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 { \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end process $group_13 @@ -63632,17 +64115,17 @@ module \mul_pipe3 process $group_18 assign \output_mul_op__insn_type 7'0000000 assign \output_mul_op__fn_unit 11'00000000000 - assign \output_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_mul_op__imm_data__imm_ok 1'0 + assign \output_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_mul_op__imm_data__ok 1'0 assign \output_mul_op__rc__rc 1'0 - assign \output_mul_op__rc__rc_ok 1'0 + assign \output_mul_op__rc__ok 1'0 assign \output_mul_op__oe__oe 1'0 - assign \output_mul_op__oe__oe_ok 1'0 + assign \output_mul_op__oe__ok 1'0 assign \output_mul_op__write_cr0 1'0 assign \output_mul_op__is_32bit 1'0 assign \output_mul_op__is_signed 1'0 assign \output_mul_op__insn 32'00000000000000000000000000000000 - assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 { \output_mul_op__oe__oe_ok \output_mul_op__oe__oe } { \output_mul_op__rc__rc_ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 { \mul3_mul_op__oe__oe_ok$24 \mul3_mul_op__oe__oe$23 } { \mul3_mul_op__rc__rc_ok$22 \mul3_mul_op__rc__rc$21 } { \mul3_mul_op__imm_data__imm_ok$20 \mul3_mul_op__imm_data__imm$19 } \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 { \output_mul_op__oe__ok \output_mul_op__oe__oe } { \output_mul_op__rc__ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__ok \output_mul_op__imm_data__data } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 { \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 } { \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 } { \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 } \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } sync init end process $group_30 @@ -63673,19 +64156,17 @@ module \mul_pipe3 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \xer_so_ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$55 process $group_36 assign \output_xer_so 1'0 assign \xer_so_ok$54 1'0 - assign { \xer_so_ok$54 \output_xer_so } { \xer_so_ok$55 \mul3_xer_so$30 } + assign { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$56 + wire width 1 \p_valid_i$55 process $group_38 - assign \p_valid_i$56 1'0 - assign \p_valid_i$56 \p_valid_i + assign \p_valid_i$55 1'0 + assign \p_valid_i$55 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" @@ -63698,28 +64179,28 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $57 + wire width 1 $56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $58 + cell $and $57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$56 + connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $57 + connect \Y $56 end process $group_40 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $57 + assign \p_valid_i_p_ready_o $56 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$59 + wire width 2 \muxid$58 process $group_41 - assign \muxid$59 2'00 - assign \muxid$59 \output_muxid$31 + assign \muxid$58 2'00 + assign \muxid$58 \output_muxid$31 sync init end attribute \enum_base_type "MicrOp" @@ -63796,7 +64277,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$60 + wire width 7 \mul_op__insn_type$59 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -63810,81 +64291,81 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$61 + wire width 11 \mul_op__fn_unit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$62 + wire width 64 \mul_op__imm_data__data$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$63 + wire width 1 \mul_op__imm_data__ok$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$64 + wire width 1 \mul_op__rc__rc$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$65 + wire width 1 \mul_op__rc__ok$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$66 + wire width 1 \mul_op__oe__oe$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$67 + wire width 1 \mul_op__oe__ok$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$68 + wire width 1 \mul_op__write_cr0$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$69 + wire width 1 \mul_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$70 + wire width 1 \mul_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$71 + wire width 32 \mul_op__insn$70 process $group_42 - assign \mul_op__insn_type$60 7'0000000 - assign \mul_op__fn_unit$61 11'00000000000 - assign \mul_op__imm_data__imm$62 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$63 1'0 - assign \mul_op__rc__rc$64 1'0 - assign \mul_op__rc__rc_ok$65 1'0 - assign \mul_op__oe__oe$66 1'0 - assign \mul_op__oe__oe_ok$67 1'0 - assign \mul_op__write_cr0$68 1'0 - assign \mul_op__is_32bit$69 1'0 - assign \mul_op__is_signed$70 1'0 - assign \mul_op__insn$71 32'00000000000000000000000000000000 - assign { \mul_op__insn$71 \mul_op__is_signed$70 \mul_op__is_32bit$69 \mul_op__write_cr0$68 { \mul_op__oe__oe_ok$67 \mul_op__oe__oe$66 } { \mul_op__rc__rc_ok$65 \mul_op__rc__rc$64 } { \mul_op__imm_data__imm_ok$63 \mul_op__imm_data__imm$62 } \mul_op__fn_unit$61 \mul_op__insn_type$60 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 { \output_mul_op__oe__oe_ok$39 \output_mul_op__oe__oe$38 } { \output_mul_op__rc__rc_ok$37 \output_mul_op__rc__rc$36 } { \output_mul_op__imm_data__imm_ok$35 \output_mul_op__imm_data__imm$34 } \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + assign \mul_op__insn_type$59 7'0000000 + assign \mul_op__fn_unit$60 11'00000000000 + assign \mul_op__imm_data__data$61 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$62 1'0 + assign \mul_op__rc__rc$63 1'0 + assign \mul_op__rc__ok$64 1'0 + assign \mul_op__oe__oe$65 1'0 + assign \mul_op__oe__ok$66 1'0 + assign \mul_op__write_cr0$67 1'0 + assign \mul_op__is_32bit$68 1'0 + assign \mul_op__is_signed$69 1'0 + assign \mul_op__insn$70 32'00000000000000000000000000000000 + assign { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 { \mul_op__oe__ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 { \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 } { \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 } { \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 } \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$72 + wire width 64 \o$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$73 + wire width 1 \o_ok$72 process $group_54 - assign \o$72 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$73 1'0 - assign { \o_ok$73 \o$72 } { \output_o_ok$45 \output_o$44 } + assign \o$71 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$72 1'0 + assign { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$74 + wire width 4 \cr_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$75 + wire width 1 \cr_a_ok$74 process $group_56 - assign \cr_a$74 4'0000 - assign \cr_a_ok$75 1'0 - assign { \cr_a_ok$75 \cr_a$74 } { \output_cr_a_ok \output_cr_a$46 } + assign \cr_a$73 4'0000 + assign \cr_a_ok$74 1'0 + assign { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$76 + wire width 2 \xer_ov$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$77 + wire width 1 \xer_ov_ok$76 process $group_58 - assign \xer_ov$76 2'00 - assign \xer_ov_ok$77 1'0 - assign { \xer_ov_ok$77 \xer_ov$76 } { \output_xer_ov_ok \output_xer_ov$47 } + assign \xer_ov$75 2'00 + assign \xer_ov_ok$76 1'0 + assign { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$78 + wire width 1 \xer_so$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$79 + wire width 1 \xer_so_ok$78 process $group_60 - assign \xer_so$78 1'0 - assign \xer_so_ok$79 1'0 - assign { \xer_so_ok$79 \xer_so$78 } { \output_xer_so_ok \output_xer_so$48 } + assign \xer_so$77 1'0 + assign \xer_so_ok$78 1'0 + assign { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" @@ -63918,10 +64399,10 @@ module \mul_pipe3 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$59 + assign \muxid$1$next \muxid$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$59 + assign \muxid$1$next \muxid$58 end sync init update \muxid$1 2'00 @@ -63931,12 +64412,12 @@ module \mul_pipe3 process $group_64 assign \mul_op__insn_type$2$next \mul_op__insn_type$2 assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 - assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4 - assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5 + assign \mul_op__imm_data__data$4$next \mul_op__imm_data__data$4 + assign \mul_op__imm_data__ok$5$next \mul_op__imm_data__ok$5 assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 - assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7 + assign \mul_op__rc__ok$7$next \mul_op__rc__ok$7 assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 - assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9 + assign \mul_op__oe__ok$9$next \mul_op__oe__ok$9 assign \mul_op__write_cr0$10$next \mul_op__write_cr0$10 assign \mul_op__is_32bit$11$next \mul_op__is_32bit$11 assign \mul_op__is_signed$12$next \mul_op__is_signed$12 @@ -63945,30 +64426,30 @@ module \mul_pipe3 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$71 \mul_op__is_signed$70 \mul_op__is_32bit$69 \mul_op__write_cr0$68 { \mul_op__oe__oe_ok$67 \mul_op__oe__oe$66 } { \mul_op__rc__rc_ok$65 \mul_op__rc__rc$64 } { \mul_op__imm_data__imm_ok$63 \mul_op__imm_data__imm$62 } \mul_op__fn_unit$61 \mul_op__insn_type$60 } + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 { \mul_op__oe__ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$71 \mul_op__is_signed$70 \mul_op__is_32bit$69 \mul_op__write_cr0$68 { \mul_op__oe__oe_ok$67 \mul_op__oe__oe$66 } { \mul_op__rc__rc_ok$65 \mul_op__rc__rc$64 } { \mul_op__imm_data__imm_ok$63 \mul_op__imm_data__imm$62 } \mul_op__fn_unit$61 \mul_op__insn_type$60 } + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 { \mul_op__oe__ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5$next 1'0 + assign \mul_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$5$next 1'0 assign \mul_op__rc__rc$6$next 1'0 - assign \mul_op__rc__rc_ok$7$next 1'0 + assign \mul_op__rc__ok$7$next 1'0 assign \mul_op__oe__oe$8$next 1'0 - assign \mul_op__oe__oe_ok$9$next 1'0 + assign \mul_op__oe__ok$9$next 1'0 end sync init update \mul_op__insn_type$2 7'0000000 update \mul_op__fn_unit$3 11'00000000000 - update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__imm_ok$5 1'0 + update \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \mul_op__imm_data__ok$5 1'0 update \mul_op__rc__rc$6 1'0 - update \mul_op__rc__rc_ok$7 1'0 + update \mul_op__rc__ok$7 1'0 update \mul_op__oe__oe$8 1'0 - update \mul_op__oe__oe_ok$9 1'0 + update \mul_op__oe__ok$9 1'0 update \mul_op__write_cr0$10 1'0 update \mul_op__is_32bit$11 1'0 update \mul_op__is_signed$12 1'0 @@ -63976,12 +64457,12 @@ module \mul_pipe3 sync posedge \coresync_clk update \mul_op__insn_type$2 \mul_op__insn_type$2$next update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next - update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next - update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next + update \mul_op__imm_data__data$4 \mul_op__imm_data__data$4$next + update \mul_op__imm_data__ok$5 \mul_op__imm_data__ok$5$next update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next - update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next + update \mul_op__rc__ok$7 \mul_op__rc__ok$7$next update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next - update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next + update \mul_op__oe__ok$9 \mul_op__oe__ok$9$next update \mul_op__write_cr0$10 \mul_op__write_cr0$10$next update \mul_op__is_32bit$11 \mul_op__is_32bit$11$next update \mul_op__is_signed$12 \mul_op__is_signed$12$next @@ -63994,10 +64475,10 @@ module \mul_pipe3 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$next \o$14$next } { \o_ok$73 \o$72 } + assign { \o_ok$next \o$14$next } { \o_ok$72 \o$71 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$next \o$14$next } { \o_ok$73 \o$72 } + assign { \o_ok$next \o$14$next } { \o_ok$72 \o$71 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -64018,10 +64499,10 @@ module \mul_pipe3 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$75 \cr_a$74 } + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$74 \cr_a$73 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$75 \cr_a$74 } + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$74 \cr_a$73 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -64042,10 +64523,10 @@ module \mul_pipe3 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$77 \xer_ov$76 } + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$77 \xer_ov$76 } + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$76 \xer_ov$75 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -64066,10 +64547,10 @@ module \mul_pipe3 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$79 \xer_so$78 } + assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$78 \xer_so$77 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$79 \xer_so$78 } + assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$78 \xer_so$77 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -64095,12 +64576,11 @@ module \mul_pipe3 end connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 - connect \xer_so_ok$55 1'0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" module \alu_mul0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -64110,7 +64590,7 @@ module \alu_mul0 wire width 1 output 3 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 4 \xer_so_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 5 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 6 \n_valid_o @@ -64206,17 +64686,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 9 \mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \mul_op__imm_data__imm + wire width 64 input 10 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__imm_data__imm_ok + wire width 1 input 11 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 12 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__rc__rc_ok + wire width 1 input 13 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 14 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \mul_op__oe__oe_ok + wire width 1 input 15 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 16 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64347,17 +64827,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_pipe1_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__imm + wire width 64 \mul_pipe1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok + wire width 1 \mul_pipe1_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe1_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc_ok + wire width 1 \mul_pipe1_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe1_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe_ok + wire width 1 \mul_pipe1_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe1_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64472,17 +64952,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_pipe1_mul_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__imm$5 + wire width 64 \mul_pipe1_mul_op__imm_data__data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok$6 + wire width 1 \mul_pipe1_mul_op__imm_data__ok$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe1_mul_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc_ok$8 + wire width 1 \mul_pipe1_mul_op__rc__ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe1_mul_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe_ok$10 + wire width 1 \mul_pipe1_mul_op__oe__ok$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe1_mul_op__write_cr0$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64505,12 +64985,12 @@ module \alu_mul0 connect \muxid \mul_pipe1_muxid connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul_pipe1_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data + connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc_ok + connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe_ok + connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed @@ -64525,12 +65005,12 @@ module \alu_mul0 connect \muxid$1 \mul_pipe1_muxid$2 connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 - connect \mul_op__imm_data__imm$4 \mul_pipe1_mul_op__imm_data__imm$5 - connect \mul_op__imm_data__imm_ok$5 \mul_pipe1_mul_op__imm_data__imm_ok$6 + connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 + connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 - connect \mul_op__rc__rc_ok$7 \mul_pipe1_mul_op__rc__rc_ok$8 + connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 - connect \mul_op__oe__oe_ok$9 \mul_pipe1_mul_op__oe__oe_ok$10 + connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 @@ -64635,17 +65115,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_pipe2_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__imm + wire width 64 \mul_pipe2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok + wire width 1 \mul_pipe2_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe2_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc_ok + wire width 1 \mul_pipe2_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe2_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe_ok + wire width 1 \mul_pipe2_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe2_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64760,17 +65240,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_pipe2_mul_op__fn_unit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__imm$21 + wire width 64 \mul_pipe2_mul_op__imm_data__data$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok$22 + wire width 1 \mul_pipe2_mul_op__imm_data__ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe2_mul_op__rc__rc$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc_ok$24 + wire width 1 \mul_pipe2_mul_op__rc__ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe2_mul_op__oe__oe$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe_ok$26 + wire width 1 \mul_pipe2_mul_op__oe__ok$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe2_mul_op__write_cr0$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64795,12 +65275,12 @@ module \alu_mul0 connect \muxid \mul_pipe2_muxid connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul_pipe2_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data + connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc_ok + connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe_ok + connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed @@ -64815,12 +65295,12 @@ module \alu_mul0 connect \muxid$1 \mul_pipe2_muxid$18 connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 - connect \mul_op__imm_data__imm$4 \mul_pipe2_mul_op__imm_data__imm$21 - connect \mul_op__imm_data__imm_ok$5 \mul_pipe2_mul_op__imm_data__imm_ok$22 + connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 + connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 - connect \mul_op__rc__rc_ok$7 \mul_pipe2_mul_op__rc__rc_ok$24 + connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 - connect \mul_op__oe__oe_ok$9 \mul_pipe2_mul_op__oe__oe_ok$26 + connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 @@ -64926,17 +65406,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_pipe3_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__imm + wire width 64 \mul_pipe3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok + wire width 1 \mul_pipe3_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe3_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc_ok + wire width 1 \mul_pipe3_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe3_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe_ok + wire width 1 \mul_pipe3_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -65049,17 +65529,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_pipe3_mul_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__imm$37 + wire width 64 \mul_pipe3_mul_op__imm_data__data$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok$38 + wire width 1 \mul_pipe3_mul_op__imm_data__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe3_mul_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc_ok$40 + wire width 1 \mul_pipe3_mul_op__rc__ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe3_mul_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe_ok$42 + wire width 1 \mul_pipe3_mul_op__oe__ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_pipe3_mul_op__write_cr0$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -65092,12 +65572,12 @@ module \alu_mul0 connect \muxid \mul_pipe3_muxid connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul_pipe3_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data + connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc_ok + connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe_ok + connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed @@ -65111,12 +65591,12 @@ module \alu_mul0 connect \muxid$1 \mul_pipe3_muxid$34 connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 - connect \mul_op__imm_data__imm$4 \mul_pipe3_mul_op__imm_data__imm$37 - connect \mul_op__imm_data__imm_ok$5 \mul_pipe3_mul_op__imm_data__imm_ok$38 + connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 + connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 - connect \mul_op__rc__rc_ok$7 \mul_pipe3_mul_op__rc__rc_ok$40 + connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 - connect \mul_op__oe__oe_ok$9 \mul_pipe3_mul_op__oe__oe_ok$42 + connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 @@ -65148,17 +65628,17 @@ module \alu_mul0 process $group_3 assign \mul_pipe2_mul_op__insn_type 7'0000000 assign \mul_pipe2_mul_op__fn_unit 11'00000000000 - assign \mul_pipe2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_mul_op__imm_data__imm_ok 1'0 + assign \mul_pipe2_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe2_mul_op__imm_data__ok 1'0 assign \mul_pipe2_mul_op__rc__rc 1'0 - assign \mul_pipe2_mul_op__rc__rc_ok 1'0 + assign \mul_pipe2_mul_op__rc__ok 1'0 assign \mul_pipe2_mul_op__oe__oe 1'0 - assign \mul_pipe2_mul_op__oe__oe_ok 1'0 + assign \mul_pipe2_mul_op__oe__ok 1'0 assign \mul_pipe2_mul_op__write_cr0 1'0 assign \mul_pipe2_mul_op__is_32bit 1'0 assign \mul_pipe2_mul_op__is_signed 1'0 assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 { \mul_pipe2_mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 { \mul_pipe1_mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 { \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 { \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } sync init end process $group_15 @@ -65204,17 +65684,17 @@ module \alu_mul0 process $group_23 assign \mul_pipe3_mul_op__insn_type 7'0000000 assign \mul_pipe3_mul_op__fn_unit 11'00000000000 - assign \mul_pipe3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe3_mul_op__imm_data__imm_ok 1'0 + assign \mul_pipe3_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe3_mul_op__imm_data__ok 1'0 assign \mul_pipe3_mul_op__rc__rc 1'0 - assign \mul_pipe3_mul_op__rc__rc_ok 1'0 + assign \mul_pipe3_mul_op__rc__ok 1'0 assign \mul_pipe3_mul_op__oe__oe 1'0 - assign \mul_pipe3_mul_op__oe__oe_ok 1'0 + assign \mul_pipe3_mul_op__oe__ok 1'0 assign \mul_pipe3_mul_op__write_cr0 1'0 assign \mul_pipe3_mul_op__is_32bit 1'0 assign \mul_pipe3_mul_op__is_signed 1'0 assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 { \mul_pipe3_mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 { \mul_pipe2_mul_op__oe__oe_ok$26 \mul_pipe2_mul_op__oe__oe$25 } { \mul_pipe2_mul_op__rc__rc_ok$24 \mul_pipe2_mul_op__rc__rc$23 } { \mul_pipe2_mul_op__imm_data__imm_ok$22 \mul_pipe2_mul_op__imm_data__imm$21 } \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 { \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 { \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 } { \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 } { \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 } \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } sync init end process $group_35 @@ -65257,17 +65737,17 @@ module \alu_mul0 process $group_42 assign \mul_pipe1_mul_op__insn_type$3 7'0000000 assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000 - assign \mul_pipe1_mul_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_mul_op__imm_data__imm_ok$6 1'0 + assign \mul_pipe1_mul_op__imm_data__data$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe1_mul_op__imm_data__ok$6 1'0 assign \mul_pipe1_mul_op__rc__rc$7 1'0 - assign \mul_pipe1_mul_op__rc__rc_ok$8 1'0 + assign \mul_pipe1_mul_op__rc__ok$8 1'0 assign \mul_pipe1_mul_op__oe__oe$9 1'0 - assign \mul_pipe1_mul_op__oe__oe_ok$10 1'0 + assign \mul_pipe1_mul_op__oe__ok$10 1'0 assign \mul_pipe1_mul_op__write_cr0$11 1'0 assign \mul_pipe1_mul_op__is_32bit$12 1'0 assign \mul_pipe1_mul_op__is_signed$13 1'0 assign \mul_pipe1_mul_op__insn$14 32'00000000000000000000000000000000 - assign { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 { \mul_pipe1_mul_op__oe__oe_ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__rc_ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__imm_ok$6 \mul_pipe1_mul_op__imm_data__imm$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 { \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } sync init end process $group_54 @@ -65392,17 +65872,17 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \mul_op__fn_unit$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$52 + wire width 64 \mul_op__imm_data__data$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$53 + wire width 1 \mul_op__imm_data__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__rc__rc$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$55 + wire width 1 \mul_op__rc__ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__oe__oe$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$57 + wire width 1 \mul_op__oe__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \mul_op__write_cr0$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -65414,17 +65894,17 @@ module \alu_mul0 process $group_60 assign \mul_op__insn_type$50 7'0000000 assign \mul_op__fn_unit$51 11'00000000000 - assign \mul_op__imm_data__imm$52 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$53 1'0 + assign \mul_op__imm_data__data$52 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__ok$53 1'0 assign \mul_op__rc__rc$54 1'0 - assign \mul_op__rc__rc_ok$55 1'0 + assign \mul_op__rc__ok$55 1'0 assign \mul_op__oe__oe$56 1'0 - assign \mul_op__oe__oe_ok$57 1'0 + assign \mul_op__oe__ok$57 1'0 assign \mul_op__write_cr0$58 1'0 assign \mul_op__is_32bit$59 1'0 assign \mul_op__is_signed$60 1'0 assign \mul_op__insn$61 32'00000000000000000000000000000000 - assign { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 { \mul_op__oe__oe_ok$57 \mul_op__oe__oe$56 } { \mul_op__rc__rc_ok$55 \mul_op__rc__rc$54 } { \mul_op__imm_data__imm_ok$53 \mul_op__imm_data__imm$52 } \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 { \mul_pipe3_mul_op__oe__oe_ok$42 \mul_pipe3_mul_op__oe__oe$41 } { \mul_pipe3_mul_op__rc__rc_ok$40 \mul_pipe3_mul_op__rc__rc$39 } { \mul_pipe3_mul_op__imm_data__imm_ok$38 \mul_pipe3_mul_op__imm_data__imm$37 } \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + assign { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 { \mul_op__oe__ok$57 \mul_op__oe__oe$56 } { \mul_op__rc__ok$55 \mul_op__rc__rc$54 } { \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 } \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 { \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 } { \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 } { \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 } \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } sync init end process $group_72 @@ -65456,9 +65936,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" module \src_l$98 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src @@ -65601,9 +66081,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" module \opc_l$99 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -65746,9 +66226,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" module \req_l$100 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 output 2 \q_req @@ -65891,9 +66371,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" module \rst_l$101 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -66036,9 +66516,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" module \rok_l$102 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -66181,9 +66661,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" module \alui_l$103 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -66326,9 +66806,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" module \alu_l$104 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -66471,7 +66951,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" module \mul0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -66563,17 +67043,17 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_mul0__imm_data__imm + wire width 64 input 3 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_mul0__imm_data__imm_ok + wire width 1 input 4 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_mul0__rc__rc_ok + wire width 1 input 6 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_mul0__oe__oe_ok + wire width 1 input 8 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \oper_i_alu_mul0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -66618,7 +67098,7 @@ module \mul0 wire width 1 output 29 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 1 output 30 \dest4_o - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 31 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_mul0_n_valid_o @@ -66718,29 +67198,29 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_mul0_mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__imm + wire width 64 \alu_mul0_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__imm$next + wire width 64 \alu_mul0_mul_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__imm_data__imm_ok + wire width 1 \alu_mul0_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__imm_data__imm_ok$next + wire width 1 \alu_mul0_mul_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_mul0_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_mul0_mul_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__rc_ok + wire width 1 \alu_mul0_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__rc_ok$next + wire width 1 \alu_mul0_mul_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_mul0_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_mul0_mul_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__oe_ok + wire width 1 \alu_mul0_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__oe_ok$next + wire width 1 \alu_mul0_mul_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_mul0_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -66786,12 +67266,12 @@ module \mul0 connect \n_ready_i \alu_mul0_n_ready_i connect \mul_op__insn_type \alu_mul0_mul_op__insn_type connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit - connect \mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc - connect \mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe - connect \mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit connect \mul_op__is_signed \alu_mul0_mul_op__is_signed @@ -67612,12 +68092,12 @@ module \mul0 process $group_27 assign \alu_mul0_mul_op__insn_type$next \alu_mul0_mul_op__insn_type assign \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__fn_unit - assign \alu_mul0_mul_op__imm_data__imm$next \alu_mul0_mul_op__imm_data__imm - assign \alu_mul0_mul_op__imm_data__imm_ok$next \alu_mul0_mul_op__imm_data__imm_ok + assign \alu_mul0_mul_op__imm_data__data$next \alu_mul0_mul_op__imm_data__data + assign \alu_mul0_mul_op__imm_data__ok$next \alu_mul0_mul_op__imm_data__ok assign \alu_mul0_mul_op__rc__rc$next \alu_mul0_mul_op__rc__rc - assign \alu_mul0_mul_op__rc__rc_ok$next \alu_mul0_mul_op__rc__rc_ok + assign \alu_mul0_mul_op__rc__ok$next \alu_mul0_mul_op__rc__ok assign \alu_mul0_mul_op__oe__oe$next \alu_mul0_mul_op__oe__oe - assign \alu_mul0_mul_op__oe__oe_ok$next \alu_mul0_mul_op__oe__oe_ok + assign \alu_mul0_mul_op__oe__ok$next \alu_mul0_mul_op__oe__ok assign \alu_mul0_mul_op__write_cr0$next \alu_mul0_mul_op__write_cr0 assign \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__is_32bit assign \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_signed @@ -67626,27 +68106,27 @@ module \mul0 switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_mul0_mul_op__insn$next \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__write_cr0$next { \alu_mul0_mul_op__oe__oe_ok$next \alu_mul0_mul_op__oe__oe$next } { \alu_mul0_mul_op__rc__rc_ok$next \alu_mul0_mul_op__rc__rc$next } { \alu_mul0_mul_op__imm_data__imm_ok$next \alu_mul0_mul_op__imm_data__imm$next } \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { \alu_mul0_mul_op__insn$next \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__write_cr0$next { \alu_mul0_mul_op__oe__ok$next \alu_mul0_mul_op__oe__oe$next } { \alu_mul0_mul_op__rc__ok$next \alu_mul0_mul_op__rc__rc$next } { \alu_mul0_mul_op__imm_data__ok$next \alu_mul0_mul_op__imm_data__data$next } \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 { \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_mul0_mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_mul_op__imm_data__imm_ok$next 1'0 + assign \alu_mul0_mul_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_mul0_mul_op__imm_data__ok$next 1'0 assign \alu_mul0_mul_op__rc__rc$next 1'0 - assign \alu_mul0_mul_op__rc__rc_ok$next 1'0 + assign \alu_mul0_mul_op__rc__ok$next 1'0 assign \alu_mul0_mul_op__oe__oe$next 1'0 - assign \alu_mul0_mul_op__oe__oe_ok$next 1'0 + assign \alu_mul0_mul_op__oe__ok$next 1'0 end sync init update \alu_mul0_mul_op__insn_type 7'0000000 update \alu_mul0_mul_op__fn_unit 11'00000000000 - update \alu_mul0_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_mul0_mul_op__imm_data__imm_ok 1'0 + update \alu_mul0_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_mul0_mul_op__imm_data__ok 1'0 update \alu_mul0_mul_op__rc__rc 1'0 - update \alu_mul0_mul_op__rc__rc_ok 1'0 + update \alu_mul0_mul_op__rc__ok 1'0 update \alu_mul0_mul_op__oe__oe 1'0 - update \alu_mul0_mul_op__oe__oe_ok 1'0 + update \alu_mul0_mul_op__oe__ok 1'0 update \alu_mul0_mul_op__write_cr0 1'0 update \alu_mul0_mul_op__is_32bit 1'0 update \alu_mul0_mul_op__is_signed 1'0 @@ -67654,12 +68134,12 @@ module \mul0 sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type \alu_mul0_mul_op__insn_type$next update \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__fn_unit$next - update \alu_mul0_mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm$next - update \alu_mul0_mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok$next + update \alu_mul0_mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data$next + update \alu_mul0_mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok$next update \alu_mul0_mul_op__rc__rc \alu_mul0_mul_op__rc__rc$next - update \alu_mul0_mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok$next + update \alu_mul0_mul_op__rc__ok \alu_mul0_mul_op__rc__ok$next update \alu_mul0_mul_op__oe__oe \alu_mul0_mul_op__oe__oe$next - update \alu_mul0_mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok$next + update \alu_mul0_mul_op__oe__ok \alu_mul0_mul_op__oe__ok$next update \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__write_cr0$next update \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__is_32bit$next update \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_signed$next @@ -67871,7 +68351,7 @@ module \mul0 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc - connect \S \alu_mul0_mul_op__imm_data__imm_ok + connect \S \alu_mul0_mul_op__imm_data__ok connect \Y $78 end process $group_48 @@ -67887,8 +68367,8 @@ module \mul0 cell $mux $81 parameter \WIDTH 64 connect \A \src2_i - connect \B \alu_mul0_mul_op__imm_data__imm - connect \S \alu_mul0_mul_op__imm_data__imm_ok + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok connect \Y $80 end process $group_49 @@ -68089,7 +68569,7 @@ module \mul0 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_mul0_mul_op__imm_data__imm_ok + connect \A \alu_mul0_mul_op__imm_data__ok connect \Y $94 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -68520,17 +69000,19 @@ module \input$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__imm + wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__imm_ok + wire width 1 input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__rc_ok + wire width 1 input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__oe_ok + wire width 1 input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -68556,9 +69038,11 @@ module \input$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 20 \xer_ca + wire width 1 input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 21 \xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 22 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -68633,7 +69117,7 @@ module \input$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \sr_op__insn_type$2 + wire width 7 output 23 \sr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -68647,45 +69131,49 @@ module \input$110 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \sr_op__fn_unit$3 + wire width 11 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \sr_op__imm_data__imm$4 + wire width 64 output 25 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \sr_op__imm_data__imm_ok$5 + wire width 1 output 26 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \sr_op__rc__rc$6 + wire width 1 output 27 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \sr_op__rc__rc_ok$7 + wire width 1 output 28 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \sr_op__oe__oe$8 + wire width 1 output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \sr_op__oe__oe_ok$9 + wire width 1 output 31 \sr_op__write_cr0$10 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$10 + wire width 2 output 32 \sr_op__input_carry$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__output_carry$11 + wire width 1 output 33 \sr_op__output_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__input_cr$12 + wire width 1 output 34 \sr_op__input_cr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__output_cr$13 + wire width 1 output 35 \sr_op__output_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_32bit$14 + wire width 1 output 36 \sr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \sr_op__is_signed$15 + wire width 1 output 37 \sr_op__is_signed$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 \sr_op__insn$16 + wire width 32 output 38 \sr_op__insn$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 38 \ra$17 + wire width 64 output 39 \ra$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 39 \rb$18 + wire width 64 output 40 \rb$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 40 \rc$19 + wire width 64 output 41 \rc$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 41 \xer_ca$20 + wire width 1 output 42 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 43 \xer_ca$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a process $group_0 @@ -68694,8 +69182,8 @@ module \input$110 sync init end process $group_1 - assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$17 \a + assign \ra$18 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$18 \a sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" @@ -68706,57 +69194,62 @@ module \input$110 sync init end process $group_3 - assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$18 \b + assign \rb$19 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$19 \b sync init end process $group_4 - assign \xer_ca$20 2'00 + assign \xer_ca$22 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" switch \sr_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" attribute \nmigen.decoding "ZERO/0" case 2'00 - assign \xer_ca$20 2'00 + assign \xer_ca$22 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" attribute \nmigen.decoding "ONE/1" case 2'01 - assign \xer_ca$20 2'11 + assign \xer_ca$22 2'11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" attribute \nmigen.decoding "CA/2" case 2'10 - assign \xer_ca$20 \xer_ca + assign \xer_ca$22 \xer_ca end sync init end process $group_5 + assign \xer_so$21 1'0 + assign \xer_so$21 \xer_so + sync init + end + process $group_6 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_6 + process $group_7 assign \sr_op__insn_type$2 7'0000000 assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5 1'0 + assign \sr_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$5 1'0 assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__rc_ok$7 1'0 + assign \sr_op__rc__ok$7 1'0 assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__oe_ok$9 1'0 - assign { } 0'0 - assign \sr_op__input_carry$10 2'00 - assign \sr_op__output_carry$11 1'0 - assign \sr_op__input_cr$12 1'0 - assign \sr_op__output_cr$13 1'0 - assign \sr_op__is_32bit$14 1'0 - assign \sr_op__is_signed$15 1'0 - assign \sr_op__insn$16 32'00000000000000000000000000000000 - assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + assign \sr_op__oe__ok$9 1'0 + assign \sr_op__write_cr0$10 1'0 + assign \sr_op__input_carry$11 2'00 + assign \sr_op__output_carry$12 1'0 + assign \sr_op__input_cr$13 1'0 + assign \sr_op__output_cr$14 1'0 + assign \sr_op__is_32bit$15 1'0 + assign \sr_op__is_signed$16 1'0 + assign \sr_op__insn$17 32'00000000000000000000000000000000 + assign { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 { \sr_op__oe__ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } sync init end - process $group_22 - assign \rc$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rc$19 \rc + process $group_23 + assign \rc$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rc$20 \rc sync init end end @@ -72086,17 +72579,19 @@ module \main$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__imm + wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__imm_ok + wire width 1 input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__rc_ok + wire width 1 input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__oe_ok + wire width 1 input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -72121,8 +72616,10 @@ module \main$111 wire width 64 input 18 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 20 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 20 \muxid$1 + wire width 2 output 21 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -72197,7 +72694,7 @@ module \main$111 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 21 \sr_op__insn_type$2 + wire width 7 output 22 \sr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -72211,43 +72708,47 @@ module \main$111 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 22 \sr_op__fn_unit$3 + wire width 11 output 23 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \sr_op__imm_data__imm$4 + wire width 64 output 24 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \sr_op__imm_data__imm_ok$5 + wire width 1 output 25 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \sr_op__rc__rc$6 + wire width 1 output 26 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \sr_op__rc__rc_ok$7 + wire width 1 output 27 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \sr_op__oe__oe$8 + wire width 1 output 28 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \sr_op__oe__oe_ok$9 + wire width 1 output 29 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \sr_op__write_cr0$10 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 30 \sr_op__input_carry$10 + wire width 2 output 31 \sr_op__input_carry$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \sr_op__output_carry$11 + wire width 1 output 32 \sr_op__output_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__input_cr$12 + wire width 1 output 33 \sr_op__input_cr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__output_cr$13 + wire width 1 output 34 \sr_op__output_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__is_32bit$14 + wire width 1 output 35 \sr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_signed$15 + wire width 1 output 36 \sr_op__is_signed$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 36 \sr_op__insn$16 + wire width 32 output 37 \sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 38 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 37 \o + wire width 1 output 39 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 38 \o_ok + wire width 1 output 40 \xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 39 \xer_ca + wire width 2 output 41 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" wire width 5 \rotator_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" @@ -72438,37 +72939,42 @@ module \main$111 sync init end process $group_19 + assign \xer_so$18 1'0 + assign \xer_so$18 \xer_so + sync init + end + process $group_20 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_20 + process $group_21 assign \sr_op__insn_type$2 7'0000000 assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5 1'0 + assign \sr_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$5 1'0 assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__rc_ok$7 1'0 + assign \sr_op__rc__ok$7 1'0 assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__oe_ok$9 1'0 - assign { } 0'0 - assign \sr_op__input_carry$10 2'00 - assign \sr_op__output_carry$11 1'0 - assign \sr_op__input_cr$12 1'0 - assign \sr_op__output_cr$13 1'0 - assign \sr_op__is_32bit$14 1'0 - assign \sr_op__is_signed$15 1'0 - assign \sr_op__insn$16 32'00000000000000000000000000000000 - assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + assign \sr_op__oe__ok$9 1'0 + assign \sr_op__write_cr0$10 1'0 + assign \sr_op__input_carry$11 2'00 + assign \sr_op__output_carry$12 1'0 + assign \sr_op__input_cr$13 1'0 + assign \sr_op__output_cr$14 1'0 + assign \sr_op__is_32bit$15 1'0 + assign \sr_op__is_signed$16 1'0 + assign \sr_op__insn$17 32'00000000000000000000000000000000 + assign { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 { \sr_op__oe__ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" module \pipe1$107 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 2 \n_valid_o @@ -72572,29 +73078,33 @@ module \pipe1$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \sr_op__imm_data__imm + wire width 64 output 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$next + wire width 64 \sr_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \sr_op__imm_data__imm_ok + wire width 1 output 8 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$next + wire width 1 \sr_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 9 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \sr_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \sr_op__rc__rc_ok + wire width 1 output 10 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$next + wire width 1 \sr_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 output 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \sr_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \sr_op__oe__oe_ok + wire width 1 output 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$next + wire width 1 output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__write_cr0$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -72644,19 +73154,27 @@ module \pipe1$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 25 \xer_ca + wire width 1 output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 26 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 2 \xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \xer_ca_ok + wire width 1 output 28 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 27 \p_valid_i + wire width 1 input 29 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 28 \p_ready_o + wire width 1 output 30 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 29 \muxid$1 + wire width 2 input 31 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -72731,7 +73249,7 @@ module \pipe1$107 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 30 \sr_op__insn_type$2 + wire width 7 input 32 \sr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -72745,45 +73263,49 @@ module \pipe1$107 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 31 \sr_op__fn_unit$3 + wire width 11 input 33 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 32 \sr_op__imm_data__imm$4 + wire width 64 input 34 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 33 \sr_op__imm_data__imm_ok$5 + wire width 1 input 35 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 34 \sr_op__rc__rc$6 + wire width 1 input 36 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 35 \sr_op__rc__rc_ok$7 + wire width 1 input 37 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 36 \sr_op__oe__oe$8 + wire width 1 input 38 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 37 \sr_op__oe__oe_ok$9 + wire width 1 input 39 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 40 \sr_op__write_cr0$10 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 39 \sr_op__input_carry$10 + wire width 2 input 41 \sr_op__input_carry$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 40 \sr_op__output_carry$11 + wire width 1 input 42 \sr_op__output_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 41 \sr_op__input_cr$12 + wire width 1 input 43 \sr_op__input_cr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 42 \sr_op__output_cr$13 + wire width 1 input 44 \sr_op__output_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 43 \sr_op__is_32bit$14 + wire width 1 input 45 \sr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 44 \sr_op__is_signed$15 + wire width 1 input 46 \sr_op__is_signed$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 45 \sr_op__insn$16 + wire width 32 input 47 \sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 48 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 46 \ra + wire width 64 input 49 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 47 \rb + wire width 64 input 50 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 48 \rc + wire width 1 input 51 \xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 49 \xer_ca$17 + wire width 2 input 52 \xer_ca$19 cell \p$108 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -72884,17 +73406,19 @@ module \pipe1$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \input_sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__imm + wire width 64 \input_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__imm_data__imm_ok + wire width 1 \input_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc_ok + wire width 1 \input_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \input_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe_ok + wire width 1 \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -72920,9 +73444,11 @@ module \pipe1$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \input_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$18 + wire width 2 \input_muxid$20 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -72997,7 +73523,7 @@ module \pipe1$107 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type$19 + wire width 7 \input_sr_op__insn_type$21 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -73011,55 +73537,60 @@ module \pipe1$107 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_sr_op__fn_unit$20 + wire width 11 \input_sr_op__fn_unit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__imm$21 + wire width 1 \input_sr_op__imm_data__ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__imm_data__imm_ok$22 + wire width 1 \input_sr_op__rc__rc$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc$23 + wire width 1 \input_sr_op__rc__ok$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc_ok$24 + wire width 1 \input_sr_op__oe__oe$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe$25 + wire width 1 \input_sr_op__oe__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe_ok$26 + wire width 1 \input_sr_op__write_cr0$29 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry$27 + wire width 2 \input_sr_op__input_carry$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__output_carry$28 + wire width 1 \input_sr_op__output_carry$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__input_cr$29 + wire width 1 \input_sr_op__input_cr$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__output_cr$30 + wire width 1 \input_sr_op__output_cr$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__is_32bit$31 + wire width 1 \input_sr_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__is_signed$32 + wire width 1 \input_sr_op__is_signed$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn$33 + wire width 32 \input_sr_op__insn$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$34 + wire width 64 \input_ra$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$35 + wire width 64 \input_rb$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc$36 + wire width 64 \input_rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$37 + wire width 1 \input_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$41 cell \input$110 \input connect \muxid \input_muxid connect \sr_op__insn_type \input_sr_op__insn_type connect \sr_op__fn_unit \input_sr_op__fn_unit - connect \sr_op__imm_data__imm \input_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm_ok + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok connect \sr_op__rc__rc \input_sr_op__rc__rc - connect \sr_op__rc__rc_ok \input_sr_op__rc__rc_ok + connect \sr_op__rc__ok \input_sr_op__rc__ok connect \sr_op__oe__oe \input_sr_op__oe__oe - connect \sr_op__oe__oe_ok \input_sr_op__oe__oe_ok + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__write_cr0 \input_sr_op__write_cr0 connect \sr_op__input_carry \input_sr_op__input_carry connect \sr_op__output_carry \input_sr_op__output_carry connect \sr_op__input_cr \input_sr_op__input_cr @@ -73070,27 +73601,30 @@ module \pipe1$107 connect \ra \input_ra connect \rb \input_rb connect \rc \input_rc + connect \xer_so \input_xer_so connect \xer_ca \input_xer_ca - connect \muxid$1 \input_muxid$18 - connect \sr_op__insn_type$2 \input_sr_op__insn_type$19 - connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$20 - connect \sr_op__imm_data__imm$4 \input_sr_op__imm_data__imm$21 - connect \sr_op__imm_data__imm_ok$5 \input_sr_op__imm_data__imm_ok$22 - connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$23 - connect \sr_op__rc__rc_ok$7 \input_sr_op__rc__rc_ok$24 - connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$25 - connect \sr_op__oe__oe_ok$9 \input_sr_op__oe__oe_ok$26 - connect \sr_op__input_carry$10 \input_sr_op__input_carry$27 - connect \sr_op__output_carry$11 \input_sr_op__output_carry$28 - connect \sr_op__input_cr$12 \input_sr_op__input_cr$29 - connect \sr_op__output_cr$13 \input_sr_op__output_cr$30 - connect \sr_op__is_32bit$14 \input_sr_op__is_32bit$31 - connect \sr_op__is_signed$15 \input_sr_op__is_signed$32 - connect \sr_op__insn$16 \input_sr_op__insn$33 - connect \ra$17 \input_ra$34 - connect \rb$18 \input_rb$35 - connect \rc$19 \input_rc$36 - connect \xer_ca$20 \input_xer_ca$37 + connect \muxid$1 \input_muxid$20 + connect \sr_op__insn_type$2 \input_sr_op__insn_type$21 + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$22 + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$23 + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$24 + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$25 + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$26 + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$27 + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$28 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$29 + connect \sr_op__input_carry$11 \input_sr_op__input_carry$30 + connect \sr_op__output_carry$12 \input_sr_op__output_carry$31 + connect \sr_op__input_cr$13 \input_sr_op__input_cr$32 + connect \sr_op__output_cr$14 \input_sr_op__output_cr$33 + connect \sr_op__is_32bit$15 \input_sr_op__is_32bit$34 + connect \sr_op__is_signed$16 \input_sr_op__is_signed$35 + connect \sr_op__insn$17 \input_sr_op__insn$36 + connect \ra$18 \input_ra$37 + connect \rb$19 \input_rb$38 + connect \rc$20 \input_rc$39 + connect \xer_so$21 \input_xer_so$40 + connect \xer_ca$22 \input_xer_ca$41 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid @@ -73184,17 +73718,19 @@ module \pipe1$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \main_sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__imm + wire width 64 \main_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__imm_data__imm_ok + wire width 1 \main_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc_ok + wire width 1 \main_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \main_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe_ok + wire width 1 \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -73219,8 +73755,10 @@ module \pipe1$107 wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \main_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$38 + wire width 2 \main_muxid$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -73295,7 +73833,7 @@ module \pipe1$107 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type$39 + wire width 7 \main_sr_op__insn_type$43 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -73309,53 +73847,58 @@ module \pipe1$107 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_sr_op__fn_unit$40 + wire width 11 \main_sr_op__fn_unit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__imm$41 + wire width 1 \main_sr_op__imm_data__ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__imm_data__imm_ok$42 + wire width 1 \main_sr_op__rc__rc$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc$43 + wire width 1 \main_sr_op__rc__ok$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc_ok$44 + wire width 1 \main_sr_op__oe__oe$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe$45 + wire width 1 \main_sr_op__oe__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe_ok$46 + wire width 1 \main_sr_op__write_cr0$51 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry$47 + wire width 2 \main_sr_op__input_carry$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__output_carry$48 + wire width 1 \main_sr_op__output_carry$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__input_cr$49 + wire width 1 \main_sr_op__input_cr$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__output_cr$50 + wire width 1 \main_sr_op__output_cr$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__is_32bit$51 + wire width 1 \main_sr_op__is_32bit$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__is_signed$52 + wire width 1 \main_sr_op__is_signed$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn$53 + wire width 32 \main_sr_op__insn$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_xer_so$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 2 \main_xer_ca cell \main$111 \main connect \muxid \main_muxid connect \sr_op__insn_type \main_sr_op__insn_type connect \sr_op__fn_unit \main_sr_op__fn_unit - connect \sr_op__imm_data__imm \main_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm_ok + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok connect \sr_op__rc__rc \main_sr_op__rc__rc - connect \sr_op__rc__rc_ok \main_sr_op__rc__rc_ok + connect \sr_op__rc__ok \main_sr_op__rc__ok connect \sr_op__oe__oe \main_sr_op__oe__oe - connect \sr_op__oe__oe_ok \main_sr_op__oe__oe_ok + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__write_cr0 \main_sr_op__write_cr0 connect \sr_op__input_carry \main_sr_op__input_carry connect \sr_op__output_carry \main_sr_op__output_carry connect \sr_op__input_cr \main_sr_op__input_cr @@ -73366,24 +73909,27 @@ module \pipe1$107 connect \ra \main_ra connect \rb \main_rb connect \rc \main_rc - connect \muxid$1 \main_muxid$38 - connect \sr_op__insn_type$2 \main_sr_op__insn_type$39 - connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$40 - connect \sr_op__imm_data__imm$4 \main_sr_op__imm_data__imm$41 - connect \sr_op__imm_data__imm_ok$5 \main_sr_op__imm_data__imm_ok$42 - connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$43 - connect \sr_op__rc__rc_ok$7 \main_sr_op__rc__rc_ok$44 - connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$45 - connect \sr_op__oe__oe_ok$9 \main_sr_op__oe__oe_ok$46 - connect \sr_op__input_carry$10 \main_sr_op__input_carry$47 - connect \sr_op__output_carry$11 \main_sr_op__output_carry$48 - connect \sr_op__input_cr$12 \main_sr_op__input_cr$49 - connect \sr_op__output_cr$13 \main_sr_op__output_cr$50 - connect \sr_op__is_32bit$14 \main_sr_op__is_32bit$51 - connect \sr_op__is_signed$15 \main_sr_op__is_signed$52 - connect \sr_op__insn$16 \main_sr_op__insn$53 + connect \xer_so \main_xer_so + connect \muxid$1 \main_muxid$42 + connect \sr_op__insn_type$2 \main_sr_op__insn_type$43 + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$44 + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$45 + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$46 + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$47 + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$48 + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$49 + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$50 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$51 + connect \sr_op__input_carry$11 \main_sr_op__input_carry$52 + connect \sr_op__output_carry$12 \main_sr_op__output_carry$53 + connect \sr_op__input_cr$13 \main_sr_op__input_cr$54 + connect \sr_op__output_cr$14 \main_sr_op__output_cr$55 + connect \sr_op__is_32bit$15 \main_sr_op__is_32bit$56 + connect \sr_op__is_signed$16 \main_sr_op__is_signed$57 + connect \sr_op__insn$17 \main_sr_op__insn$58 connect \o \main_o connect \o_ok \main_o_ok + connect \xer_so$18 \main_xer_so$59 connect \xer_ca \main_xer_ca end process $group_0 @@ -73394,13 +73940,13 @@ module \pipe1$107 process $group_1 assign \input_sr_op__insn_type 7'0000000 assign \input_sr_op__fn_unit 11'00000000000 - assign \input_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_sr_op__imm_data__imm_ok 1'0 + assign \input_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_sr_op__imm_data__ok 1'0 assign \input_sr_op__rc__rc 1'0 - assign \input_sr_op__rc__rc_ok 1'0 + assign \input_sr_op__rc__ok 1'0 assign \input_sr_op__oe__oe 1'0 - assign \input_sr_op__oe__oe_ok 1'0 - assign { } 0'0 + assign \input_sr_op__oe__ok 1'0 + assign \input_sr_op__write_cr0 1'0 assign \input_sr_op__input_carry 2'00 assign \input_sr_op__output_carry 1'0 assign \input_sr_op__input_cr 1'0 @@ -73408,7 +73954,7 @@ module \pipe1$107 assign \input_sr_op__is_32bit 1'0 assign \input_sr_op__is_signed 1'0 assign \input_sr_op__insn 32'00000000000000000000000000000000 - assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry { } { \input_sr_op__oe__oe_ok \input_sr_op__oe__oe } { \input_sr_op__rc__rc_ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } + assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__write_cr0 { \input_sr_op__oe__ok \input_sr_op__oe__oe } { \input_sr_op__rc__ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__ok \input_sr_op__imm_data__data } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 { \sr_op__oe__ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } sync init end process $group_17 @@ -73427,25 +73973,30 @@ module \pipe1$107 sync init end process $group_20 - assign \input_xer_ca 2'00 - assign \input_xer_ca \xer_ca$17 + assign \input_xer_so 1'0 + assign \input_xer_so \xer_so$18 sync init end process $group_21 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$18 + assign \input_xer_ca 2'00 + assign \input_xer_ca \xer_ca$19 sync init end process $group_22 + assign \main_muxid 2'00 + assign \main_muxid \input_muxid$20 + sync init + end + process $group_23 assign \main_sr_op__insn_type 7'0000000 assign \main_sr_op__fn_unit 11'00000000000 - assign \main_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_sr_op__imm_data__imm_ok 1'0 + assign \main_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_sr_op__imm_data__ok 1'0 assign \main_sr_op__rc__rc 1'0 - assign \main_sr_op__rc__rc_ok 1'0 + assign \main_sr_op__rc__ok 1'0 assign \main_sr_op__oe__oe 1'0 - assign \main_sr_op__oe__oe_ok 1'0 - assign { } 0'0 + assign \main_sr_op__oe__ok 1'0 + assign \main_sr_op__write_cr0 1'0 assign \main_sr_op__input_carry 2'00 assign \main_sr_op__output_carry 1'0 assign \main_sr_op__input_cr 1'0 @@ -73453,41 +74004,46 @@ module \pipe1$107 assign \main_sr_op__is_32bit 1'0 assign \main_sr_op__is_signed 1'0 assign \main_sr_op__insn 32'00000000000000000000000000000000 - assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry { } { \main_sr_op__oe__oe_ok \main_sr_op__oe__oe } { \main_sr_op__rc__rc_ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$33 \input_sr_op__is_signed$32 \input_sr_op__is_32bit$31 \input_sr_op__output_cr$30 \input_sr_op__input_cr$29 \input_sr_op__output_carry$28 \input_sr_op__input_carry$27 { } { \input_sr_op__oe__oe_ok$26 \input_sr_op__oe__oe$25 } { \input_sr_op__rc__rc_ok$24 \input_sr_op__rc__rc$23 } { \input_sr_op__imm_data__imm_ok$22 \input_sr_op__imm_data__imm$21 } \input_sr_op__fn_unit$20 \input_sr_op__insn_type$19 } + assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__write_cr0 { \main_sr_op__oe__ok \main_sr_op__oe__oe } { \main_sr_op__rc__ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__ok \main_sr_op__imm_data__data } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$36 \input_sr_op__is_signed$35 \input_sr_op__is_32bit$34 \input_sr_op__output_cr$33 \input_sr_op__input_cr$32 \input_sr_op__output_carry$31 \input_sr_op__input_carry$30 \input_sr_op__write_cr0$29 { \input_sr_op__oe__ok$28 \input_sr_op__oe__oe$27 } { \input_sr_op__rc__ok$26 \input_sr_op__rc__rc$25 } { \input_sr_op__imm_data__ok$24 \input_sr_op__imm_data__data$23 } \input_sr_op__fn_unit$22 \input_sr_op__insn_type$21 } sync init end - process $group_38 + process $group_39 assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$34 + assign \main_ra \input_ra$37 sync init end - process $group_39 + process $group_40 assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$35 + assign \main_rb \input_rb$38 sync init end - process $group_40 + process $group_41 assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rc \input_rc$36 + assign \main_rc \input_rc$39 + sync init + end + process $group_42 + assign \main_xer_so 1'0 + assign \main_xer_so \input_xer_so$40 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$54 - process $group_41 - assign \xer_ca$54 2'00 - assign \xer_ca$54 \input_xer_ca$37 + wire width 2 \xer_ca$60 + process $group_43 + assign \xer_ca$60 2'00 + assign \xer_ca$60 \input_xer_ca$41 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$55 - process $group_42 - assign \p_valid_i$55 1'0 - assign \p_valid_i$55 \p_valid_i + wire width 1 \p_valid_i$61 + process $group_44 + assign \p_valid_i$61 1'0 + assign \p_valid_i$61 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_43 + process $group_45 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -73495,28 +74051,28 @@ module \pipe1$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $56 + wire width 1 $62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $57 + cell $and $63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$55 + connect \A \p_valid_i$61 connect \B \p_ready_o - connect \Y $56 + connect \Y $62 end - process $group_44 + process $group_46 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $56 + assign \p_valid_i_p_ready_o $62 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$58 - process $group_45 - assign \muxid$58 2'00 - assign \muxid$58 \main_muxid$38 + wire width 2 \muxid$64 + process $group_47 + assign \muxid$64 2'00 + assign \muxid$64 \main_muxid$42 sync init end attribute \enum_base_type "MicrOp" @@ -73593,7 +74149,7 @@ module \pipe1$107 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$59 + wire width 7 \sr_op__insn_type$65 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -73607,98 +74163,112 @@ module \pipe1$107 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$60 + wire width 11 \sr_op__fn_unit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$61 + wire width 1 \sr_op__imm_data__ok$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$62 + wire width 1 \sr_op__rc__rc$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$63 + wire width 1 \sr_op__rc__ok$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$64 + wire width 1 \sr_op__oe__oe$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$65 + wire width 1 \sr_op__oe__ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$66 + wire width 1 \sr_op__write_cr0$73 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$67 + wire width 2 \sr_op__input_carry$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$68 + wire width 1 \sr_op__output_carry$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$69 + wire width 1 \sr_op__input_cr$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$70 + wire width 1 \sr_op__output_cr$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$71 + wire width 1 \sr_op__is_32bit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$72 + wire width 1 \sr_op__is_signed$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$73 - process $group_46 - assign \sr_op__insn_type$59 7'0000000 - assign \sr_op__fn_unit$60 11'00000000000 - assign \sr_op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$62 1'0 - assign \sr_op__rc__rc$63 1'0 - assign \sr_op__rc__rc_ok$64 1'0 - assign \sr_op__oe__oe$65 1'0 - assign \sr_op__oe__oe_ok$66 1'0 - assign { } 0'0 - assign \sr_op__input_carry$67 2'00 - assign \sr_op__output_carry$68 1'0 - assign \sr_op__input_cr$69 1'0 - assign \sr_op__output_cr$70 1'0 - assign \sr_op__is_32bit$71 1'0 - assign \sr_op__is_signed$72 1'0 - assign \sr_op__insn$73 32'00000000000000000000000000000000 - assign { \sr_op__insn$73 \sr_op__is_signed$72 \sr_op__is_32bit$71 \sr_op__output_cr$70 \sr_op__input_cr$69 \sr_op__output_carry$68 \sr_op__input_carry$67 { } { \sr_op__oe__oe_ok$66 \sr_op__oe__oe$65 } { \sr_op__rc__rc_ok$64 \sr_op__rc__rc$63 } { \sr_op__imm_data__imm_ok$62 \sr_op__imm_data__imm$61 } \sr_op__fn_unit$60 \sr_op__insn_type$59 } { \main_sr_op__insn$53 \main_sr_op__is_signed$52 \main_sr_op__is_32bit$51 \main_sr_op__output_cr$50 \main_sr_op__input_cr$49 \main_sr_op__output_carry$48 \main_sr_op__input_carry$47 { } { \main_sr_op__oe__oe_ok$46 \main_sr_op__oe__oe$45 } { \main_sr_op__rc__rc_ok$44 \main_sr_op__rc__rc$43 } { \main_sr_op__imm_data__imm_ok$42 \main_sr_op__imm_data__imm$41 } \main_sr_op__fn_unit$40 \main_sr_op__insn_type$39 } + wire width 32 \sr_op__insn$80 + process $group_48 + assign \sr_op__insn_type$65 7'0000000 + assign \sr_op__fn_unit$66 11'00000000000 + assign \sr_op__imm_data__data$67 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$68 1'0 + assign \sr_op__rc__rc$69 1'0 + assign \sr_op__rc__ok$70 1'0 + assign \sr_op__oe__oe$71 1'0 + assign \sr_op__oe__ok$72 1'0 + assign \sr_op__write_cr0$73 1'0 + assign \sr_op__input_carry$74 2'00 + assign \sr_op__output_carry$75 1'0 + assign \sr_op__input_cr$76 1'0 + assign \sr_op__output_cr$77 1'0 + assign \sr_op__is_32bit$78 1'0 + assign \sr_op__is_signed$79 1'0 + assign \sr_op__insn$80 32'00000000000000000000000000000000 + assign { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 { \sr_op__oe__ok$72 \sr_op__oe__oe$71 } { \sr_op__rc__ok$70 \sr_op__rc__rc$69 } { \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 } \sr_op__fn_unit$66 \sr_op__insn_type$65 } { \main_sr_op__insn$58 \main_sr_op__is_signed$57 \main_sr_op__is_32bit$56 \main_sr_op__output_cr$55 \main_sr_op__input_cr$54 \main_sr_op__output_carry$53 \main_sr_op__input_carry$52 \main_sr_op__write_cr0$51 { \main_sr_op__oe__ok$50 \main_sr_op__oe__oe$49 } { \main_sr_op__rc__ok$48 \main_sr_op__rc__rc$47 } { \main_sr_op__imm_data__ok$46 \main_sr_op__imm_data__data$45 } \main_sr_op__fn_unit$44 \main_sr_op__insn_type$43 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$74 + wire width 64 \o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$75 - process $group_62 - assign \o$74 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$75 1'0 - assign { \o_ok$75 \o$74 } { \main_o_ok \main_o } + wire width 1 \o_ok$82 + process $group_64 + assign \o$81 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$82 1'0 + assign { \o_ok$82 \o$81 } { \main_o_ok \main_o } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$76 + wire width 4 \cr_a$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$77 + wire width 1 \cr_a_ok$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$78 + wire width 4 \cr_a$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$79 - process $group_64 - assign \cr_a$76 4'0000 - assign \cr_a_ok$77 1'0 - assign { \cr_a_ok$77 \cr_a$76 } { \cr_a_ok$79 \cr_a$78 } + wire width 1 \cr_a_ok$86 + process $group_66 + assign \cr_a$83 4'0000 + assign \cr_a_ok$84 1'0 + assign { \cr_a_ok$84 \cr_a$83 } { \cr_a_ok$86 \cr_a$85 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$80 + wire width 1 \xer_so$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$81 + wire width 1 \xer_so_ok$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$82 - process $group_66 - assign \xer_ca$80 2'00 - assign \xer_ca_ok$81 1'0 - assign { \xer_ca_ok$81 \xer_ca$80 } { \xer_ca_ok$82 \main_xer_ca } + wire width 1 \xer_so_ok$89 + process $group_68 + assign \xer_so$87 1'0 + assign \xer_so_ok$88 1'0 + assign { \xer_so_ok$88 \xer_so$87 } { \xer_so_ok$89 \main_xer_so$59 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$92 + process $group_70 + assign \xer_ca$90 2'00 + assign \xer_ca_ok$91 1'0 + assign { \xer_ca_ok$91 \xer_ca$90 } { \xer_ca_ok$92 \main_xer_ca } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_68 + process $group_72 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -73719,32 +74289,32 @@ module \pipe1$107 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_69 + process $group_73 assign \muxid$next \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$next \muxid$58 + assign \muxid$next \muxid$64 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$next \muxid$58 + assign \muxid$next \muxid$64 end sync init update \muxid 2'00 sync posedge \coresync_clk update \muxid \muxid$next end - process $group_70 + process $group_74 assign \sr_op__insn_type$next \sr_op__insn_type assign \sr_op__fn_unit$next \sr_op__fn_unit - assign \sr_op__imm_data__imm$next \sr_op__imm_data__imm - assign \sr_op__imm_data__imm_ok$next \sr_op__imm_data__imm_ok + assign \sr_op__imm_data__data$next \sr_op__imm_data__data + assign \sr_op__imm_data__ok$next \sr_op__imm_data__ok assign \sr_op__rc__rc$next \sr_op__rc__rc - assign \sr_op__rc__rc_ok$next \sr_op__rc__rc_ok + assign \sr_op__rc__ok$next \sr_op__rc__ok assign \sr_op__oe__oe$next \sr_op__oe__oe - assign \sr_op__oe__oe_ok$next \sr_op__oe__oe_ok - assign { } { } + assign \sr_op__oe__ok$next \sr_op__oe__ok + assign \sr_op__write_cr0$next \sr_op__write_cr0 assign \sr_op__input_carry$next \sr_op__input_carry assign \sr_op__output_carry$next \sr_op__output_carry assign \sr_op__input_cr$next \sr_op__input_cr @@ -73756,31 +74326,31 @@ module \pipe1$107 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next { } { \sr_op__oe__oe_ok$next \sr_op__oe__oe$next } { \sr_op__rc__rc_ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__imm_ok$next \sr_op__imm_data__imm$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$73 \sr_op__is_signed$72 \sr_op__is_32bit$71 \sr_op__output_cr$70 \sr_op__input_cr$69 \sr_op__output_carry$68 \sr_op__input_carry$67 { } { \sr_op__oe__oe_ok$66 \sr_op__oe__oe$65 } { \sr_op__rc__rc_ok$64 \sr_op__rc__rc$63 } { \sr_op__imm_data__imm_ok$62 \sr_op__imm_data__imm$61 } \sr_op__fn_unit$60 \sr_op__insn_type$59 } + assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next \sr_op__write_cr0$next { \sr_op__oe__ok$next \sr_op__oe__oe$next } { \sr_op__rc__ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__ok$next \sr_op__imm_data__data$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 { \sr_op__oe__ok$72 \sr_op__oe__oe$71 } { \sr_op__rc__ok$70 \sr_op__rc__rc$69 } { \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 } \sr_op__fn_unit$66 \sr_op__insn_type$65 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next { } { \sr_op__oe__oe_ok$next \sr_op__oe__oe$next } { \sr_op__rc__rc_ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__imm_ok$next \sr_op__imm_data__imm$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$73 \sr_op__is_signed$72 \sr_op__is_32bit$71 \sr_op__output_cr$70 \sr_op__input_cr$69 \sr_op__output_carry$68 \sr_op__input_carry$67 { } { \sr_op__oe__oe_ok$66 \sr_op__oe__oe$65 } { \sr_op__rc__rc_ok$64 \sr_op__rc__rc$63 } { \sr_op__imm_data__imm_ok$62 \sr_op__imm_data__imm$61 } \sr_op__fn_unit$60 \sr_op__insn_type$59 } + assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next \sr_op__write_cr0$next { \sr_op__oe__ok$next \sr_op__oe__oe$next } { \sr_op__rc__ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__ok$next \sr_op__imm_data__data$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 { \sr_op__oe__ok$72 \sr_op__oe__oe$71 } { \sr_op__rc__ok$70 \sr_op__rc__rc$69 } { \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 } \sr_op__fn_unit$66 \sr_op__insn_type$65 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \sr_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$next 1'0 + assign \sr_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$next 1'0 assign \sr_op__rc__rc$next 1'0 - assign \sr_op__rc__rc_ok$next 1'0 + assign \sr_op__rc__ok$next 1'0 assign \sr_op__oe__oe$next 1'0 - assign \sr_op__oe__oe_ok$next 1'0 + assign \sr_op__oe__ok$next 1'0 end sync init update \sr_op__insn_type 7'0000000 update \sr_op__fn_unit 11'00000000000 - update \sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \sr_op__imm_data__imm_ok 1'0 + update \sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \sr_op__imm_data__ok 1'0 update \sr_op__rc__rc 1'0 - update \sr_op__rc__rc_ok 1'0 + update \sr_op__rc__ok 1'0 update \sr_op__oe__oe 1'0 - update \sr_op__oe__oe_ok 1'0 - update { } 0'0 + update \sr_op__oe__ok 1'0 + update \sr_op__write_cr0 1'0 update \sr_op__input_carry 2'00 update \sr_op__output_carry 1'0 update \sr_op__input_cr 1'0 @@ -73791,13 +74361,13 @@ module \pipe1$107 sync posedge \coresync_clk update \sr_op__insn_type \sr_op__insn_type$next update \sr_op__fn_unit \sr_op__fn_unit$next - update \sr_op__imm_data__imm \sr_op__imm_data__imm$next - update \sr_op__imm_data__imm_ok \sr_op__imm_data__imm_ok$next + update \sr_op__imm_data__data \sr_op__imm_data__data$next + update \sr_op__imm_data__ok \sr_op__imm_data__ok$next update \sr_op__rc__rc \sr_op__rc__rc$next - update \sr_op__rc__rc_ok \sr_op__rc__rc_ok$next + update \sr_op__rc__ok \sr_op__rc__ok$next update \sr_op__oe__oe \sr_op__oe__oe$next - update \sr_op__oe__oe_ok \sr_op__oe__oe_ok$next - update { } { } + update \sr_op__oe__ok \sr_op__oe__ok$next + update \sr_op__write_cr0 \sr_op__write_cr0$next update \sr_op__input_carry \sr_op__input_carry$next update \sr_op__output_carry \sr_op__output_carry$next update \sr_op__input_cr \sr_op__input_cr$next @@ -73806,17 +74376,17 @@ module \pipe1$107 update \sr_op__is_signed \sr_op__is_signed$next update \sr_op__insn \sr_op__insn$next end - process $group_86 + process $group_90 assign \o$next \o assign \o_ok$next \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$75 \o$74 } + assign { \o_ok$next \o$next } { \o_ok$82 \o$81 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$next \o$next } { \o_ok$75 \o$74 } + assign { \o_ok$next \o$next } { \o_ok$82 \o$81 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -73830,17 +74400,17 @@ module \pipe1$107 update \o \o$next update \o_ok \o_ok$next end - process $group_88 + process $group_92 assign \cr_a$next \cr_a assign \cr_a_ok$next \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$77 \cr_a$76 } + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$84 \cr_a$83 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$77 \cr_a$76 } + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$84 \cr_a$83 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -73854,17 +74424,41 @@ module \pipe1$107 update \cr_a \cr_a$next update \cr_a_ok \cr_a_ok$next end - process $group_90 + process $group_94 + assign \xer_so$next \xer_so + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$88 \xer_so$87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$88 \xer_so$87 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_so_ok$next 1'0 + end + sync init + update \xer_so 1'0 + update \xer_so_ok 1'0 + sync posedge \coresync_clk + update \xer_so \xer_so$next + update \xer_so_ok \xer_so_ok$next + end + process $group_96 assign \xer_ca$next \xer_ca assign \xer_ca_ok$next \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$81 \xer_ca$80 } + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$91 \xer_ca$90 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$81 \xer_ca$80 } + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$91 \xer_ca$90 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -73878,19 +74472,20 @@ module \pipe1$107 update \xer_ca \xer_ca$next update \xer_ca_ok \xer_ca_ok$next end - process $group_92 + process $group_98 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_93 + process $group_99 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end - connect \cr_a$78 4'0000 - connect \cr_a_ok$79 1'0 - connect \xer_ca_ok$82 1'0 + connect \cr_a$85 4'0000 + connect \cr_a_ok$86 1'0 + connect \xer_so_ok$89 1'0 + connect \xer_ca_ok$92 1'0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" @@ -74043,17 +74638,19 @@ module \output$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__imm + wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__imm_ok + wire width 1 input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__rc_ok + wire width 1 input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__oe_ok + wire width 1 input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -74079,9 +74676,11 @@ module \output$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 4 input 19 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 20 \xer_ca + wire width 1 input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 21 \xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 22 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -74156,7 +74755,7 @@ module \output$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \sr_op__insn_type$2 + wire width 7 output 23 \sr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -74170,76 +74769,78 @@ module \output$115 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \sr_op__fn_unit$3 + wire width 11 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \sr_op__imm_data__imm$4 + wire width 64 output 25 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \sr_op__imm_data__imm_ok$5 + wire width 1 output 26 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \sr_op__rc__rc$6 + wire width 1 output 27 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \sr_op__rc__rc_ok$7 + wire width 1 output 28 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \sr_op__oe__oe$8 + wire width 1 output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \sr_op__oe__oe_ok$9 + wire width 1 output 31 \sr_op__write_cr0$10 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$10 + wire width 2 output 32 \sr_op__input_carry$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__output_carry$11 + wire width 1 output 33 \sr_op__output_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__input_cr$12 + wire width 1 output 34 \sr_op__input_cr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__output_cr$13 + wire width 1 output 35 \sr_op__output_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_32bit$14 + wire width 1 output 36 \sr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \sr_op__is_signed$15 + wire width 1 output 37 \sr_op__is_signed$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 \sr_op__insn$16 + wire width 32 output 38 \sr_op__insn$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 38 \o$17 + wire width 64 output 39 \o$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 39 \o_ok$18 + wire width 1 output 40 \o_ok$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 40 \cr_a$19 + wire width 4 output 41 \cr_a$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 41 \cr_a_ok + wire width 1 output 42 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 42 \xer_ca$20 + wire width 2 output 43 \xer_ca$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$21 + wire width 1 output 44 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $22 + wire width 65 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $23 + cell $pos $24 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $22 + connect \Y $23 end process $group_0 - assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \o$21 $22 + assign \o$22 65'00000000000000000000000000000000000000000000000000000000000000000 + assign \o$22 $23 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target process $group_1 assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$21 [63:0] + assign \target \o$22 [63:0] sync init end process $group_2 - assign \xer_ca$20 2'00 - assign \xer_ca$20 \xer_ca + assign \xer_ca$21 2'00 + assign \xer_ca$21 \xer_ca sync init end process $group_3 @@ -74247,12 +74848,12 @@ module \output$115 assign \xer_ca_ok \sr_op__output_carry sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $26 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -74260,19 +74861,19 @@ module \output$115 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $24 + connect \Y $25 end process $group_4 assign \is_cmp 1'0 - assign \is_cmp $24 + assign \is_cmp $25 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -74280,166 +74881,130 @@ module \output$115 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $26 + connect \Y $27 end process $group_5 assign \is_cmpeqb 1'0 - assign \is_cmpeqb $26 + assign \is_cmpeqb $27 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire width 1 \msb_test process $group_6 assign \msb_test 1'0 assign \msb_test \target [63] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_bool $30 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $28 + connect \Y $29 end process $group_7 assign \is_nzero 1'0 - assign \is_nzero $28 + assign \is_nzero $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire width 1 \is_negative + process $group_8 + assign \is_negative 1'0 + assign \is_negative \msb_test + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $30 + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \B $30 - connect \Y $32 + connect \B $31 + connect \Y $33 end - process $group_8 + process $group_9 assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $32 - end + assign \is_positive $33 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $34 - connect \Y $36 - end - process $group_9 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $35 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $38 + connect \Y $37 end process $group_10 assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch { $35 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" case 1'1 assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" case - assign \cr0 { \is_negative \is_positive $38 1'0 } + assign \cr0 { \is_negative \is_positive $37 \xer_so } end sync init end process $group_11 - assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$17 \o$21 [63:0] + assign \o$18 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$18 \o$22 [63:0] sync init end process $group_12 - assign \o_ok$18 1'0 - assign \o_ok$18 \o_ok + assign \o_ok$19 1'0 + assign \o_ok$19 \o_ok sync init end process $group_13 - assign \cr_a$19 4'0000 - assign \cr_a$19 \cr0 + assign \cr_a$20 4'0000 + assign \cr_a$20 \cr0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 0 - parameter \Y_WIDTH 1 - connect \A { } - connect \Y $40 - end process $group_14 assign \cr_a_ok 1'0 - assign \cr_a_ok $40 + assign \cr_a_ok \sr_op__write_cr0 sync init end process $group_15 @@ -74450,30 +75015,30 @@ module \output$115 process $group_16 assign \sr_op__insn_type$2 7'0000000 assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5 1'0 + assign \sr_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$5 1'0 assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__rc_ok$7 1'0 + assign \sr_op__rc__ok$7 1'0 assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__oe_ok$9 1'0 - assign { } 0'0 - assign \sr_op__input_carry$10 2'00 - assign \sr_op__output_carry$11 1'0 - assign \sr_op__input_cr$12 1'0 - assign \sr_op__output_cr$13 1'0 - assign \sr_op__is_32bit$14 1'0 - assign \sr_op__is_signed$15 1'0 - assign \sr_op__insn$16 32'00000000000000000000000000000000 - assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + assign \sr_op__oe__ok$9 1'0 + assign \sr_op__write_cr0$10 1'0 + assign \sr_op__input_carry$11 2'00 + assign \sr_op__output_carry$12 1'0 + assign \sr_op__input_cr$13 1'0 + assign \sr_op__output_cr$14 1'0 + assign \sr_op__is_32bit$15 1'0 + assign \sr_op__is_signed$16 1'0 + assign \sr_op__insn$17 32'00000000000000000000000000000000 + assign { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 { \sr_op__oe__ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" module \pipe2$112 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -74571,17 +75136,19 @@ module \pipe2$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \sr_op__imm_data__imm + wire width 64 input 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__imm_data__imm_ok + wire width 1 input 8 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \sr_op__rc__rc_ok + wire width 1 input 10 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__oe__oe_ok + wire width 1 input 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -74609,15 +75176,19 @@ module \pipe2$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 input 24 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 25 \xer_ca + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 26 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 26 \xer_ca_ok + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 28 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 27 \n_valid_o + wire width 1 output 29 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 28 \n_ready_i + wire width 1 input 30 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 29 \muxid$1 + wire width 2 output 31 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" @@ -74694,7 +75265,7 @@ module \pipe2$112 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 30 \sr_op__insn_type$2 + wire width 7 output 32 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$2$next attribute \enum_base_type "Function" @@ -74710,89 +75281,93 @@ module \pipe2$112 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 31 \sr_op__fn_unit$3 + wire width 11 output 33 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \sr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 32 \sr_op__imm_data__imm$4 + wire width 64 output 34 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$4$next + wire width 64 \sr_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__imm_data__imm_ok$5 + wire width 1 output 35 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$5$next + wire width 1 \sr_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__rc__rc$6 + wire width 1 output 36 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \sr_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__rc__rc_ok$7 + wire width 1 output 37 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$7$next + wire width 1 \sr_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \sr_op__oe__oe$8 + wire width 1 output 38 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \sr_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \sr_op__oe__oe_ok$9 + wire width 1 output 39 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$9$next + wire width 1 output 40 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__write_cr0$10$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 39 \sr_op__input_carry$10 + wire width 2 output 41 \sr_op__input_carry$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$10$next + wire width 2 \sr_op__input_carry$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \sr_op__output_carry$11 + wire width 1 output 42 \sr_op__output_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$11$next + wire width 1 \sr_op__output_carry$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \sr_op__input_cr$12 + wire width 1 output 43 \sr_op__input_cr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$12$next + wire width 1 \sr_op__input_cr$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \sr_op__output_cr$13 + wire width 1 output 44 \sr_op__output_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$13$next + wire width 1 \sr_op__output_cr$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \sr_op__is_32bit$14 + wire width 1 output 45 \sr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$14$next + wire width 1 \sr_op__is_32bit$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \sr_op__is_signed$15 + wire width 1 output 46 \sr_op__is_signed$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$15$next + wire width 1 \sr_op__is_signed$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 45 \sr_op__insn$16 + wire width 32 output 47 \sr_op__insn$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$16$next + wire width 32 \sr_op__insn$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 46 \o$17 + wire width 64 output 48 \o$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$17$next + wire width 64 \o$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \o_ok$18 + wire width 1 output 49 \o_ok$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$18$next + wire width 1 \o_ok$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 48 \cr_a$19 + wire width 4 output 50 \cr_a$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$19$next + wire width 4 \cr_a$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \cr_a_ok$20 + wire width 1 output 51 \cr_a_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$20$next + wire width 1 \cr_a_ok$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 50 \xer_ca$21 + wire width 2 output 52 \xer_ca$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$21$next + wire width 2 \xer_ca$22$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 51 \xer_ca_ok$22 + wire width 1 output 53 \xer_ca_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$22$next + wire width 1 \xer_ca_ok$23$next cell \p$113 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -74893,17 +75468,19 @@ module \pipe2$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \output_sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__imm + wire width 64 \output_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__imm_data__imm_ok + wire width 1 \output_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc_ok + wire width 1 \output_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \output_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe_ok + wire width 1 \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -74929,9 +75506,11 @@ module \pipe2$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 2 \output_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$23 + wire width 2 \output_muxid$24 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -75006,7 +75585,7 @@ module \pipe2$112 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type$24 + wire width 7 \output_sr_op__insn_type$25 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -75020,59 +75599,62 @@ module \pipe2$112 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_sr_op__fn_unit$25 + wire width 11 \output_sr_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__imm$26 + wire width 1 \output_sr_op__imm_data__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__imm_data__imm_ok$27 + wire width 1 \output_sr_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc$28 + wire width 1 \output_sr_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc_ok$29 + wire width 1 \output_sr_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe$30 + wire width 1 \output_sr_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe_ok$31 + wire width 1 \output_sr_op__write_cr0$33 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$32 + wire width 2 \output_sr_op__input_carry$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__output_carry$33 + wire width 1 \output_sr_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__input_cr$34 + wire width 1 \output_sr_op__input_cr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__output_cr$35 + wire width 1 \output_sr_op__output_cr$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__is_32bit$36 + wire width 1 \output_sr_op__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__is_signed$37 + wire width 1 \output_sr_op__is_signed$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$38 + wire width 32 \output_sr_op__insn$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$39 + wire width 64 \output_o$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$40 + wire width 1 \output_o_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$41 + wire width 4 \output_cr_a$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$42 + wire width 2 \output_xer_ca$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \output_xer_ca_ok cell \output$115 \output connect \muxid \output_muxid connect \sr_op__insn_type \output_sr_op__insn_type connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__imm_data__imm \output_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm_ok + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc_ok \output_sr_op__rc__rc_ok + connect \sr_op__rc__ok \output_sr_op__rc__ok connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe_ok \output_sr_op__oe__oe_ok + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__write_cr0 \output_sr_op__write_cr0 connect \sr_op__input_carry \output_sr_op__input_carry connect \sr_op__output_carry \output_sr_op__output_carry connect \sr_op__input_cr \output_sr_op__input_cr @@ -75083,28 +75665,30 @@ module \pipe2$112 connect \o \output_o connect \o_ok \output_o_ok connect \cr_a \output_cr_a + connect \xer_so \output_xer_so connect \xer_ca \output_xer_ca - connect \muxid$1 \output_muxid$23 - connect \sr_op__insn_type$2 \output_sr_op__insn_type$24 - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$25 - connect \sr_op__imm_data__imm$4 \output_sr_op__imm_data__imm$26 - connect \sr_op__imm_data__imm_ok$5 \output_sr_op__imm_data__imm_ok$27 - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$28 - connect \sr_op__rc__rc_ok$7 \output_sr_op__rc__rc_ok$29 - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$30 - connect \sr_op__oe__oe_ok$9 \output_sr_op__oe__oe_ok$31 - connect \sr_op__input_carry$10 \output_sr_op__input_carry$32 - connect \sr_op__output_carry$11 \output_sr_op__output_carry$33 - connect \sr_op__input_cr$12 \output_sr_op__input_cr$34 - connect \sr_op__output_cr$13 \output_sr_op__output_cr$35 - connect \sr_op__is_32bit$14 \output_sr_op__is_32bit$36 - connect \sr_op__is_signed$15 \output_sr_op__is_signed$37 - connect \sr_op__insn$16 \output_sr_op__insn$38 - connect \o$17 \output_o$39 - connect \o_ok$18 \output_o_ok$40 - connect \cr_a$19 \output_cr_a$41 + connect \muxid$1 \output_muxid$24 + connect \sr_op__insn_type$2 \output_sr_op__insn_type$25 + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$26 + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$27 + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$28 + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$29 + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$30 + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$31 + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$32 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$33 + connect \sr_op__input_carry$11 \output_sr_op__input_carry$34 + connect \sr_op__output_carry$12 \output_sr_op__output_carry$35 + connect \sr_op__input_cr$13 \output_sr_op__input_cr$36 + connect \sr_op__output_cr$14 \output_sr_op__output_cr$37 + connect \sr_op__is_32bit$15 \output_sr_op__is_32bit$38 + connect \sr_op__is_signed$16 \output_sr_op__is_signed$39 + connect \sr_op__insn$17 \output_sr_op__insn$40 + connect \o$18 \output_o$41 + connect \o_ok$19 \output_o_ok$42 + connect \cr_a$20 \output_cr_a$43 connect \cr_a_ok \output_cr_a_ok - connect \xer_ca$20 \output_xer_ca$42 + connect \xer_ca$21 \output_xer_ca$44 connect \xer_ca_ok \output_xer_ca_ok end process $group_0 @@ -75115,13 +75699,13 @@ module \pipe2$112 process $group_1 assign \output_sr_op__insn_type 7'0000000 assign \output_sr_op__fn_unit 11'00000000000 - assign \output_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_sr_op__imm_data__imm_ok 1'0 + assign \output_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_sr_op__imm_data__ok 1'0 assign \output_sr_op__rc__rc 1'0 - assign \output_sr_op__rc__rc_ok 1'0 + assign \output_sr_op__rc__ok 1'0 assign \output_sr_op__oe__oe 1'0 - assign \output_sr_op__oe__oe_ok 1'0 - assign { } 0'0 + assign \output_sr_op__oe__ok 1'0 + assign \output_sr_op__write_cr0 1'0 assign \output_sr_op__input_carry 2'00 assign \output_sr_op__output_carry 1'0 assign \output_sr_op__input_cr 1'0 @@ -75129,7 +75713,7 @@ module \pipe2$112 assign \output_sr_op__is_32bit 1'0 assign \output_sr_op__is_signed 1'0 assign \output_sr_op__insn 32'00000000000000000000000000000000 - assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry { } { \output_sr_op__oe__oe_ok \output_sr_op__oe__oe } { \output_sr_op__rc__rc_ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm } \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__write_cr0 { \output_sr_op__oe__ok \output_sr_op__oe__oe } { \output_sr_op__rc__ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__ok \output_sr_op__imm_data__data } \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } sync init end process $group_17 @@ -75139,31 +75723,39 @@ module \pipe2$112 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$43 + wire width 1 \cr_a_ok$45 process $group_19 assign \output_cr_a 4'0000 - assign \cr_a_ok$43 1'0 - assign { \cr_a_ok$43 \output_cr_a } { \cr_a_ok \cr_a } + assign \cr_a_ok$45 1'0 + assign { \cr_a_ok$45 \output_cr_a } { \cr_a_ok \cr_a } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$44 + wire width 1 \xer_so_ok$46 process $group_21 + assign \output_xer_so 1'0 + assign \xer_so_ok$46 1'0 + assign { \xer_so_ok$46 \output_xer_so } { \xer_so_ok \xer_so } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$47 + process $group_23 assign \output_xer_ca 2'00 - assign \xer_ca_ok$44 1'0 - assign { \xer_ca_ok$44 \output_xer_ca } { \xer_ca_ok \xer_ca } + assign \xer_ca_ok$47 1'0 + assign { \xer_ca_ok$47 \output_xer_ca } { \xer_ca_ok \xer_ca } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$45 - process $group_23 - assign \p_valid_i$45 1'0 - assign \p_valid_i$45 \p_valid_i + wire width 1 \p_valid_i$48 + process $group_25 + assign \p_valid_i$48 1'0 + assign \p_valid_i$48 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_24 + process $group_26 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -75171,28 +75763,28 @@ module \pipe2$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $46 + wire width 1 $49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $47 + cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$45 + connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $46 + connect \Y $49 end - process $group_25 + process $group_27 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $46 + assign \p_valid_i_p_ready_o $49 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$48 - process $group_26 - assign \muxid$48 2'00 - assign \muxid$48 \output_muxid$23 + wire width 2 \muxid$51 + process $group_28 + assign \muxid$51 2'00 + assign \muxid$51 \output_muxid$24 sync init end attribute \enum_base_type "MicrOp" @@ -75269,7 +75861,7 @@ module \pipe2$112 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$49 + wire width 7 \sr_op__insn_type$52 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -75283,92 +75875,94 @@ module \pipe2$112 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$50 + wire width 11 \sr_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$51 + wire width 1 \sr_op__imm_data__ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$52 + wire width 1 \sr_op__rc__rc$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$53 + wire width 1 \sr_op__rc__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$54 + wire width 1 \sr_op__oe__oe$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$55 + wire width 1 \sr_op__oe__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$56 + wire width 1 \sr_op__write_cr0$60 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$57 + wire width 2 \sr_op__input_carry$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$58 + wire width 1 \sr_op__output_carry$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$59 + wire width 1 \sr_op__input_cr$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$60 + wire width 1 \sr_op__output_cr$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$61 + wire width 1 \sr_op__is_32bit$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$62 + wire width 1 \sr_op__is_signed$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$63 - process $group_27 - assign \sr_op__insn_type$49 7'0000000 - assign \sr_op__fn_unit$50 11'00000000000 - assign \sr_op__imm_data__imm$51 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$52 1'0 - assign \sr_op__rc__rc$53 1'0 - assign \sr_op__rc__rc_ok$54 1'0 - assign \sr_op__oe__oe$55 1'0 - assign \sr_op__oe__oe_ok$56 1'0 - assign { } 0'0 - assign \sr_op__input_carry$57 2'00 - assign \sr_op__output_carry$58 1'0 - assign \sr_op__input_cr$59 1'0 - assign \sr_op__output_cr$60 1'0 - assign \sr_op__is_32bit$61 1'0 - assign \sr_op__is_signed$62 1'0 - assign \sr_op__insn$63 32'00000000000000000000000000000000 - assign { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 { } { \sr_op__oe__oe_ok$56 \sr_op__oe__oe$55 } { \sr_op__rc__rc_ok$54 \sr_op__rc__rc$53 } { \sr_op__imm_data__imm_ok$52 \sr_op__imm_data__imm$51 } \sr_op__fn_unit$50 \sr_op__insn_type$49 } { \output_sr_op__insn$38 \output_sr_op__is_signed$37 \output_sr_op__is_32bit$36 \output_sr_op__output_cr$35 \output_sr_op__input_cr$34 \output_sr_op__output_carry$33 \output_sr_op__input_carry$32 { } { \output_sr_op__oe__oe_ok$31 \output_sr_op__oe__oe$30 } { \output_sr_op__rc__rc_ok$29 \output_sr_op__rc__rc$28 } { \output_sr_op__imm_data__imm_ok$27 \output_sr_op__imm_data__imm$26 } \output_sr_op__fn_unit$25 \output_sr_op__insn_type$24 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$65 - process $group_43 - assign \o$64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$65 1'0 - assign { \o_ok$65 \o$64 } { \output_o_ok$40 \output_o$39 } + wire width 32 \sr_op__insn$67 + process $group_29 + assign \sr_op__insn_type$52 7'0000000 + assign \sr_op__fn_unit$53 11'00000000000 + assign \sr_op__imm_data__data$54 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$55 1'0 + assign \sr_op__rc__rc$56 1'0 + assign \sr_op__rc__ok$57 1'0 + assign \sr_op__oe__oe$58 1'0 + assign \sr_op__oe__ok$59 1'0 + assign \sr_op__write_cr0$60 1'0 + assign \sr_op__input_carry$61 2'00 + assign \sr_op__output_carry$62 1'0 + assign \sr_op__input_cr$63 1'0 + assign \sr_op__output_cr$64 1'0 + assign \sr_op__is_32bit$65 1'0 + assign \sr_op__is_signed$66 1'0 + assign \sr_op__insn$67 32'00000000000000000000000000000000 + assign { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 { \sr_op__oe__ok$59 \sr_op__oe__oe$58 } { \sr_op__rc__ok$57 \sr_op__rc__rc$56 } { \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 } \sr_op__fn_unit$53 \sr_op__insn_type$52 } { \output_sr_op__insn$40 \output_sr_op__is_signed$39 \output_sr_op__is_32bit$38 \output_sr_op__output_cr$37 \output_sr_op__input_cr$36 \output_sr_op__output_carry$35 \output_sr_op__input_carry$34 \output_sr_op__write_cr0$33 { \output_sr_op__oe__ok$32 \output_sr_op__oe__oe$31 } { \output_sr_op__rc__ok$30 \output_sr_op__rc__rc$29 } { \output_sr_op__imm_data__ok$28 \output_sr_op__imm_data__data$27 } \output_sr_op__fn_unit$26 \output_sr_op__insn_type$25 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$69 + process $group_45 + assign \o$68 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$69 1'0 + assign { \o_ok$69 \o$68 } { \output_o_ok$42 \output_o$41 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$66 + wire width 4 \cr_a$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$67 - process $group_45 - assign \cr_a$66 4'0000 - assign \cr_a_ok$67 1'0 - assign { \cr_a_ok$67 \cr_a$66 } { \output_cr_a_ok \output_cr_a$41 } + wire width 1 \cr_a_ok$71 + process $group_47 + assign \cr_a$70 4'0000 + assign \cr_a_ok$71 1'0 + assign { \cr_a_ok$71 \cr_a$70 } { \output_cr_a_ok \output_cr_a$43 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$68 + wire width 2 \xer_ca$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$69 - process $group_47 - assign \xer_ca$68 2'00 - assign \xer_ca_ok$69 1'0 - assign { \xer_ca_ok$69 \xer_ca$68 } { \output_xer_ca_ok \output_xer_ca$42 } + wire width 1 \xer_ca_ok$73 + process $group_49 + assign \xer_ca$72 2'00 + assign \xer_ca_ok$73 1'0 + assign { \xer_ca_ok$73 \xer_ca$72 } { \output_xer_ca_ok \output_xer_ca$44 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_49 + process $group_51 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -75389,171 +75983,171 @@ module \pipe2$112 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_50 + process $group_52 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$48 + assign \muxid$1$next \muxid$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$48 + assign \muxid$1$next \muxid$51 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_51 + process $group_53 assign \sr_op__insn_type$2$next \sr_op__insn_type$2 assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3 - assign \sr_op__imm_data__imm$4$next \sr_op__imm_data__imm$4 - assign \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm_ok$5 + assign \sr_op__imm_data__data$4$next \sr_op__imm_data__data$4 + assign \sr_op__imm_data__ok$5$next \sr_op__imm_data__ok$5 assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6 - assign \sr_op__rc__rc_ok$7$next \sr_op__rc__rc_ok$7 + assign \sr_op__rc__ok$7$next \sr_op__rc__ok$7 assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8 - assign \sr_op__oe__oe_ok$9$next \sr_op__oe__oe_ok$9 - assign { } { } - assign \sr_op__input_carry$10$next \sr_op__input_carry$10 - assign \sr_op__output_carry$11$next \sr_op__output_carry$11 - assign \sr_op__input_cr$12$next \sr_op__input_cr$12 - assign \sr_op__output_cr$13$next \sr_op__output_cr$13 - assign \sr_op__is_32bit$14$next \sr_op__is_32bit$14 - assign \sr_op__is_signed$15$next \sr_op__is_signed$15 - assign \sr_op__insn$16$next \sr_op__insn$16 + assign \sr_op__oe__ok$9$next \sr_op__oe__ok$9 + assign \sr_op__write_cr0$10$next \sr_op__write_cr0$10 + assign \sr_op__input_carry$11$next \sr_op__input_carry$11 + assign \sr_op__output_carry$12$next \sr_op__output_carry$12 + assign \sr_op__input_cr$13$next \sr_op__input_cr$13 + assign \sr_op__output_cr$14$next \sr_op__output_cr$14 + assign \sr_op__is_32bit$15$next \sr_op__is_32bit$15 + assign \sr_op__is_signed$16$next \sr_op__is_signed$16 + assign \sr_op__insn$17$next \sr_op__insn$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 { } { \sr_op__oe__oe_ok$56 \sr_op__oe__oe$55 } { \sr_op__rc__rc_ok$54 \sr_op__rc__rc$53 } { \sr_op__imm_data__imm_ok$52 \sr_op__imm_data__imm$51 } \sr_op__fn_unit$50 \sr_op__insn_type$49 } + assign { \sr_op__insn$17$next \sr_op__is_signed$16$next \sr_op__is_32bit$15$next \sr_op__output_cr$14$next \sr_op__input_cr$13$next \sr_op__output_carry$12$next \sr_op__input_carry$11$next \sr_op__write_cr0$10$next { \sr_op__oe__ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__ok$5$next \sr_op__imm_data__data$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 { \sr_op__oe__ok$59 \sr_op__oe__oe$58 } { \sr_op__rc__ok$57 \sr_op__rc__rc$56 } { \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 } \sr_op__fn_unit$53 \sr_op__insn_type$52 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 { } { \sr_op__oe__oe_ok$56 \sr_op__oe__oe$55 } { \sr_op__rc__rc_ok$54 \sr_op__rc__rc$53 } { \sr_op__imm_data__imm_ok$52 \sr_op__imm_data__imm$51 } \sr_op__fn_unit$50 \sr_op__insn_type$49 } + assign { \sr_op__insn$17$next \sr_op__is_signed$16$next \sr_op__is_32bit$15$next \sr_op__output_cr$14$next \sr_op__input_cr$13$next \sr_op__output_carry$12$next \sr_op__input_carry$11$next \sr_op__write_cr0$10$next { \sr_op__oe__ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__ok$5$next \sr_op__imm_data__data$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 { \sr_op__oe__ok$59 \sr_op__oe__oe$58 } { \sr_op__rc__ok$57 \sr_op__rc__rc$56 } { \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 } \sr_op__fn_unit$53 \sr_op__insn_type$52 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \sr_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5$next 1'0 + assign \sr_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$5$next 1'0 assign \sr_op__rc__rc$6$next 1'0 - assign \sr_op__rc__rc_ok$7$next 1'0 + assign \sr_op__rc__ok$7$next 1'0 assign \sr_op__oe__oe$8$next 1'0 - assign \sr_op__oe__oe_ok$9$next 1'0 + assign \sr_op__oe__ok$9$next 1'0 end sync init update \sr_op__insn_type$2 7'0000000 update \sr_op__fn_unit$3 11'00000000000 - update \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \sr_op__imm_data__imm_ok$5 1'0 + update \sr_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \sr_op__imm_data__ok$5 1'0 update \sr_op__rc__rc$6 1'0 - update \sr_op__rc__rc_ok$7 1'0 + update \sr_op__rc__ok$7 1'0 update \sr_op__oe__oe$8 1'0 - update \sr_op__oe__oe_ok$9 1'0 - update { } 0'0 - update \sr_op__input_carry$10 2'00 - update \sr_op__output_carry$11 1'0 - update \sr_op__input_cr$12 1'0 - update \sr_op__output_cr$13 1'0 - update \sr_op__is_32bit$14 1'0 - update \sr_op__is_signed$15 1'0 - update \sr_op__insn$16 32'00000000000000000000000000000000 + update \sr_op__oe__ok$9 1'0 + update \sr_op__write_cr0$10 1'0 + update \sr_op__input_carry$11 2'00 + update \sr_op__output_carry$12 1'0 + update \sr_op__input_cr$13 1'0 + update \sr_op__output_cr$14 1'0 + update \sr_op__is_32bit$15 1'0 + update \sr_op__is_signed$16 1'0 + update \sr_op__insn$17 32'00000000000000000000000000000000 sync posedge \coresync_clk update \sr_op__insn_type$2 \sr_op__insn_type$2$next update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next - update \sr_op__imm_data__imm$4 \sr_op__imm_data__imm$4$next - update \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm_ok$5$next + update \sr_op__imm_data__data$4 \sr_op__imm_data__data$4$next + update \sr_op__imm_data__ok$5 \sr_op__imm_data__ok$5$next update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next - update \sr_op__rc__rc_ok$7 \sr_op__rc__rc_ok$7$next + update \sr_op__rc__ok$7 \sr_op__rc__ok$7$next update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next - update \sr_op__oe__oe_ok$9 \sr_op__oe__oe_ok$9$next - update { } { } - update \sr_op__input_carry$10 \sr_op__input_carry$10$next - update \sr_op__output_carry$11 \sr_op__output_carry$11$next - update \sr_op__input_cr$12 \sr_op__input_cr$12$next - update \sr_op__output_cr$13 \sr_op__output_cr$13$next - update \sr_op__is_32bit$14 \sr_op__is_32bit$14$next - update \sr_op__is_signed$15 \sr_op__is_signed$15$next - update \sr_op__insn$16 \sr_op__insn$16$next + update \sr_op__oe__ok$9 \sr_op__oe__ok$9$next + update \sr_op__write_cr0$10 \sr_op__write_cr0$10$next + update \sr_op__input_carry$11 \sr_op__input_carry$11$next + update \sr_op__output_carry$12 \sr_op__output_carry$12$next + update \sr_op__input_cr$13 \sr_op__input_cr$13$next + update \sr_op__output_cr$14 \sr_op__output_cr$14$next + update \sr_op__is_32bit$15 \sr_op__is_32bit$15$next + update \sr_op__is_signed$16 \sr_op__is_signed$16$next + update \sr_op__insn$17 \sr_op__insn$17$next end - process $group_67 - assign \o$17$next \o$17 - assign \o_ok$18$next \o_ok$18 + process $group_69 + assign \o$18$next \o$18 + assign \o_ok$19$next \o_ok$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$18$next \o$17$next } { \o_ok$65 \o$64 } + assign { \o_ok$19$next \o$18$next } { \o_ok$69 \o$68 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$18$next \o$17$next } { \o_ok$65 \o$64 } + assign { \o_ok$19$next \o$18$next } { \o_ok$69 \o$68 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \o_ok$18$next 1'0 + assign \o_ok$19$next 1'0 end sync init - update \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok$18 1'0 + update \o$18 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok$19 1'0 sync posedge \coresync_clk - update \o$17 \o$17$next - update \o_ok$18 \o_ok$18$next + update \o$18 \o$18$next + update \o_ok$19 \o_ok$19$next end - process $group_69 - assign \cr_a$19$next \cr_a$19 - assign \cr_a_ok$20$next \cr_a_ok$20 + process $group_71 + assign \cr_a$20$next \cr_a$20 + assign \cr_a_ok$21$next \cr_a_ok$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$20$next \cr_a$19$next } { \cr_a_ok$67 \cr_a$66 } + assign { \cr_a_ok$21$next \cr_a$20$next } { \cr_a_ok$71 \cr_a$70 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$20$next \cr_a$19$next } { \cr_a_ok$67 \cr_a$66 } + assign { \cr_a_ok$21$next \cr_a$20$next } { \cr_a_ok$71 \cr_a$70 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \cr_a_ok$20$next 1'0 + assign \cr_a_ok$21$next 1'0 end sync init - update \cr_a$19 4'0000 - update \cr_a_ok$20 1'0 + update \cr_a$20 4'0000 + update \cr_a_ok$21 1'0 sync posedge \coresync_clk - update \cr_a$19 \cr_a$19$next - update \cr_a_ok$20 \cr_a_ok$20$next + update \cr_a$20 \cr_a$20$next + update \cr_a_ok$21 \cr_a_ok$21$next end - process $group_71 - assign \xer_ca$21$next \xer_ca$21 - assign \xer_ca_ok$22$next \xer_ca_ok$22 + process $group_73 + assign \xer_ca$22$next \xer_ca$22 + assign \xer_ca_ok$23$next \xer_ca_ok$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ca_ok$22$next \xer_ca$21$next } { \xer_ca_ok$69 \xer_ca$68 } + assign { \xer_ca_ok$23$next \xer_ca$22$next } { \xer_ca_ok$73 \xer_ca$72 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ca_ok$22$next \xer_ca$21$next } { \xer_ca_ok$69 \xer_ca$68 } + assign { \xer_ca_ok$23$next \xer_ca$22$next } { \xer_ca_ok$73 \xer_ca$72 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \xer_ca_ok$22$next 1'0 + assign \xer_ca_ok$23$next 1'0 end sync init - update \xer_ca$21 2'00 - update \xer_ca_ok$22 1'0 + update \xer_ca$22 2'00 + update \xer_ca_ok$23 1'0 sync posedge \coresync_clk - update \xer_ca$21 \xer_ca$21$next - update \xer_ca_ok$22 \xer_ca_ok$22$next + update \xer_ca$22 \xer_ca$22$next + update \xer_ca_ok$23 \xer_ca_ok$23$next end - process $group_73 + process $group_75 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_74 + process $group_76 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init @@ -75562,7 +76156,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" module \alu_shift_rot0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 1 \o_ok @@ -75570,7 +76164,7 @@ module \alu_shift_rot0 wire width 1 output 2 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 3 \xer_ca_ok - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 4 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 output 5 \n_valid_o @@ -75666,17 +76260,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 8 \sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \sr_op__imm_data__imm + wire width 64 input 9 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \sr_op__imm_data__imm_ok + wire width 1 input 10 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__rc__rc_ok + wire width 1 input 12 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__oe__oe_ok + wire width 1 input 14 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -75708,11 +76304,13 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 28 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 29 \xer_ca$1 + wire width 1 input 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 30 \xer_ca$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 30 \p_valid_i + wire width 1 input 31 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 31 \p_ready_o + wire width 1 output 32 \p_ready_o cell \p$105 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -75817,17 +76415,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe1_sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__imm + wire width 64 \pipe1_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__imm_data__imm_ok + wire width 1 \pipe1_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__rc__rc_ok + wire width 1 \pipe1_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__oe__oe_ok + wire width 1 \pipe1_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -75855,6 +76455,10 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe1_xer_ca_ok @@ -75954,35 +76558,37 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe1_sr_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__imm$5 + wire width 64 \pipe1_sr_op__imm_data__data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__imm_data__imm_ok$6 + wire width 1 \pipe1_sr_op__imm_data__ok$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_sr_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__rc__rc_ok$8 + wire width 1 \pipe1_sr_op__rc__ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe1_sr_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__oe__oe_ok$10 + wire width 1 \pipe1_sr_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__write_cr0$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry$11 + wire width 2 \pipe1_sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__output_carry$12 + wire width 1 \pipe1_sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__input_cr$13 + wire width 1 \pipe1_sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__output_cr$14 + wire width 1 \pipe1_sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__is_32bit$15 + wire width 1 \pipe1_sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__is_signed$16 + wire width 1 \pipe1_sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn$17 + wire width 32 \pipe1_sr_op__insn$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -75990,7 +76596,9 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe1_xer_ca$18 + wire width 1 \pipe1_xer_so$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$20 cell \pipe1$107 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -75999,12 +76607,13 @@ module \alu_shift_rot0 connect \muxid \pipe1_muxid connect \sr_op__insn_type \pipe1_sr_op__insn_type connect \sr_op__fn_unit \pipe1_sr_op__fn_unit - connect \sr_op__imm_data__imm \pipe1_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \pipe1_sr_op__imm_data__imm_ok + connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data + connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok connect \sr_op__rc__rc \pipe1_sr_op__rc__rc - connect \sr_op__rc__rc_ok \pipe1_sr_op__rc__rc_ok + connect \sr_op__rc__ok \pipe1_sr_op__rc__ok connect \sr_op__oe__oe \pipe1_sr_op__oe__oe - connect \sr_op__oe__oe_ok \pipe1_sr_op__oe__oe_ok + connect \sr_op__oe__ok \pipe1_sr_op__oe__ok + connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 connect \sr_op__input_carry \pipe1_sr_op__input_carry connect \sr_op__output_carry \pipe1_sr_op__output_carry connect \sr_op__input_cr \pipe1_sr_op__input_cr @@ -76016,6 +76625,8 @@ module \alu_shift_rot0 connect \o_ok \pipe1_o_ok connect \cr_a \pipe1_cr_a connect \cr_a_ok \pipe1_cr_a_ok + connect \xer_so \pipe1_xer_so + connect \xer_so_ok \pipe1_xer_so_ok connect \xer_ca \pipe1_xer_ca connect \xer_ca_ok \pipe1_xer_ca_ok connect \p_valid_i \pipe1_p_valid_i @@ -76023,23 +76634,25 @@ module \alu_shift_rot0 connect \muxid$1 \pipe1_muxid$2 connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 - connect \sr_op__imm_data__imm$4 \pipe1_sr_op__imm_data__imm$5 - connect \sr_op__imm_data__imm_ok$5 \pipe1_sr_op__imm_data__imm_ok$6 + connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 + connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 - connect \sr_op__rc__rc_ok$7 \pipe1_sr_op__rc__rc_ok$8 + connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 - connect \sr_op__oe__oe_ok$9 \pipe1_sr_op__oe__oe_ok$10 - connect \sr_op__input_carry$10 \pipe1_sr_op__input_carry$11 - connect \sr_op__output_carry$11 \pipe1_sr_op__output_carry$12 - connect \sr_op__input_cr$12 \pipe1_sr_op__input_cr$13 - connect \sr_op__output_cr$13 \pipe1_sr_op__output_cr$14 - connect \sr_op__is_32bit$14 \pipe1_sr_op__is_32bit$15 - connect \sr_op__is_signed$15 \pipe1_sr_op__is_signed$16 - connect \sr_op__insn$16 \pipe1_sr_op__insn$17 + connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 + connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 + connect \sr_op__input_carry$11 \pipe1_sr_op__input_carry$12 + connect \sr_op__output_carry$12 \pipe1_sr_op__output_carry$13 + connect \sr_op__input_cr$13 \pipe1_sr_op__input_cr$14 + connect \sr_op__output_cr$14 \pipe1_sr_op__output_cr$15 + connect \sr_op__is_32bit$15 \pipe1_sr_op__is_32bit$16 + connect \sr_op__is_signed$16 \pipe1_sr_op__is_signed$17 + connect \sr_op__insn$17 \pipe1_sr_op__insn$18 connect \ra \pipe1_ra connect \rb \pipe1_rb connect \rc \pipe1_rc - connect \xer_ca$17 \pipe1_xer_ca$18 + connect \xer_so$18 \pipe1_xer_so$19 + connect \xer_ca$19 \pipe1_xer_ca$20 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 \pipe2_p_valid_i @@ -76137,17 +76750,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \pipe2_sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_sr_op__imm_data__imm + wire width 64 \pipe2_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__imm_data__imm_ok + wire width 1 \pipe2_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__rc_ok + wire width 1 \pipe2_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \pipe2_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__oe_ok + wire width 1 \pipe2_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -76175,6 +76790,10 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 2 \pipe2_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe2_xer_ca_ok @@ -76183,7 +76802,7 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire width 1 \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid$19 + wire width 2 \pipe2_muxid$21 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -76258,7 +76877,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_sr_op__insn_type$20 + wire width 7 \pipe2_sr_op__insn_type$22 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -76272,49 +76891,51 @@ module \alu_shift_rot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe2_sr_op__fn_unit$21 + wire width 11 \pipe2_sr_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_sr_op__imm_data__imm$22 + wire width 1 \pipe2_sr_op__imm_data__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__imm_data__imm_ok$23 + wire width 1 \pipe2_sr_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__rc$24 + wire width 1 \pipe2_sr_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__rc_ok$25 + wire width 1 \pipe2_sr_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__oe$26 + wire width 1 \pipe2_sr_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__oe_ok$27 + wire width 1 \pipe2_sr_op__write_cr0$30 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_sr_op__input_carry$28 + wire width 2 \pipe2_sr_op__input_carry$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__output_carry$29 + wire width 1 \pipe2_sr_op__output_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__input_cr$30 + wire width 1 \pipe2_sr_op__input_cr$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__output_cr$31 + wire width 1 \pipe2_sr_op__output_cr$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__is_32bit$32 + wire width 1 \pipe2_sr_op__is_32bit$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__is_signed$33 + wire width 1 \pipe2_sr_op__is_signed$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_sr_op__insn$34 + wire width 32 \pipe2_sr_op__insn$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o$35 + wire width 64 \pipe2_o$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_o_ok$36 + wire width 1 \pipe2_o_ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a$37 + wire width 4 \pipe2_cr_a$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_cr_a_ok$38 + wire width 1 \pipe2_cr_a_ok$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca$39 + wire width 2 \pipe2_xer_ca$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ca_ok$40 + wire width 1 \pipe2_xer_ca_ok$43 cell \pipe2$112 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -76323,12 +76944,13 @@ module \alu_shift_rot0 connect \muxid \pipe2_muxid connect \sr_op__insn_type \pipe2_sr_op__insn_type connect \sr_op__fn_unit \pipe2_sr_op__fn_unit - connect \sr_op__imm_data__imm \pipe2_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \pipe2_sr_op__imm_data__imm_ok + connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data + connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok connect \sr_op__rc__rc \pipe2_sr_op__rc__rc - connect \sr_op__rc__rc_ok \pipe2_sr_op__rc__rc_ok + connect \sr_op__rc__ok \pipe2_sr_op__rc__ok connect \sr_op__oe__oe \pipe2_sr_op__oe__oe - connect \sr_op__oe__oe_ok \pipe2_sr_op__oe__oe_ok + connect \sr_op__oe__ok \pipe2_sr_op__oe__ok + connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 connect \sr_op__input_carry \pipe2_sr_op__input_carry connect \sr_op__output_carry \pipe2_sr_op__output_carry connect \sr_op__input_cr \pipe2_sr_op__input_cr @@ -76340,32 +76962,35 @@ module \alu_shift_rot0 connect \o_ok \pipe2_o_ok connect \cr_a \pipe2_cr_a connect \cr_a_ok \pipe2_cr_a_ok + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok connect \xer_ca \pipe2_xer_ca connect \xer_ca_ok \pipe2_xer_ca_ok connect \n_valid_o \pipe2_n_valid_o connect \n_ready_i \pipe2_n_ready_i - connect \muxid$1 \pipe2_muxid$19 - connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$20 - connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$21 - connect \sr_op__imm_data__imm$4 \pipe2_sr_op__imm_data__imm$22 - connect \sr_op__imm_data__imm_ok$5 \pipe2_sr_op__imm_data__imm_ok$23 - connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$24 - connect \sr_op__rc__rc_ok$7 \pipe2_sr_op__rc__rc_ok$25 - connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$26 - connect \sr_op__oe__oe_ok$9 \pipe2_sr_op__oe__oe_ok$27 - connect \sr_op__input_carry$10 \pipe2_sr_op__input_carry$28 - connect \sr_op__output_carry$11 \pipe2_sr_op__output_carry$29 - connect \sr_op__input_cr$12 \pipe2_sr_op__input_cr$30 - connect \sr_op__output_cr$13 \pipe2_sr_op__output_cr$31 - connect \sr_op__is_32bit$14 \pipe2_sr_op__is_32bit$32 - connect \sr_op__is_signed$15 \pipe2_sr_op__is_signed$33 - connect \sr_op__insn$16 \pipe2_sr_op__insn$34 - connect \o$17 \pipe2_o$35 - connect \o_ok$18 \pipe2_o_ok$36 - connect \cr_a$19 \pipe2_cr_a$37 - connect \cr_a_ok$20 \pipe2_cr_a_ok$38 - connect \xer_ca$21 \pipe2_xer_ca$39 - connect \xer_ca_ok$22 \pipe2_xer_ca_ok$40 + connect \muxid$1 \pipe2_muxid$21 + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$22 + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$23 + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$25 + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$26 + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$27 + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$28 + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$29 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$30 + connect \sr_op__input_carry$11 \pipe2_sr_op__input_carry$31 + connect \sr_op__output_carry$12 \pipe2_sr_op__output_carry$32 + connect \sr_op__input_cr$13 \pipe2_sr_op__input_cr$33 + connect \sr_op__output_cr$14 \pipe2_sr_op__output_cr$34 + connect \sr_op__is_32bit$15 \pipe2_sr_op__is_32bit$35 + connect \sr_op__is_signed$16 \pipe2_sr_op__is_signed$36 + connect \sr_op__insn$17 \pipe2_sr_op__insn$37 + connect \o$18 \pipe2_o$38 + connect \o_ok$19 \pipe2_o_ok$39 + connect \cr_a$20 \pipe2_cr_a$40 + connect \cr_a_ok$21 \pipe2_cr_a_ok$41 + connect \xer_ca$22 \pipe2_xer_ca$42 + connect \xer_ca_ok$23 \pipe2_xer_ca_ok$43 end process $group_0 assign \pipe2_p_valid_i 1'0 @@ -76385,13 +77010,13 @@ module \alu_shift_rot0 process $group_3 assign \pipe2_sr_op__insn_type 7'0000000 assign \pipe2_sr_op__fn_unit 11'00000000000 - assign \pipe2_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe2_sr_op__imm_data__imm_ok 1'0 + assign \pipe2_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe2_sr_op__imm_data__ok 1'0 assign \pipe2_sr_op__rc__rc 1'0 - assign \pipe2_sr_op__rc__rc_ok 1'0 + assign \pipe2_sr_op__rc__ok 1'0 assign \pipe2_sr_op__oe__oe 1'0 - assign \pipe2_sr_op__oe__oe_ok 1'0 - assign { } 0'0 + assign \pipe2_sr_op__oe__ok 1'0 + assign \pipe2_sr_op__write_cr0 1'0 assign \pipe2_sr_op__input_carry 2'00 assign \pipe2_sr_op__output_carry 1'0 assign \pipe2_sr_op__input_cr 1'0 @@ -76399,7 +77024,7 @@ module \alu_shift_rot0 assign \pipe2_sr_op__is_32bit 1'0 assign \pipe2_sr_op__is_signed 1'0 assign \pipe2_sr_op__insn 32'00000000000000000000000000000000 - assign { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry { } { \pipe2_sr_op__oe__oe_ok \pipe2_sr_op__oe__oe } { \pipe2_sr_op__rc__rc_ok \pipe2_sr_op__rc__rc } { \pipe2_sr_op__imm_data__imm_ok \pipe2_sr_op__imm_data__imm } \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry { } { \pipe1_sr_op__oe__oe_ok \pipe1_sr_op__oe__oe } { \pipe1_sr_op__rc__rc_ok \pipe1_sr_op__rc__rc } { \pipe1_sr_op__imm_data__imm_ok \pipe1_sr_op__imm_data__imm } \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + assign { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__write_cr0 { \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe } { \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc } { \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data } \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__write_cr0 { \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe } { \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc } { \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data } \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } sync init end process $group_19 @@ -76415,83 +77040,94 @@ module \alu_shift_rot0 sync init end process $group_23 + assign \pipe2_xer_so 1'0 + assign \pipe2_xer_so_ok 1'0 + assign { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + sync init + end + process $group_25 assign \pipe2_xer_ca 2'00 assign \pipe2_xer_ca_ok 1'0 assign { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } sync init end - process $group_25 + process $group_27 assign \pipe1_p_valid_i 1'0 assign \pipe1_p_valid_i \p_valid_i sync init end - process $group_26 + process $group_28 assign \p_ready_o 1'0 assign \p_ready_o \pipe1_p_ready_o sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid - process $group_27 + process $group_29 assign \pipe1_muxid$2 2'00 assign \pipe1_muxid$2 \muxid sync init end - process $group_28 + process $group_30 assign \pipe1_sr_op__insn_type$3 7'0000000 assign \pipe1_sr_op__fn_unit$4 11'00000000000 - assign \pipe1_sr_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_sr_op__imm_data__imm_ok$6 1'0 + assign \pipe1_sr_op__imm_data__data$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_sr_op__imm_data__ok$6 1'0 assign \pipe1_sr_op__rc__rc$7 1'0 - assign \pipe1_sr_op__rc__rc_ok$8 1'0 + assign \pipe1_sr_op__rc__ok$8 1'0 assign \pipe1_sr_op__oe__oe$9 1'0 - assign \pipe1_sr_op__oe__oe_ok$10 1'0 - assign { } 0'0 - assign \pipe1_sr_op__input_carry$11 2'00 - assign \pipe1_sr_op__output_carry$12 1'0 - assign \pipe1_sr_op__input_cr$13 1'0 - assign \pipe1_sr_op__output_cr$14 1'0 - assign \pipe1_sr_op__is_32bit$15 1'0 - assign \pipe1_sr_op__is_signed$16 1'0 - assign \pipe1_sr_op__insn$17 32'00000000000000000000000000000000 - assign { \pipe1_sr_op__insn$17 \pipe1_sr_op__is_signed$16 \pipe1_sr_op__is_32bit$15 \pipe1_sr_op__output_cr$14 \pipe1_sr_op__input_cr$13 \pipe1_sr_op__output_carry$12 \pipe1_sr_op__input_carry$11 { } { \pipe1_sr_op__oe__oe_ok$10 \pipe1_sr_op__oe__oe$9 } { \pipe1_sr_op__rc__rc_ok$8 \pipe1_sr_op__rc__rc$7 } { \pipe1_sr_op__imm_data__imm_ok$6 \pipe1_sr_op__imm_data__imm$5 } \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + assign \pipe1_sr_op__oe__ok$10 1'0 + assign \pipe1_sr_op__write_cr0$11 1'0 + assign \pipe1_sr_op__input_carry$12 2'00 + assign \pipe1_sr_op__output_carry$13 1'0 + assign \pipe1_sr_op__input_cr$14 1'0 + assign \pipe1_sr_op__output_cr$15 1'0 + assign \pipe1_sr_op__is_32bit$16 1'0 + assign \pipe1_sr_op__is_signed$17 1'0 + assign \pipe1_sr_op__insn$18 32'00000000000000000000000000000000 + assign { \pipe1_sr_op__insn$18 \pipe1_sr_op__is_signed$17 \pipe1_sr_op__is_32bit$16 \pipe1_sr_op__output_cr$15 \pipe1_sr_op__input_cr$14 \pipe1_sr_op__output_carry$13 \pipe1_sr_op__input_carry$12 \pipe1_sr_op__write_cr0$11 { \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 } { \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 } { \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 } \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } sync init end - process $group_44 + process $group_46 assign \pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe1_ra \ra sync init end - process $group_45 + process $group_47 assign \pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe1_rb \rb sync init end - process $group_46 + process $group_48 assign \pipe1_rc 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe1_rc \rc sync init end - process $group_47 - assign \pipe1_xer_ca$18 2'00 - assign \pipe1_xer_ca$18 \xer_ca$1 + process $group_49 + assign \pipe1_xer_so$19 1'0 + assign \pipe1_xer_so$19 \xer_so sync init end - process $group_48 + process $group_50 + assign \pipe1_xer_ca$20 2'00 + assign \pipe1_xer_ca$20 \xer_ca$1 + sync init + end + process $group_51 assign \n_valid_o 1'0 assign \n_valid_o \pipe2_n_valid_o sync init end - process $group_49 + process $group_52 assign \pipe2_n_ready_i 1'0 assign \pipe2_n_ready_i \n_ready_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$41 - process $group_50 - assign \muxid$41 2'00 - assign \muxid$41 \pipe2_muxid$19 + wire width 2 \muxid$44 + process $group_53 + assign \muxid$44 2'00 + assign \muxid$44 \pipe2_muxid$21 sync init end attribute \enum_base_type "MicrOp" @@ -76568,7 +77204,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$42 + wire width 7 \sr_op__insn_type$45 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -76582,73 +77218,75 @@ module \alu_shift_rot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$43 + wire width 11 \sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$44 + wire width 1 \sr_op__imm_data__ok$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$45 + wire width 1 \sr_op__rc__rc$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$46 + wire width 1 \sr_op__rc__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$47 + wire width 1 \sr_op__oe__oe$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$48 + wire width 1 \sr_op__oe__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$49 + wire width 1 \sr_op__write_cr0$53 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$50 + wire width 2 \sr_op__input_carry$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$51 + wire width 1 \sr_op__output_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$52 + wire width 1 \sr_op__input_cr$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$53 + wire width 1 \sr_op__output_cr$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$54 + wire width 1 \sr_op__is_32bit$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$55 + wire width 1 \sr_op__is_signed$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$56 - process $group_51 - assign \sr_op__insn_type$42 7'0000000 - assign \sr_op__fn_unit$43 11'00000000000 - assign \sr_op__imm_data__imm$44 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$45 1'0 - assign \sr_op__rc__rc$46 1'0 - assign \sr_op__rc__rc_ok$47 1'0 - assign \sr_op__oe__oe$48 1'0 - assign \sr_op__oe__oe_ok$49 1'0 - assign { } 0'0 - assign \sr_op__input_carry$50 2'00 - assign \sr_op__output_carry$51 1'0 - assign \sr_op__input_cr$52 1'0 - assign \sr_op__output_cr$53 1'0 - assign \sr_op__is_32bit$54 1'0 - assign \sr_op__is_signed$55 1'0 - assign \sr_op__insn$56 32'00000000000000000000000000000000 - assign { \sr_op__insn$56 \sr_op__is_signed$55 \sr_op__is_32bit$54 \sr_op__output_cr$53 \sr_op__input_cr$52 \sr_op__output_carry$51 \sr_op__input_carry$50 { } { \sr_op__oe__oe_ok$49 \sr_op__oe__oe$48 } { \sr_op__rc__rc_ok$47 \sr_op__rc__rc$46 } { \sr_op__imm_data__imm_ok$45 \sr_op__imm_data__imm$44 } \sr_op__fn_unit$43 \sr_op__insn_type$42 } { \pipe2_sr_op__insn$34 \pipe2_sr_op__is_signed$33 \pipe2_sr_op__is_32bit$32 \pipe2_sr_op__output_cr$31 \pipe2_sr_op__input_cr$30 \pipe2_sr_op__output_carry$29 \pipe2_sr_op__input_carry$28 { } { \pipe2_sr_op__oe__oe_ok$27 \pipe2_sr_op__oe__oe$26 } { \pipe2_sr_op__rc__rc_ok$25 \pipe2_sr_op__rc__rc$24 } { \pipe2_sr_op__imm_data__imm_ok$23 \pipe2_sr_op__imm_data__imm$22 } \pipe2_sr_op__fn_unit$21 \pipe2_sr_op__insn_type$20 } + wire width 32 \sr_op__insn$60 + process $group_54 + assign \sr_op__insn_type$45 7'0000000 + assign \sr_op__fn_unit$46 11'00000000000 + assign \sr_op__imm_data__data$47 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__ok$48 1'0 + assign \sr_op__rc__rc$49 1'0 + assign \sr_op__rc__ok$50 1'0 + assign \sr_op__oe__oe$51 1'0 + assign \sr_op__oe__ok$52 1'0 + assign \sr_op__write_cr0$53 1'0 + assign \sr_op__input_carry$54 2'00 + assign \sr_op__output_carry$55 1'0 + assign \sr_op__input_cr$56 1'0 + assign \sr_op__output_cr$57 1'0 + assign \sr_op__is_32bit$58 1'0 + assign \sr_op__is_signed$59 1'0 + assign \sr_op__insn$60 32'00000000000000000000000000000000 + assign { \sr_op__insn$60 \sr_op__is_signed$59 \sr_op__is_32bit$58 \sr_op__output_cr$57 \sr_op__input_cr$56 \sr_op__output_carry$55 \sr_op__input_carry$54 \sr_op__write_cr0$53 { \sr_op__oe__ok$52 \sr_op__oe__oe$51 } { \sr_op__rc__ok$50 \sr_op__rc__rc$49 } { \sr_op__imm_data__ok$48 \sr_op__imm_data__data$47 } \sr_op__fn_unit$46 \sr_op__insn_type$45 } { \pipe2_sr_op__insn$37 \pipe2_sr_op__is_signed$36 \pipe2_sr_op__is_32bit$35 \pipe2_sr_op__output_cr$34 \pipe2_sr_op__input_cr$33 \pipe2_sr_op__output_carry$32 \pipe2_sr_op__input_carry$31 \pipe2_sr_op__write_cr0$30 { \pipe2_sr_op__oe__ok$29 \pipe2_sr_op__oe__oe$28 } { \pipe2_sr_op__rc__ok$27 \pipe2_sr_op__rc__rc$26 } { \pipe2_sr_op__imm_data__ok$25 \pipe2_sr_op__imm_data__data$24 } \pipe2_sr_op__fn_unit$23 \pipe2_sr_op__insn_type$22 } sync init end - process $group_67 + process $group_70 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o_ok 1'0 - assign { \o_ok \o } { \pipe2_o_ok$36 \pipe2_o$35 } + assign { \o_ok \o } { \pipe2_o_ok$39 \pipe2_o$38 } sync init end - process $group_69 + process $group_72 assign \cr_a 4'0000 assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$38 \pipe2_cr_a$37 } + assign { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$41 \pipe2_cr_a$40 } sync init end - process $group_71 + process $group_74 assign \xer_ca 2'00 assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$40 \pipe2_xer_ca$39 } + assign { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$43 \pipe2_xer_ca$42 } sync init end connect \muxid 2'00 @@ -76656,52 +77294,52 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" module \src_l$116 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src + wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src + wire width 5 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src + wire width 5 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int + wire width 5 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next + wire width 5 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 + wire width 5 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \r_src connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 + wire width 5 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 + wire width 5 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A $3 connect \B \s_src connect \Y $5 @@ -76712,88 +77350,88 @@ module \src_l$116 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 4'0000 + assign \q_int$next 5'00000 end sync init - update \q_int 4'0000 + update \q_int 5'00000 sync posedge \coresync_clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 + wire width 5 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \r_src connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 + wire width 5 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 + wire width 5 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A $9 connect \B \s_src connect \Y $11 end process $group_1 - assign \q_src 4'0000 + assign \q_src 5'00000 assign \q_src $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src + wire width 5 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 + wire width 5 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \q_src connect \Y $13 end process $group_2 - assign \qn_src 4'0000 + assign \qn_src 5'00000 assign \qn_src $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src + wire width 5 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 + wire width 5 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_src 4'0000 + assign \qlq_src 5'00000 assign \qlq_src $15 sync init end @@ -76801,9 +77439,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" module \opc_l$117 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -76946,9 +77584,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" module \req_l$118 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req @@ -77091,9 +77729,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" module \rst_l$119 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -77236,9 +77874,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" module \rok_l$120 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -77381,9 +78019,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" module \alui_l$121 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -77526,9 +78164,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" module \alu_l$122 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -77671,7 +78309,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" module \shiftrot0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -77763,17 +78401,19 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 2 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__imm + wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_shift_rot0__imm_data__imm_ok + wire width 1 input 4 \oper_i_alu_shift_rot0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 5 \oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_shift_rot0__rc__rc_ok + wire width 1 input 6 \oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 7 \oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_shift_rot0__oe__oe_ok + wire width 1 input 8 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -77797,11 +78437,11 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire width 1 output 18 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 19 \cu_rdmaskn_i + wire width 5 input 19 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 20 \cu_rd__rel_o + wire width 5 output 20 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 21 \cu_rd__go_i + wire width 5 input 21 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 22 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" @@ -77809,25 +78449,27 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 24 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 25 \src4_i + wire width 1 input 25 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 26 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \o_ok + wire width 1 output 27 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 27 \cu_wr__rel_o + wire width 3 output 28 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 28 \cu_wr__go_i + wire width 3 input 29 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 29 \dest1_o + wire width 64 output 30 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \cr_a_ok + wire width 1 output 31 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 31 \dest2_o + wire width 4 output 32 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \xer_ca_ok + wire width 1 output 33 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 33 \dest3_o - attribute \src "simple/issuer.py:102" - wire width 1 input 34 \coresync_rst + wire width 2 output 34 \dest3_o + attribute \src "simple/issuer.py:141" + wire width 1 input 35 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \alu_shift_rot0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -77926,29 +78568,33 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 \alu_shift_rot0_sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__imm + wire width 64 \alu_shift_rot0_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__imm$next + wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok + wire width 1 \alu_shift_rot0_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok$next + wire width 1 \alu_shift_rot0_sr_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_shift_rot0_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_shift_rot0_sr_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok + wire width 1 \alu_shift_rot0_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok$next + wire width 1 \alu_shift_rot0_sr_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_shift_rot0_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \alu_shift_rot0_sr_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok + wire width 1 \alu_shift_rot0_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok$next + wire width 1 \alu_shift_rot0_sr_op__write_cr0$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -77994,6 +78640,8 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \alu_shift_rot0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_shift_rot0_xer_ca$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 \alu_shift_rot0_p_valid_i @@ -78009,12 +78657,13 @@ module \shiftrot0 connect \n_ready_i \alu_shift_rot0_n_ready_i connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit - connect \sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data + connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc - connect \sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok + connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe - connect \sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok + connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok + connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr @@ -78028,20 +78677,21 @@ module \shiftrot0 connect \ra \alu_shift_rot0_ra connect \rb \alu_shift_rot0_rb connect \rc \alu_shift_rot0_rc + connect \xer_so \alu_shift_rot0_xer_so connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 connect \p_valid_i \alu_shift_rot0_p_valid_i connect \p_ready_o \alu_shift_rot0_p_ready_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src + wire width 5 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next + wire width 5 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src + wire width 5 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next + wire width 5 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src + wire width 5 \src_l_q_src cell \src_l$116 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -78162,24 +78812,24 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 $4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 $5 + wire width 5 $5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o connect \Y $5 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 $7 + wire width 5 $7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A $5 connect \B \cu_rd__go_i connect \Y $7 @@ -78187,7 +78837,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A $7 connect \Y $4 @@ -78647,22 +79297,22 @@ module \shiftrot0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 4 \reset_r + wire width 5 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 4 $62 + wire width 5 $62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $63 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $62 end process $group_16 - assign \reset_r 4'0000 + assign \reset_r 5'00000 assign \reset_r $62 sync init end @@ -78759,14 +79409,14 @@ module \shiftrot0 end process $group_23 assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_s_src$next 4'0000 + assign \src_l_s_src$next 5'00000 end sync init - update \src_l_s_src 4'0000 + update \src_l_s_src 5'00000 sync posedge \coresync_clk update \src_l_s_src \src_l_s_src$next end @@ -78776,10 +79426,10 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_r_src$next 4'1111 + assign \src_l_r_src$next 5'11111 end sync init - update \src_l_r_src 4'1111 + update \src_l_r_src 5'11111 sync posedge \coresync_clk update \src_l_r_src \src_l_r_src$next end @@ -78838,13 +79488,13 @@ module \shiftrot0 process $group_27 assign \alu_shift_rot0_sr_op__insn_type$next \alu_shift_rot0_sr_op__insn_type assign \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__fn_unit - assign \alu_shift_rot0_sr_op__imm_data__imm$next \alu_shift_rot0_sr_op__imm_data__imm - assign \alu_shift_rot0_sr_op__imm_data__imm_ok$next \alu_shift_rot0_sr_op__imm_data__imm_ok + assign \alu_shift_rot0_sr_op__imm_data__data$next \alu_shift_rot0_sr_op__imm_data__data + assign \alu_shift_rot0_sr_op__imm_data__ok$next \alu_shift_rot0_sr_op__imm_data__ok assign \alu_shift_rot0_sr_op__rc__rc$next \alu_shift_rot0_sr_op__rc__rc - assign \alu_shift_rot0_sr_op__rc__rc_ok$next \alu_shift_rot0_sr_op__rc__rc_ok + assign \alu_shift_rot0_sr_op__rc__ok$next \alu_shift_rot0_sr_op__rc__ok assign \alu_shift_rot0_sr_op__oe__oe$next \alu_shift_rot0_sr_op__oe__oe - assign \alu_shift_rot0_sr_op__oe__oe_ok$next \alu_shift_rot0_sr_op__oe__oe_ok - assign { } { } + assign \alu_shift_rot0_sr_op__oe__ok$next \alu_shift_rot0_sr_op__oe__ok + assign \alu_shift_rot0_sr_op__write_cr0$next \alu_shift_rot0_sr_op__write_cr0 assign \alu_shift_rot0_sr_op__input_carry$next \alu_shift_rot0_sr_op__input_carry assign \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__output_carry assign \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__input_cr @@ -78856,28 +79506,28 @@ module \shiftrot0 switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \alu_shift_rot0_sr_op__insn$next \alu_shift_rot0_sr_op__is_signed$next \alu_shift_rot0_sr_op__is_32bit$next \alu_shift_rot0_sr_op__output_cr$next \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__input_carry$next { } { \alu_shift_rot0_sr_op__oe__oe_ok$next \alu_shift_rot0_sr_op__oe__oe$next } { \alu_shift_rot0_sr_op__rc__rc_ok$next \alu_shift_rot0_sr_op__rc__rc$next } { \alu_shift_rot0_sr_op__imm_data__imm_ok$next \alu_shift_rot0_sr_op__imm_data__imm$next } \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { \alu_shift_rot0_sr_op__insn$next \alu_shift_rot0_sr_op__is_signed$next \alu_shift_rot0_sr_op__is_32bit$next \alu_shift_rot0_sr_op__output_cr$next \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__input_carry$next \alu_shift_rot0_sr_op__write_cr0$next { \alu_shift_rot0_sr_op__oe__ok$next \alu_shift_rot0_sr_op__oe__oe$next } { \alu_shift_rot0_sr_op__rc__ok$next \alu_shift_rot0_sr_op__rc__rc$next } { \alu_shift_rot0_sr_op__imm_data__ok$next \alu_shift_rot0_sr_op__imm_data__data$next } \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__write_cr0 { \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \alu_shift_rot0_sr_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_sr_op__imm_data__imm_ok$next 1'0 + assign \alu_shift_rot0_sr_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_sr_op__imm_data__ok$next 1'0 assign \alu_shift_rot0_sr_op__rc__rc$next 1'0 - assign \alu_shift_rot0_sr_op__rc__rc_ok$next 1'0 + assign \alu_shift_rot0_sr_op__rc__ok$next 1'0 assign \alu_shift_rot0_sr_op__oe__oe$next 1'0 - assign \alu_shift_rot0_sr_op__oe__oe_ok$next 1'0 + assign \alu_shift_rot0_sr_op__oe__ok$next 1'0 end sync init update \alu_shift_rot0_sr_op__insn_type 7'0000000 update \alu_shift_rot0_sr_op__fn_unit 11'00000000000 - update \alu_shift_rot0_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_shift_rot0_sr_op__imm_data__imm_ok 1'0 + update \alu_shift_rot0_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_shift_rot0_sr_op__imm_data__ok 1'0 update \alu_shift_rot0_sr_op__rc__rc 1'0 - update \alu_shift_rot0_sr_op__rc__rc_ok 1'0 + update \alu_shift_rot0_sr_op__rc__ok 1'0 update \alu_shift_rot0_sr_op__oe__oe 1'0 - update \alu_shift_rot0_sr_op__oe__oe_ok 1'0 - update { } 0'0 + update \alu_shift_rot0_sr_op__oe__ok 1'0 + update \alu_shift_rot0_sr_op__write_cr0 1'0 update \alu_shift_rot0_sr_op__input_carry 2'00 update \alu_shift_rot0_sr_op__output_carry 1'0 update \alu_shift_rot0_sr_op__input_cr 1'0 @@ -78888,13 +79538,13 @@ module \shiftrot0 sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type \alu_shift_rot0_sr_op__insn_type$next update \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit$next - update \alu_shift_rot0_sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm$next - update \alu_shift_rot0_sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok$next + update \alu_shift_rot0_sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data$next + update \alu_shift_rot0_sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok$next update \alu_shift_rot0_sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc$next - update \alu_shift_rot0_sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok$next + update \alu_shift_rot0_sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok$next update \alu_shift_rot0_sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe$next - update \alu_shift_rot0_sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok$next - update { } { } + update \alu_shift_rot0_sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok$next + update \alu_shift_rot0_sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0$next update \alu_shift_rot0_sr_op__input_carry \alu_shift_rot0_sr_op__input_carry$next update \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__output_carry$next update \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__input_cr$next @@ -79061,7 +79711,7 @@ module \shiftrot0 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc - connect \S \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \S \alu_shift_rot0_sr_op__imm_data__ok connect \Y $76 end process $group_50 @@ -79077,8 +79727,8 @@ module \shiftrot0 cell $mux $79 parameter \WIDTH 64 connect \A \src2_i - connect \B \alu_shift_rot0_sr_op__imm_data__imm - connect \S \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \B \alu_shift_rot0_sr_op__imm_data__data + connect \S \alu_shift_rot0_sr_op__imm_data__ok connect \Y $78 end process $group_51 @@ -79183,22 +79833,22 @@ module \shiftrot0 update \src_r2 \src_r2$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3 + wire width 1 \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3$next + wire width 1 \src_r3$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $86 + wire width 1 $86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $87 - parameter \WIDTH 2 + parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] connect \Y $86 end process $group_58 - assign \alu_shift_rot0_xer_ca$1 2'00 - assign \alu_shift_rot0_xer_ca$1 $86 + assign \alu_shift_rot0_xer_so 1'0 + assign \alu_shift_rot0_xer_so $86 sync init end process $group_59 @@ -79210,19 +79860,51 @@ module \shiftrot0 assign \src_r3$next \src4_i end sync init - update \src_r3 2'00 + update \src_r3 1'0 sync posedge \coresync_clk update \src_r3 \src_r3$next end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $88 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $89 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $88 + end process $group_60 + assign \alu_shift_rot0_xer_ca$1 2'00 + assign \alu_shift_rot0_xer_ca$1 $88 + sync init + end + process $group_61 + assign \src_r4$next \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [4] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r4$next \src5_i + end + sync init + update \src_r4 2'00 + sync posedge \coresync_clk + update \src_r4 \src_r4$next + end + process $group_62 assign \alu_shift_rot0_p_valid_i 1'0 assign \alu_shift_rot0_p_valid_i \alui_l_q_alui sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $88 + wire width 1 $90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $89 + cell $and $91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79230,11 +79912,11 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $88 + connect \Y $90 end - process $group_61 + process $group_63 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $88 + assign \alui_l_r_alui$next $90 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -79245,20 +79927,20 @@ module \shiftrot0 sync posedge \coresync_clk update \alui_l_r_alui \alui_l_r_alui$next end - process $group_62 + process $group_64 assign \alui_l_s_alui 1'0 assign \alui_l_s_alui \all_rd_pulse sync init end - process $group_63 + process $group_65 assign \alu_shift_rot0_n_ready_i 1'0 assign \alu_shift_rot0_n_ready_i \alu_l_q_alu sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $90 + wire width 1 $92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $91 + cell $and $93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79266,11 +79948,11 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $90 + connect \Y $92 end - process $group_64 + process $group_66 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $90 + assign \alu_l_r_alu$next $92 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -79281,96 +79963,83 @@ module \shiftrot0 sync posedge \coresync_clk update \alu_l_r_alu \alu_l_r_alu$next end - process $group_65 + process $group_67 assign \alu_l_s_alu 1'0 assign \alu_l_s_alu \all_rd_pulse sync init end - process $group_66 + process $group_68 assign \cu_busy_o 1'0 assign \cu_busy_o \opc_l_q_opc sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $92 + wire width 5 $94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $93 + cell $and $95 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $92 + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $94 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $94 + wire width 1 $96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $95 + cell $not $97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_sr_op__imm_data__imm_ok - connect \Y $94 + connect \A \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $96 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $96 + wire width 5 $98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $97 + cell $and $99 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $92 - connect \B { 1'1 1'1 $94 1'1 } - connect \Y $96 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $94 + connect \B { 1'1 1'1 1'1 $96 1'1 } + connect \Y $98 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $98 + wire width 5 $100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $99 + cell $not $101 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $98 + connect \Y $100 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $100 + wire width 5 $102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $101 + cell $and $103 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $96 - connect \B $98 - connect \Y $100 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $98 + connect \B $100 + connect \Y $102 end - process $group_67 - assign \cu_rd__rel_o 4'0000 - assign \cu_rd__rel_o $100 + process $group_69 + assign \cu_rd__rel_o 5'00000 + assign \cu_rd__rel_o $102 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire width 1 \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $102 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire width 1 $104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $105 @@ -79396,41 +80065,54 @@ module \shiftrot0 connect \B \cu_shadown_i connect \Y $106 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $108 + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $108 + wire width 3 $110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $109 + cell $and $111 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req - connect \B { $102 $104 $106 } - connect \Y $108 + connect \B { $104 $106 $108 } + connect \Y $110 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $110 + wire width 3 $112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $111 + cell $and $113 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $108 + connect \A $110 connect \B \cu_wrmask_o - connect \Y $110 + connect \Y $112 end - process $group_68 + process $group_70 assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $110 + assign \cu_wr__rel_o $112 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $112 + wire width 1 $114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $113 + cell $and $115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79438,12 +80120,12 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $112 + connect \Y $114 end - process $group_69 + process $group_71 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $112 } + switch { $114 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] @@ -79451,9 +80133,9 @@ module \shiftrot0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $114 + wire width 1 $116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $115 + cell $and $117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79461,12 +80143,12 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $114 + connect \Y $116 end - process $group_70 + process $group_72 assign \dest2_o 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $114 } + switch { $116 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] @@ -79474,9 +80156,9 @@ module \shiftrot0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $116 + wire width 1 $118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $117 + cell $and $119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79484,12 +80166,12 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $116 + connect \Y $118 end - process $group_71 + process $group_73 assign \dest3_o 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $116 } + switch { $118 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] @@ -79502,9 +80184,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" module \opc_l$123 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -79647,9 +80329,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" module \src_l$124 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src @@ -79792,9 +80474,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" module \alu_l$125 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_alu @@ -79937,9 +80619,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" module \adr_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_adr @@ -80082,9 +80764,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" module \lod_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_lod @@ -80227,9 +80909,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" module \sto_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_sto @@ -80372,9 +81054,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" module \wri_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_wri @@ -80517,9 +81199,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" module \upd_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_upd @@ -80662,9 +81344,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" module \rst_l$126 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -80807,9 +81489,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" module \lsd_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_lsd @@ -80952,7 +81634,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" module \ldst0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 1 output 1 \cu_st__rel_o @@ -81037,91 +81719,107 @@ module \ldst0 attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \oper_i_ldst_ldst0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 6 \oper_i_ldst_ldst0__imm_data__imm + wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_ldst_ldst0__imm_data__imm_ok + wire width 1 input 8 \oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_ldst_ldst0__zero_a + wire width 1 input 9 \oper_i_ldst_ldst0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_ldst_ldst0__rc__rc + wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc_ok + wire width 1 input 11 \oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_ldst_ldst0__oe__oe + wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe_ok + wire width 1 input 13 \oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_ldst_ldst0__is_32bit + wire width 1 input 14 \oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_ldst_ldst0__is_signed + wire width 1 input 15 \oper_i_ldst_ldst0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 15 \oper_i_ldst_ldst0__data_len + wire width 4 input 16 \oper_i_ldst_ldst0__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \oper_i_ldst_ldst0__byte_reverse + wire width 1 input 17 \oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \oper_i_ldst_ldst0__sign_extend + wire width 1 input 18 \oper_i_ldst_ldst0__sign_extend attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 18 \oper_i_ldst_ldst0__ldst_mode + wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 20 \oper_i_ldst_ldst0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 19 \cu_issue_i + wire width 1 input 21 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 20 \cu_busy_o + wire width 1 output 22 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 21 \cu_rdmaskn_i + wire width 3 input 23 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 22 \cu_rd__rel_o + wire width 3 output 24 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 23 \cu_rd__go_i + wire width 3 input 25 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src1_i + wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src2_i + wire width 64 input 27 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src3_i + wire width 64 input 28 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 27 \cu_wr__rel_o + wire width 2 output 29 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 28 \cu_wr__go_i + wire width 2 input 30 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 29 \o + wire width 64 output 31 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \ea - attribute \src "simple/issuer.py:102" - wire width 1 input 31 \coresync_rst + wire width 64 output 32 \ea + attribute \src "simple/issuer.py:141" + wire width 1 input 33 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 input 32 \ldst_port0_busy_o + wire width 1 input 34 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 output 33 \ldst_port0_is_ld_i + wire width 1 output 35 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 output 34 \ldst_port0_is_st_i + wire width 1 output 36 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 35 \ldst_port0_data_len + wire width 4 output 37 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 36 \ldst_port0_addr_i + wire width 96 output 38 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 96 \ldst_port0_addr_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 37 \ldst_port0_addr_i_ok + wire width 1 output 39 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \ldst_port0_addr_i_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 input 38 \ldst_port0_addr_exc_o + wire width 1 input 40 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 input 39 \ldst_port0_addr_ok_o + wire width 1 input 41 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 40 \ldst_port0_ld_data_o + wire width 64 input 42 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 41 \ldst_port0_ld_data_o_ok + wire width 1 input 43 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \ldst_port0_st_data_i + wire width 64 output 44 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \ldst_port0_st_data_i_ok + wire width 1 output 45 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" @@ -82014,14 +82712,30 @@ module \ldst0 assign \rst_l_r_rst \cu_issue_i sync init end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm + wire width 11 \oper_r__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm$next + wire width 64 \oper_r__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 64 \oper_r__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok$next + wire width 1 \oper_r__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \oper_r__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -82031,17 +82745,17 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \oper_r__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 \oper_r__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok$next + wire width 1 \oper_r__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \oper_r__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \oper_r__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 \oper_r__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok$next + wire width 1 \oper_r__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \oper_r__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -82062,73 +82776,83 @@ module \ldst0 wire width 1 \oper_r__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 \oper_r__sign_extend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn$next process $group_34 assign \oper_r__insn_type$next \oper_r__insn_type - assign \oper_r__imm_data__imm$next \oper_r__imm_data__imm - assign \oper_r__imm_data__imm_ok$next \oper_r__imm_data__imm_ok + assign \oper_r__fn_unit$next \oper_r__fn_unit + assign \oper_r__imm_data__data$next \oper_r__imm_data__data + assign \oper_r__imm_data__ok$next \oper_r__imm_data__ok assign \oper_r__zero_a$next \oper_r__zero_a assign \oper_r__rc__rc$next \oper_r__rc__rc - assign \oper_r__rc__rc_ok$next \oper_r__rc__rc_ok + assign \oper_r__rc__ok$next \oper_r__rc__ok assign \oper_r__oe__oe$next \oper_r__oe__oe - assign \oper_r__oe__oe_ok$next \oper_r__oe__oe_ok + assign \oper_r__oe__ok$next \oper_r__oe__ok assign \oper_r__is_32bit$next \oper_r__is_32bit assign \oper_r__is_signed$next \oper_r__is_signed assign \oper_r__data_len$next \oper_r__data_len assign \oper_r__byte_reverse$next \oper_r__byte_reverse assign \oper_r__sign_extend$next \oper_r__sign_extend assign \oper_r__ldst_mode$next \oper_r__ldst_mode + assign \oper_r__insn$next \oper_r__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" switch { \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" case 1'1 - assign { \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__oe_ok$next \oper_r__oe__oe$next } { \oper_r__rc__rc_ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__imm_ok$next \oper_r__imm_data__imm$next } \oper_r__insn_type$next } { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type } + assign { \oper_r__insn$next \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__ok$next \oper_r__oe__oe$next } { \oper_r__rc__ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__ok$next \oper_r__imm_data__data$next } \oper_r__fn_unit$next \oper_r__insn_type$next } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data } \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" switch { \cu_done_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" case 1'1 - assign { \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__oe_ok$next \oper_r__oe__oe$next } { \oper_r__rc__rc_ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__imm_ok$next \oper_r__imm_data__imm$next } \oper_r__insn_type$next } 87'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { \oper_r__insn$next \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__ok$next \oper_r__oe__oe$next } { \oper_r__rc__ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__ok$next \oper_r__imm_data__data$next } \oper_r__fn_unit$next \oper_r__insn_type$next } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \oper_r__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok$next 1'0 + assign \oper_r__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_r__imm_data__ok$next 1'0 assign \oper_r__rc__rc$next 1'0 - assign \oper_r__rc__rc_ok$next 1'0 + assign \oper_r__rc__ok$next 1'0 assign \oper_r__oe__oe$next 1'0 - assign \oper_r__oe__oe_ok$next 1'0 + assign \oper_r__oe__ok$next 1'0 end sync init update \oper_r__insn_type 7'0000000 - update \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_r__imm_data__imm_ok 1'0 + update \oper_r__fn_unit 11'00000000000 + update \oper_r__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_r__imm_data__ok 1'0 update \oper_r__zero_a 1'0 update \oper_r__rc__rc 1'0 - update \oper_r__rc__rc_ok 1'0 + update \oper_r__rc__ok 1'0 update \oper_r__oe__oe 1'0 - update \oper_r__oe__oe_ok 1'0 + update \oper_r__oe__ok 1'0 update \oper_r__is_32bit 1'0 update \oper_r__is_signed 1'0 update \oper_r__data_len 4'0000 update \oper_r__byte_reverse 1'0 update \oper_r__sign_extend 1'0 update \oper_r__ldst_mode 2'00 + update \oper_r__insn 32'00000000000000000000000000000000 sync posedge \coresync_clk update \oper_r__insn_type \oper_r__insn_type$next - update \oper_r__imm_data__imm \oper_r__imm_data__imm$next - update \oper_r__imm_data__imm_ok \oper_r__imm_data__imm_ok$next + update \oper_r__fn_unit \oper_r__fn_unit$next + update \oper_r__imm_data__data \oper_r__imm_data__data$next + update \oper_r__imm_data__ok \oper_r__imm_data__ok$next update \oper_r__zero_a \oper_r__zero_a$next update \oper_r__rc__rc \oper_r__rc__rc$next - update \oper_r__rc__rc_ok \oper_r__rc__rc_ok$next + update \oper_r__rc__ok \oper_r__rc__ok$next update \oper_r__oe__oe \oper_r__oe__oe$next - update \oper_r__oe__oe_ok \oper_r__oe__oe_ok$next + update \oper_r__oe__ok \oper_r__oe__ok$next update \oper_r__is_32bit \oper_r__is_32bit$next update \oper_r__is_signed \oper_r__is_signed$next update \oper_r__data_len \oper_r__data_len$next update \oper_r__byte_reverse \oper_r__byte_reverse$next update \oper_r__sign_extend \oper_r__sign_extend$next update \oper_r__ldst_mode \oper_r__ldst_mode$next + update \oper_r__insn \oper_r__insn$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" wire width 64 \ldd_r @@ -82148,12 +82872,12 @@ module \ldst0 connect \S \ld_ok connect \Y $58 end - process $group_48 + process $group_50 assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000 assign \ldd_r $58 sync init end - process $group_49 + process $group_51 assign \ldo_r$next \ldo_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \ld_ok } @@ -82170,7 +82894,7 @@ module \ldst0 wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" wire width 64 \src_r0$next - process $group_50 + process $group_52 assign \src_r0$next \src_r0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" switch { \cu_rd__go_i [0] } @@ -82193,7 +82917,7 @@ module \ldst0 wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" wire width 64 \src_r1$next - process $group_51 + process $group_53 assign \src_r1$next \src_r1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" switch { \cu_rd__go_i [1] } @@ -82216,7 +82940,7 @@ module \ldst0 wire width 64 \src_r2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" wire width 64 \src_r2$next - process $group_52 + process $group_54 assign \src_r2$next \src_r2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" switch { \cu_rd__go_i [2] } @@ -82253,12 +82977,12 @@ module \ldst0 connect \S \alu_l_q_alu connect \Y $60 end - process $group_53 + process $group_55 assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000 assign \addr_r $60 sync init end - process $group_54 + process $group_56 assign \ea_r$next \ea_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \alu_l_q_alu } @@ -82283,7 +83007,7 @@ module \ldst0 connect \S \oper_r__zero_a connect \Y $62 end - process $group_55 + process $group_57 assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src1_or_z $62 sync init @@ -82296,11 +83020,11 @@ module \ldst0 cell $mux $65 parameter \WIDTH 64 connect \A \src_r1 - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok connect \Y $64 end - process $group_56 + process $group_58 assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src2_or_imm $64 sync init @@ -82321,12 +83045,12 @@ module \ldst0 connect \Y $67 end connect $66 $67 - process $group_57 + process $group_59 assign \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \alu_o $66 [63:0] sync init end - process $group_58 + process $group_60 assign \alu_ok$next \alu_ok assign \alu_ok$next \alu_valid sync init @@ -82334,7 +83058,7 @@ module \ldst0 sync posedge \coresync_clk update \alu_ok \alu_ok$next end - process $group_59 + process $group_61 assign \cu_busy_o 1'0 assign \cu_busy_o \opc_l_q_opc sync init @@ -82359,7 +83083,7 @@ module \ldst0 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a } + connect \A { \oper_r__imm_data__ok \oper_r__zero_a } connect \Y $71 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" @@ -82424,7 +83148,7 @@ module \ldst0 connect \B \op_is_st connect \Y $81 end - process $group_60 + process $group_62 assign \cu_rd__rel_o 3'000 assign \cu_rd__rel_o $77 assign \cu_rd__rel_o [2] $81 @@ -82443,7 +83167,7 @@ module \ldst0 connect \B \cu_rd__go_i [1] connect \Y $83 end - process $group_61 + process $group_63 assign \rda_any 1'0 assign \rda_any $83 sync init @@ -82484,7 +83208,7 @@ module \ldst0 connect \B $85 connect \Y $89 end - process $group_62 + process $group_64 assign \alu_valid 1'0 assign \alu_valid $89 sync init @@ -82514,7 +83238,7 @@ module \ldst0 connect \B $91 connect \Y $93 end - process $group_63 + process $group_65 assign \rd_done 1'0 assign \rd_done $93 sync init @@ -82545,7 +83269,7 @@ module \ldst0 connect \B \cu_busy_o connect \Y $97 end - process $group_64 + process $group_66 assign \cu_ad__rel_o 1'0 assign \cu_ad__rel_o $97 sync init @@ -82604,7 +83328,7 @@ module \ldst0 connect \B \cu_shadown_i connect \Y $105 end - process $group_65 + process $group_67 assign \cu_st__rel_o 1'0 assign \cu_st__rel_o $105 sync init @@ -82739,7 +83463,7 @@ module \ldst0 connect \B \cu_shadown_i connect \Y $125 end - process $group_66 + process $group_68 assign \cu_wr__rel_o 2'00 assign \cu_wr__rel_o [0] $115 assign \cu_wr__rel_o [1] $125 @@ -82786,7 +83510,7 @@ module \ldst0 connect \B \cu_wr__go_i [1] connect \Y $131 end - process $group_67 + process $group_69 assign \wr_any 1'0 assign \wr_any $131 sync init @@ -82892,7 +83616,7 @@ module \ldst0 connect \B $145 connect \Y $147 end - process $group_68 + process $group_70 assign \wr_reset 1'0 assign \wr_reset $147 sync init @@ -82933,19 +83657,19 @@ module \ldst0 connect \B $151 connect \Y $153 end - process $group_69 + process $group_71 assign \cu_done_o 1'0 assign \cu_done_o $153 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest1_o - process $group_70 + process $group_72 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o \dest1_o sync init end - process $group_71 + process $group_73 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" switch { \cu_wr__go_i [0] } @@ -82957,7 +83681,7 @@ module \ldst0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest2_o - process $group_72 + process $group_74 assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000 assign \ea \dest2_o sync init @@ -82988,7 +83712,7 @@ module \ldst0 connect \B \cu_wr__go_i [1] connect \Y $157 end - process $group_73 + process $group_75 assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" switch { $157 } @@ -83029,7 +83753,7 @@ module \ldst0 connect \Y $162 end connect $159 $162 - process $group_74 + process $group_76 assign \cu_wrmask_o 2'00 assign \cu_wrmask_o $159 [1:0] sync init @@ -83047,7 +83771,7 @@ module \ldst0 connect \B \cu_busy_o connect \Y $164 end - process $group_75 + process $group_77 assign \ldst_port0_is_ld_i 1'0 assign \ldst_port0_is_ld_i $164 sync init @@ -83065,12 +83789,12 @@ module \ldst0 connect \B \cu_busy_o connect \Y $166 end - process $group_76 + process $group_78 assign \ldst_port0_is_st_i 1'0 assign \ldst_port0_is_st_i $166 sync init end - process $group_77 + process $group_79 assign \ldst_port0_data_len 4'0000 assign \ldst_port0_data_len \oper_r__data_len sync init @@ -83085,7 +83809,7 @@ module \ldst0 connect \A \addr_r connect \Y $168 end - process $group_78 + process $group_80 assign \ldst_port0_addr_i$next \ldst_port0_addr_i assign \ldst_port0_addr_i$next $168 sync init @@ -83106,7 +83830,7 @@ module \ldst0 connect \B \lsd_l_q_lsd connect \Y $170 end - process $group_79 + process $group_81 assign \ldst_port0_addr_i_ok$next \ldst_port0_addr_i_ok assign \ldst_port0_addr_i_ok$next $170 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -83121,12 +83845,12 @@ module \ldst0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:107" wire width 1 \addr_exc_o - process $group_80 + process $group_82 assign \addr_exc_o 1'0 assign \addr_exc_o \ldst_port0_addr_exc_o sync init end - process $group_81 + process $group_83 assign \addr_ok 1'0 assign \addr_ok \ldst_port0_addr_ok_o sync init @@ -83163,7 +83887,7 @@ module \ldst0 connect \A { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } connect \Y $176 end - process $group_82 + process $group_84 assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" switch { \oper_r__byte_reverse } @@ -83191,7 +83915,7 @@ module \ldst0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" wire width 64 \revnorev - process $group_83 + process $group_85 assign \revnorev 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" switch { \oper_r__byte_reverse } @@ -83204,20 +83928,41 @@ module \ldst0 end sync init end - process $group_84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + wire width 1 $178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + cell $eq $179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__data_len + connect \B 2'10 + connect \Y $178 + end + process $group_86 assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" switch { \oper_r__sign_extend } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" case 1'1 - assign \ldd_o { { \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] } \revnorev [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + switch { $178 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + case 1'1 + assign \ldd_o { { \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] } \revnorev [15:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" + case + assign \ldd_o { { \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] } \revnorev [31:0] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:514" case assign \ldd_o \revnorev end sync init end - process $group_85 + process $group_87 assign \ld_ok 1'0 assign \ld_ok \ldst_port0_ld_data_o_ok sync init @@ -83225,75 +83970,75 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" wire width 64 \stdata_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $178 + wire width 64 $180 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $179 + cell $pos $181 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A { \src_r2 [7:0] } - connect \Y $178 + connect \Y $180 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $180 + wire width 64 $182 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $181 + cell $pos $183 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A { \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $180 + connect \Y $182 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $182 + wire width 64 $184 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $183 + cell $pos $185 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $182 + connect \Y $184 end - process $group_86 + process $group_88 assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" switch { \oper_r__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" case 1'1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" switch \oper_r__data_len attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" case 4'0001 - assign \stdata_r $178 + assign \stdata_r $180 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" case 4'0010 - assign \stdata_r $180 + assign \stdata_r $182 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" case 4'0100 - assign \stdata_r $182 + assign \stdata_r $184 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" case 4'1000 assign \stdata_r { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:527" case end sync init end - process $group_87 + process $group_89 assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" switch { \oper_r__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" case 1'1 assign \ldst_port0_st_data_i \stdata_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:527" case assign \ldst_port0_st_data_i \src_r2 end sync init end - process $group_88 + process $group_90 assign \ldst_port0_st_data_i_ok 1'0 assign \ldst_port0_st_data_i_ok \cu_st__go_i sync init @@ -83304,7 +84049,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus" module \fus - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 1 output 1 \cu_st__rel_o @@ -83404,17 +84149,17 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 11 input 6 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \oper_i_alu_alu0__imm_data__imm + wire width 64 input 7 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_alu0__imm_data__imm_ok + wire width 1 input 8 \oper_i_alu_alu0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 9 \oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_alu0__rc__rc_ok + wire width 1 input 10 \oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 11 \oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_alu0__oe__oe_ok + wire width 1 input 12 \oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 13 \oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -83536,18 +84281,14 @@ module \fus wire width 11 input 27 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 28 \oper_i_alu_cr0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 29 \oper_i_alu_cr0__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 30 \oper_i_alu_cr0__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 31 \cu_issue_i$1 + wire width 1 input 29 \cu_issue_i$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 32 \cu_busy_o$2 + wire width 1 output 30 \cu_busy_o$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 33 \cu_rdmaskn_i$3 + wire width 6 input 31 \cu_rdmaskn_i$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 34 \oper_i_alu_branch0__cia + wire width 64 input 32 \oper_i_alu_branch0__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -83622,7 +84363,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 35 \oper_i_alu_branch0__insn_type + wire width 7 input 33 \oper_i_alu_branch0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83636,23 +84377,23 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 36 \oper_i_alu_branch0__fn_unit + wire width 11 input 34 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 37 \oper_i_alu_branch0__insn + wire width 32 input 35 \oper_i_alu_branch0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \oper_i_alu_branch0__imm_data__imm + wire width 64 input 36 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 39 \oper_i_alu_branch0__imm_data__imm_ok + wire width 1 input 37 \oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 40 \oper_i_alu_branch0__lk + wire width 1 input 38 \oper_i_alu_branch0__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 41 \oper_i_alu_branch0__is_32bit + wire width 1 input 39 \oper_i_alu_branch0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 42 \cu_issue_i$4 + wire width 1 input 40 \cu_issue_i$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 43 \cu_busy_o$5 + wire width 1 output 41 \cu_busy_o$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 44 \cu_rdmaskn_i$6 + wire width 3 input 42 \cu_rdmaskn_i$6 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -83727,7 +84468,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 45 \oper_i_alu_trap0__insn_type + wire width 7 input 43 \oper_i_alu_trap0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83741,25 +84482,25 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 46 \oper_i_alu_trap0__fn_unit + wire width 11 input 44 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 47 \oper_i_alu_trap0__insn + wire width 32 input 45 \oper_i_alu_trap0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 48 \oper_i_alu_trap0__msr + wire width 64 input 46 \oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 49 \oper_i_alu_trap0__cia + wire width 64 input 47 \oper_i_alu_trap0__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 50 \oper_i_alu_trap0__is_32bit + wire width 1 input 48 \oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 51 \oper_i_alu_trap0__traptype + wire width 7 input 49 \oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 52 \oper_i_alu_trap0__trapaddr + wire width 13 input 50 \oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 53 \cu_issue_i$7 + wire width 1 input 51 \cu_issue_i$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 54 \cu_busy_o$8 + wire width 1 output 52 \cu_busy_o$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 55 \cu_rdmaskn_i$9 + wire width 4 input 53 \cu_rdmaskn_i$9 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -83834,7 +84575,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 56 \oper_i_alu_logical0__insn_type + wire width 7 input 54 \oper_i_alu_logical0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83848,49 +84589,49 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 57 \oper_i_alu_logical0__fn_unit + wire width 11 input 55 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 58 \oper_i_alu_logical0__imm_data__imm + wire width 64 input 56 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 59 \oper_i_alu_logical0__imm_data__imm_ok + wire width 1 input 57 \oper_i_alu_logical0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 60 \oper_i_alu_logical0__rc__rc + wire width 1 input 58 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 61 \oper_i_alu_logical0__rc__rc_ok + wire width 1 input 59 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 62 \oper_i_alu_logical0__oe__oe + wire width 1 input 60 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 63 \oper_i_alu_logical0__oe__oe_ok + wire width 1 input 61 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 64 \oper_i_alu_logical0__invert_in + wire width 1 input 62 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 65 \oper_i_alu_logical0__zero_a + wire width 1 input 63 \oper_i_alu_logical0__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 66 \oper_i_alu_logical0__input_carry + wire width 2 input 64 \oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 67 \oper_i_alu_logical0__invert_out + wire width 1 input 65 \oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 68 \oper_i_alu_logical0__write_cr0 + wire width 1 input 66 \oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 69 \oper_i_alu_logical0__output_carry + wire width 1 input 67 \oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 70 \oper_i_alu_logical0__is_32bit + wire width 1 input 68 \oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 71 \oper_i_alu_logical0__is_signed + wire width 1 input 69 \oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 72 \oper_i_alu_logical0__data_len + wire width 4 input 70 \oper_i_alu_logical0__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 73 \oper_i_alu_logical0__insn + wire width 32 input 71 \oper_i_alu_logical0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 74 \cu_issue_i$10 + wire width 1 input 72 \cu_issue_i$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 75 \cu_busy_o$11 + wire width 1 output 73 \cu_busy_o$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 2 input 76 \cu_rdmaskn_i$12 + wire width 3 input 74 \cu_rdmaskn_i$12 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -83965,7 +84706,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 77 \oper_i_alu_spr0__insn_type + wire width 7 input 75 \oper_i_alu_spr0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83979,17 +84720,17 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 78 \oper_i_alu_spr0__fn_unit + wire width 11 input 76 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 79 \oper_i_alu_spr0__insn + wire width 32 input 77 \oper_i_alu_spr0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 80 \oper_i_alu_spr0__is_32bit + wire width 1 input 78 \oper_i_alu_spr0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 81 \cu_issue_i$13 + wire width 1 input 79 \cu_issue_i$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 82 \cu_busy_o$14 + wire width 1 output 80 \cu_busy_o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 83 \cu_rdmaskn_i$15 + wire width 6 input 81 \cu_rdmaskn_i$15 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84064,7 +84805,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 84 \oper_i_alu_div0__insn_type + wire width 7 input 82 \oper_i_alu_div0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84078,49 +84819,49 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 85 \oper_i_alu_div0__fn_unit + wire width 11 input 83 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 86 \oper_i_alu_div0__imm_data__imm + wire width 64 input 84 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 87 \oper_i_alu_div0__imm_data__imm_ok + wire width 1 input 85 \oper_i_alu_div0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 88 \oper_i_alu_div0__rc__rc + wire width 1 input 86 \oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 89 \oper_i_alu_div0__rc__rc_ok + wire width 1 input 87 \oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 90 \oper_i_alu_div0__oe__oe + wire width 1 input 88 \oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 91 \oper_i_alu_div0__oe__oe_ok + wire width 1 input 89 \oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 92 \oper_i_alu_div0__invert_in + wire width 1 input 90 \oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 93 \oper_i_alu_div0__zero_a + wire width 1 input 91 \oper_i_alu_div0__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 94 \oper_i_alu_div0__input_carry + wire width 2 input 92 \oper_i_alu_div0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 95 \oper_i_alu_div0__invert_out + wire width 1 input 93 \oper_i_alu_div0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 96 \oper_i_alu_div0__write_cr0 + wire width 1 input 94 \oper_i_alu_div0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 97 \oper_i_alu_div0__output_carry + wire width 1 input 95 \oper_i_alu_div0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 98 \oper_i_alu_div0__is_32bit + wire width 1 input 96 \oper_i_alu_div0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 99 \oper_i_alu_div0__is_signed + wire width 1 input 97 \oper_i_alu_div0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 100 \oper_i_alu_div0__data_len + wire width 4 input 98 \oper_i_alu_div0__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 101 \oper_i_alu_div0__insn + wire width 32 input 99 \oper_i_alu_div0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 102 \cu_issue_i$16 + wire width 1 input 100 \cu_issue_i$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 103 \cu_busy_o$17 + wire width 1 output 101 \cu_busy_o$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 104 \cu_rdmaskn_i$18 + wire width 3 input 102 \cu_rdmaskn_i$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84195,7 +84936,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 105 \oper_i_alu_mul0__insn_type + wire width 7 input 103 \oper_i_alu_mul0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84209,33 +84950,33 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 106 \oper_i_alu_mul0__fn_unit + wire width 11 input 104 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 107 \oper_i_alu_mul0__imm_data__imm + wire width 64 input 105 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 108 \oper_i_alu_mul0__imm_data__imm_ok + wire width 1 input 106 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 109 \oper_i_alu_mul0__rc__rc + wire width 1 input 107 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 110 \oper_i_alu_mul0__rc__rc_ok + wire width 1 input 108 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 111 \oper_i_alu_mul0__oe__oe + wire width 1 input 109 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 112 \oper_i_alu_mul0__oe__oe_ok + wire width 1 input 110 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 113 \oper_i_alu_mul0__write_cr0 + wire width 1 input 111 \oper_i_alu_mul0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 114 \oper_i_alu_mul0__is_32bit + wire width 1 input 112 \oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 115 \oper_i_alu_mul0__is_signed + wire width 1 input 113 \oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 116 \oper_i_alu_mul0__insn + wire width 32 input 114 \oper_i_alu_mul0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 117 \cu_issue_i$19 + wire width 1 input 115 \cu_issue_i$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 118 \cu_busy_o$20 + wire width 1 output 116 \cu_busy_o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 119 \cu_rdmaskn_i$21 + wire width 3 input 117 \cu_rdmaskn_i$21 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84310,7 +85051,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type + wire width 7 input 118 \oper_i_alu_shift_rot0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84324,43 +85065,45 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 121 \oper_i_alu_shift_rot0__fn_unit + wire width 11 input 119 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__imm + wire width 64 input 120 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 123 \oper_i_alu_shift_rot0__imm_data__imm_ok + wire width 1 input 121 \oper_i_alu_shift_rot0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 124 \oper_i_alu_shift_rot0__rc__rc + wire width 1 input 122 \oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 125 \oper_i_alu_shift_rot0__rc__rc_ok + wire width 1 input 123 \oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 126 \oper_i_alu_shift_rot0__oe__oe + wire width 1 input 124 \oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 127 \oper_i_alu_shift_rot0__oe__oe_ok + wire width 1 input 125 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 126 \oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 129 \oper_i_alu_shift_rot0__input_carry + wire width 2 input 127 \oper_i_alu_shift_rot0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 130 \oper_i_alu_shift_rot0__output_carry + wire width 1 input 128 \oper_i_alu_shift_rot0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 131 \oper_i_alu_shift_rot0__input_cr + wire width 1 input 129 \oper_i_alu_shift_rot0__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 132 \oper_i_alu_shift_rot0__output_cr + wire width 1 input 130 \oper_i_alu_shift_rot0__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 133 \oper_i_alu_shift_rot0__is_32bit + wire width 1 input 131 \oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 134 \oper_i_alu_shift_rot0__is_signed + wire width 1 input 132 \oper_i_alu_shift_rot0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 135 \oper_i_alu_shift_rot0__insn + wire width 32 input 133 \oper_i_alu_shift_rot0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 136 \cu_issue_i$22 + wire width 1 input 134 \cu_issue_i$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 137 \cu_busy_o$23 + wire width 1 output 135 \cu_busy_o$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 138 \cu_rdmaskn_i$24 + wire width 5 input 136 \cu_rdmaskn_i$24 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84435,38 +85178,54 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 139 \oper_i_ldst_ldst0__insn_type + wire width 7 input 137 \oper_i_ldst_ldst0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 138 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 140 \oper_i_ldst_ldst0__imm_data__imm + wire width 64 input 139 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 141 \oper_i_ldst_ldst0__imm_data__imm_ok + wire width 1 input 140 \oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 142 \oper_i_ldst_ldst0__zero_a + wire width 1 input 141 \oper_i_ldst_ldst0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 143 \oper_i_ldst_ldst0__rc__rc + wire width 1 input 142 \oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 144 \oper_i_ldst_ldst0__rc__rc_ok + wire width 1 input 143 \oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 145 \oper_i_ldst_ldst0__oe__oe + wire width 1 input 144 \oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 146 \oper_i_ldst_ldst0__oe__oe_ok + wire width 1 input 145 \oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 147 \oper_i_ldst_ldst0__is_32bit + wire width 1 input 146 \oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 148 \oper_i_ldst_ldst0__is_signed + wire width 1 input 147 \oper_i_ldst_ldst0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 149 \oper_i_ldst_ldst0__data_len + wire width 4 input 148 \oper_i_ldst_ldst0__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 150 \oper_i_ldst_ldst0__byte_reverse + wire width 1 input 149 \oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 151 \oper_i_ldst_ldst0__sign_extend + wire width 1 input 150 \oper_i_ldst_ldst0__sign_extend attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 152 \oper_i_ldst_ldst0__ldst_mode + wire width 2 input 151 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 152 \oper_i_ldst_ldst0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 input 153 \cu_issue_i$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" @@ -84492,9 +85251,9 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 164 \src1_i$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 165 \cu_rd__rel_o$34 + wire width 3 output 165 \cu_rd__rel_o$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 166 \cu_rd__go_i$35 + wire width 3 input 166 \cu_rd__go_i$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 167 \src1_i$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" @@ -84516,9 +85275,9 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 176 \src1_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 177 \cu_rd__rel_o$46 + wire width 5 output 177 \cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 178 \cu_rd__go_i$47 + wire width 5 input 178 \cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 179 \src1_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" @@ -84550,103 +85309,103 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 1 input 193 \src3_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 input 194 \src4_i + wire width 1 input 194 \src3_i$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 input 195 \src3_i$61 + wire width 1 input 195 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 1 input 196 \src3_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 197 \src4_i$63 + wire width 1 input 197 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 198 \src4_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 198 \src6_i + wire width 2 input 199 \src4_i$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 199 \src4_i$64 + wire width 2 input 200 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 200 \src5_i + wire width 2 input 201 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 201 \src3_i$65 + wire width 2 input 202 \src5_i$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 202 \src4_i$66 + wire width 32 input 203 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 204 \src4_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 203 \cu_rd__rel_o$67 + wire width 3 output 205 \cu_rd__rel_o$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 204 \cu_rd__go_i$68 + wire width 3 input 206 \cu_rd__go_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 205 \src3_i$69 + wire width 4 input 207 \src3_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 206 \src5_i$70 + wire width 4 input 208 \src5_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 207 \src6_i$71 + wire width 4 input 209 \src6_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 208 \src1_i$72 + wire width 64 input 210 \src1_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 209 \src3_i$73 + wire width 64 input 211 \src3_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 210 \src3_i$74 + wire width 64 input 212 \src3_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 211 \src2_i$75 + wire width 64 input 213 \src2_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 212 \src4_i$76 + wire width 64 input 214 \src4_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 213 \src2_i$77 + wire width 64 input 215 \src2_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 214 \o_ok + wire width 1 output 216 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 215 \cu_wr__rel_o + wire width 5 output 217 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 216 \cu_wr__go_i + wire width 5 input 218 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 217 \o_ok$78 + wire width 1 output 219 \o_ok$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 218 \cu_wr__rel_o$79 + wire width 3 output 220 \cu_wr__rel_o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 219 \cu_wr__go_i$80 + wire width 3 input 221 \cu_wr__go_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 220 \o_ok$81 + wire width 1 output 222 \o_ok$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 221 \cu_wr__rel_o$82 + wire width 5 output 223 \cu_wr__rel_o$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 222 \cu_wr__go_i$83 + wire width 5 input 224 \cu_wr__go_i$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 223 \o_ok$84 + wire width 1 output 225 \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 224 \cu_wr__rel_o$85 + wire width 2 output 226 \cu_wr__rel_o$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 225 \cu_wr__go_i$86 + wire width 2 input 227 \cu_wr__go_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 226 \o_ok$87 + wire width 1 output 228 \o_ok$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 227 \cu_wr__rel_o$88 + wire width 6 output 229 \cu_wr__rel_o$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 228 \cu_wr__go_i$89 + wire width 6 input 230 \cu_wr__go_i$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 229 \o_ok$90 + wire width 1 output 231 \o_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 230 \cu_wr__rel_o$91 + wire width 4 output 232 \cu_wr__rel_o$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 231 \cu_wr__go_i$92 + wire width 4 input 233 \cu_wr__go_i$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 232 \o_ok$93 + wire width 1 output 234 \o_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 233 \cu_wr__rel_o$94 + wire width 4 output 235 \cu_wr__rel_o$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 234 \cu_wr__go_i$95 + wire width 4 input 236 \cu_wr__go_i$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 235 \o_ok$96 + wire width 1 output 237 \o_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 236 \cu_wr__rel_o$97 + wire width 3 output 238 \cu_wr__rel_o$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 237 \cu_wr__go_i$98 + wire width 3 input 239 \cu_wr__go_i$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 238 \cu_wr__rel_o$99 + wire width 2 output 240 \cu_wr__rel_o$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 239 \cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 240 \dest1_o + wire width 2 input 241 \cu_wr__go_i$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 241 \dest1_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 242 \dest1_o$102 + wire width 64 output 242 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 243 \dest1_o$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" @@ -84657,48 +85416,48 @@ module \fus wire width 64 output 246 \dest1_o$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 247 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 248 \o + wire width 64 output 250 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 249 \ea + wire width 64 output 251 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 250 \full_cr_ok + wire width 1 output 252 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 251 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 252 \cr_a_ok + wire width 32 output 253 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 253 \cr_a_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 254 \cr_a_ok$109 + wire width 1 output 254 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 255 \cr_a_ok$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 256 \cr_a_ok$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 257 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 258 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 259 \cr_a_ok$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 258 \dest2_o$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 259 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 260 \dest2_o$114 + wire width 4 output 260 \dest2_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 261 \dest2_o$115 + wire width 4 output 261 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 262 \dest2_o$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 263 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 264 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 265 \xer_ca_ok$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 266 \xer_ca_ok$119 + wire width 1 output 266 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 267 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 268 \dest3_o$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 268 \xer_ca_ok$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 269 \dest3_o$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" @@ -84777,7 +85536,7 @@ module \fus wire width 1 output 306 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 307 \dest2_o$150 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 308 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire width 1 input 309 \ldst_port0_busy_o @@ -84807,12 +85566,12 @@ module \fus connect \coresync_clk \coresync_clk connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__imm \oper_i_alu_alu0__imm_data__imm - connect \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm_ok + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc_ok + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe_ok + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out @@ -84831,15 +85590,15 @@ module \fus connect \src1_i \src1_i connect \src2_i \src2_i connect \src3_i \src3_i$60 - connect \src4_i \src4_i$63 + connect \src4_i \src4_i$65 connect \o_ok \o_ok connect \cu_wr__rel_o \cu_wr__rel_o connect \cu_wr__go_i \cu_wr__go_i connect \dest1_o \dest1_o connect \cr_a_ok \cr_a_ok - connect \dest2_o \dest2_o$113 + connect \dest2_o \dest2_o$115 connect \xer_ca_ok \xer_ca_ok - connect \dest3_o \dest3_o$121 + connect \dest3_o \dest3_o$122 connect \xer_ov_ok \xer_ov_ok connect \dest4_o \dest4_o connect \xer_so_ok \xer_so_ok @@ -84851,8 +85610,6 @@ module \fus connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole - connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole connect \cu_issue_i \cu_issue_i$1 connect \cu_busy_o \cu_busy_o$2 connect \cu_rdmaskn_i \cu_rdmaskn_i$3 @@ -84860,17 +85617,17 @@ module \fus connect \cu_rd__go_i \cu_rd__go_i$29 connect \src1_i \src1_i$30 connect \src2_i \src2_i$52 - connect \src3_i \src3_i$65 - connect \src4_i \src4_i$66 - connect \src5_i \src5_i$70 - connect \src6_i \src6_i$71 - connect \o_ok \o_ok$78 - connect \cu_wr__rel_o \cu_wr__rel_o$79 - connect \cu_wr__go_i \cu_wr__go_i$80 - connect \dest1_o \dest1_o$101 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 + connect \o_ok \o_ok$80 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \dest1_o \dest1_o$103 connect \full_cr_ok \full_cr_ok connect \dest2_o \dest2_o - connect \cr_a_ok \cr_a_ok$108 + connect \cr_a_ok \cr_a_ok$110 connect \dest3_o \dest3_o connect \coresync_rst \coresync_rst end @@ -84880,18 +85637,18 @@ module \fus connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__imm_data__imm \oper_i_alu_branch0__imm_data__imm - connect \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm_ok + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit connect \cu_issue_i \cu_issue_i$4 connect \cu_busy_o \cu_busy_o$5 connect \cu_rdmaskn_i \cu_rdmaskn_i$6 - connect \cu_rd__rel_o \cu_rd__rel_o$67 - connect \cu_rd__go_i \cu_rd__go_i$68 - connect \src3_i \src3_i$69 - connect \src1_i \src1_i$72 - connect \src2_i \src2_i$75 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \src3_i \src3_i$71 + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 connect \fast1_ok \fast1_ok connect \cu_wr__rel_o \cu_wr__rel_o$136 connect \cu_wr__go_i \cu_wr__go_i$137 @@ -84919,12 +85676,12 @@ module \fus connect \cu_rd__go_i \cu_rd__go_i$32 connect \src1_i \src1_i$33 connect \src2_i \src2_i$53 - connect \src3_i \src3_i$73 - connect \src4_i \src4_i$76 - connect \o_ok \o_ok$81 - connect \cu_wr__rel_o \cu_wr__rel_o$82 - connect \cu_wr__go_i \cu_wr__go_i$83 - connect \dest1_o \dest1_o$102 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 + connect \o_ok \o_ok$83 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \dest1_o \dest1_o$104 connect \fast1_ok \fast1_ok$138 connect \fast2_ok \fast2_ok$140 connect \dest2_o \dest2_o$142 @@ -84939,12 +85696,12 @@ module \fus connect \coresync_clk \coresync_clk connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__imm \oper_i_alu_logical0__imm_data__imm - connect \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm_ok + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc_ok + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe_ok + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry @@ -84962,14 +85719,13 @@ module \fus connect \cu_rd__go_i \cu_rd__go_i$35 connect \src1_i \src1_i$36 connect \src2_i \src2_i$54 - connect \o_ok \o_ok$84 - connect \cu_wr__rel_o \cu_wr__rel_o$85 - connect \cu_wr__go_i \cu_wr__go_i$86 - connect \dest1_o \dest1_o$103 - connect \cr_a_ok \cr_a_ok$109 - connect \dest2_o \dest2_o$114 - connect \xer_ca_ok \xer_ca_ok$118 - connect \dest3_o \dest3_o$122 + connect \src3_i \src3_i$61 + connect \o_ok \o_ok$86 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \dest1_o \dest1_o$105 + connect \cr_a_ok \cr_a_ok$111 + connect \dest2_o \dest2_o$116 connect \coresync_rst \coresync_rst end cell \spr0 \spr0 @@ -84986,14 +85742,14 @@ module \fus connect \src1_i \src1_i$39 connect \src4_i \src4_i connect \src6_i \src6_i - connect \src5_i \src5_i - connect \src3_i \src3_i$74 - connect \src2_i \src2_i$77 - connect \o_ok \o_ok$87 - connect \cu_wr__rel_o \cu_wr__rel_o$88 - connect \cu_wr__go_i \cu_wr__go_i$89 - connect \dest1_o \dest1_o$104 - connect \xer_ca_ok \xer_ca_ok$119 + connect \src5_i \src5_i$66 + connect \src3_i \src3_i$76 + connect \src2_i \src2_i$79 + connect \o_ok \o_ok$89 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \dest1_o \dest1_o$106 + connect \xer_ca_ok \xer_ca_ok$120 connect \dest6_o \dest6_o connect \xer_ov_ok \xer_ov_ok$124 connect \dest5_o \dest5_o @@ -85009,12 +85765,12 @@ module \fus connect \coresync_clk \coresync_clk connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__imm \oper_i_alu_div0__imm_data__imm - connect \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm_ok + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc_ok + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe_ok + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry @@ -85032,13 +85788,13 @@ module \fus connect \cu_rd__go_i \cu_rd__go_i$41 connect \src1_i \src1_i$42 connect \src2_i \src2_i$55 - connect \src3_i \src3_i$61 - connect \o_ok \o_ok$90 - connect \cu_wr__rel_o \cu_wr__rel_o$91 - connect \cu_wr__go_i \cu_wr__go_i$92 - connect \dest1_o \dest1_o$105 - connect \cr_a_ok \cr_a_ok$110 - connect \dest2_o \dest2_o$115 + connect \src3_i \src3_i$62 + connect \o_ok \o_ok$92 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \dest1_o \dest1_o$107 + connect \cr_a_ok \cr_a_ok$112 + connect \dest2_o \dest2_o$117 connect \xer_ov_ok \xer_ov_ok$125 connect \dest3_o \dest3_o$127 connect \xer_so_ok \xer_so_ok$130 @@ -85049,12 +85805,12 @@ module \fus connect \coresync_clk \coresync_clk connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__imm \oper_i_alu_mul0__imm_data__imm - connect \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm_ok + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc_ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe_ok + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed @@ -85066,13 +85822,13 @@ module \fus connect \cu_rd__go_i \cu_rd__go_i$44 connect \src1_i \src1_i$45 connect \src2_i \src2_i$56 - connect \src3_i \src3_i$62 - connect \o_ok \o_ok$93 - connect \cu_wr__rel_o \cu_wr__rel_o$94 - connect \cu_wr__go_i \cu_wr__go_i$95 - connect \dest1_o \dest1_o$106 - connect \cr_a_ok \cr_a_ok$111 - connect \dest2_o \dest2_o$116 + connect \src3_i \src3_i$63 + connect \o_ok \o_ok$95 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \dest1_o \dest1_o$108 + connect \cr_a_ok \cr_a_ok$113 + connect \dest2_o \dest2_o$118 connect \xer_ov_ok \xer_ov_ok$126 connect \dest3_o \dest3_o$128 connect \xer_so_ok \xer_so_ok$131 @@ -85083,12 +85839,13 @@ module \fus connect \coresync_clk \coresync_clk connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__imm \oper_i_alu_shift_rot0__imm_data__imm - connect \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm_ok + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc_ok + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe_ok + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr @@ -85105,13 +85862,14 @@ module \fus connect \src2_i \src2_i$57 connect \src3_i \src3_i connect \src4_i \src4_i$64 - connect \o_ok \o_ok$96 - connect \cu_wr__rel_o \cu_wr__rel_o$97 - connect \cu_wr__go_i \cu_wr__go_i$98 - connect \dest1_o \dest1_o$107 - connect \cr_a_ok \cr_a_ok$112 - connect \dest2_o \dest2_o$117 - connect \xer_ca_ok \xer_ca_ok$120 + connect \src5_i \src5_i + connect \o_ok \o_ok$98 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \dest1_o \dest1_o$109 + connect \cr_a_ok \cr_a_ok$114 + connect \dest2_o \dest2_o$119 + connect \xer_ca_ok \xer_ca_ok$121 connect \dest3_o \dest3_o$123 connect \coresync_rst \coresync_rst end @@ -85122,19 +85880,21 @@ module \fus connect \cu_ad__rel_o \cu_ad__rel_o connect \cu_st__go_i \cu_st__go_i connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm - connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc_ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe_ok + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn connect \cu_issue_i \cu_issue_i$25 connect \cu_busy_o \cu_busy_o$26 connect \cu_rdmaskn_i \cu_rdmaskn_i$27 @@ -85143,8 +85903,8 @@ module \fus connect \src1_i \src1_i$51 connect \src2_i \src2_i$58 connect \src3_i \src3_i$59 - connect \cu_wr__rel_o \cu_wr__rel_o$99 - connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \cu_wr__go_i \cu_wr__go_i$102 connect \o \o connect \ea \ea connect \coresync_rst \coresync_rst @@ -85165,9 +85925,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" module \st_active - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 2 \r_st_active @@ -85310,9 +86070,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" module \st_done - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_st_done @@ -85455,9 +86215,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" module \ld_active - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 2 \r_ld_active @@ -85600,9 +86360,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" module \reset_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_reset @@ -85709,9 +86469,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" module \adrok_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_addr_acked @@ -85854,9 +86614,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" module \busy_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_busy @@ -85999,9 +86759,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" module \cyc_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_cyc @@ -86189,9 +86949,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" module \valid_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_valid @@ -86334,9 +87094,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" module \pimem - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire width 1 input 2 \ldst_port0_is_ld_i @@ -87613,9 +88373,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" module \idx_l - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_idx_l @@ -87758,9 +88518,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" module \reset_l$128 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_reset @@ -87905,9 +88665,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0" module \l0$127 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire width 1 output 2 \ldst_port0_busy_o @@ -88301,9 +89061,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" module \lsmem - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" wire width 8 input 2 \x_mask_i @@ -89220,9 +89980,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0" module \l0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire width 1 output 2 \ldst_port0_busy_o @@ -89388,7 +90148,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.int" module \int - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 5 input 1 \dmi__addr @@ -89420,7 +90180,7 @@ module \int wire width 5 input 14 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 15 \dest1__wen - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 16 \coresync_rst memory width 64 size 32 \memory cell $meminit $1 @@ -89432,9 +90192,9 @@ module \int connect \ADDR 6'000000 connect \DATA 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data cell $memrd \rp_src1 parameter \MEMID "\\memory" @@ -89448,9 +90208,9 @@ module \int connect \ADDR \memory_r_addr connect \DATA \memory_r_data end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$3 cell $memrd \rp_src2 parameter \MEMID "\\memory" @@ -89464,9 +90224,9 @@ module \int connect \ADDR \memory_r_addr$2 connect \DATA \memory_r_data$3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$5 cell $memrd \rp_src3 parameter \MEMID "\\memory" @@ -89480,9 +90240,9 @@ module \int connect \ADDR \memory_r_addr$4 connect \DATA \memory_r_data$5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$7 cell $memrd \rp_dmi parameter \MEMID "\\memory" @@ -89496,11 +90256,11 @@ module \int connect \ADDR \memory_r_addr$6 connect \DATA \memory_r_data$7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 5 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data cell $memwr \wp_dest1 parameter \MEMID "\\memory" @@ -89519,9 +90279,9 @@ module \int assign \memory_r_addr \src1__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$next process $group_1 assign \ren_delay$next \ren_delay @@ -89538,9 +90298,9 @@ module \int end process $group_2 assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch { \ren_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 assign \src1__data_o \memory_r_data end @@ -89551,9 +90311,9 @@ module \int assign \memory_r_addr$2 \src2__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$8$next process $group_4 assign \ren_delay$8$next \ren_delay$8 @@ -89570,9 +90330,9 @@ module \int end process $group_5 assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch { \ren_delay$8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 assign \src2__data_o \memory_r_data$3 end @@ -89583,9 +90343,9 @@ module \int assign \memory_r_addr$4 \src3__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$9$next process $group_7 assign \ren_delay$9$next \ren_delay$9 @@ -89602,9 +90362,9 @@ module \int end process $group_8 assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch { \ren_delay$9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 assign \src3__data_o \memory_r_data$5 end @@ -89615,9 +90375,9 @@ module \int assign \memory_r_addr$6 \dmi__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$10$next process $group_10 assign \ren_delay$10$next \ren_delay$10 @@ -89634,9 +90394,9 @@ module \int end process $group_11 assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch { \ren_delay$10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 assign \dmi__data_o \memory_r_data$7 end @@ -89661,9 +90421,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" module \reg_0 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src10__ren @@ -89698,14 +90458,20 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w0__data_i + wire width 4 output 14 \r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89713,38 +90479,38 @@ module \reg_0 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src10__data_o$next \src10__data_o assign \src10__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src10__data_o$next \reg end @@ -89761,37 +90527,37 @@ module \reg_0 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89802,31 +90568,31 @@ module \reg_0 process $group_2 assign \src20__data_o$next \src20__data_o assign \src20__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src20__data_o$next \reg end @@ -89843,37 +90609,37 @@ module \reg_0 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89884,31 +90650,31 @@ module \reg_0 process $group_4 assign \src30__data_o$next \src30__data_o assign \src30__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src30__data_o$next \reg end @@ -89925,37 +90691,37 @@ module \reg_0 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89966,31 +90732,31 @@ module \reg_0 process $group_6 assign \r0__data_o$next \r0__data_o assign \r0__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r0__data_o$next \reg end @@ -90007,49 +90773,131 @@ module \reg_0 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r20__data_o$next \r20__data_o + assign \r20__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r20__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r20__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r20__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r20__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r20__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r20__data_o$next 4'0000 + end + sync init + update \r20__data_o 4'0000 + sync posedge \coresync_clk + update \r20__data_o \r20__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r20__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w0__data_i end @@ -90067,9 +90915,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" module \reg_1 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src11__ren @@ -90104,14 +90952,20 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w1__data_i + wire width 4 output 14 \r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90119,38 +90973,38 @@ module \reg_1 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src11__data_o$next \src11__data_o assign \src11__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src11__data_o$next \reg end @@ -90167,37 +91021,37 @@ module \reg_1 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90208,31 +91062,31 @@ module \reg_1 process $group_2 assign \src21__data_o$next \src21__data_o assign \src21__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src21__data_o$next \reg end @@ -90249,37 +91103,37 @@ module \reg_1 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90290,31 +91144,31 @@ module \reg_1 process $group_4 assign \src31__data_o$next \src31__data_o assign \src31__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src31__data_o$next \reg end @@ -90331,37 +91185,37 @@ module \reg_1 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90372,31 +91226,31 @@ module \reg_1 process $group_6 assign \r1__data_o$next \r1__data_o assign \r1__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r1__data_o$next \reg end @@ -90413,49 +91267,131 @@ module \reg_1 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r21__data_o$next \r21__data_o + assign \r21__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r21__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r21__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r21__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r21__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r21__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r21__data_o$next 4'0000 + end + sync init + update \r21__data_o 4'0000 + sync posedge \coresync_clk + update \r21__data_o \r21__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r21__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w1__data_i end @@ -90473,9 +91409,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" module \reg_2 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src12__ren @@ -90510,14 +91446,20 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w2__data_i + wire width 4 output 14 \r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90525,38 +91467,38 @@ module \reg_2 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src12__data_o$next \src12__data_o assign \src12__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src12__data_o$next \reg end @@ -90573,37 +91515,37 @@ module \reg_2 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90614,31 +91556,31 @@ module \reg_2 process $group_2 assign \src22__data_o$next \src22__data_o assign \src22__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src22__data_o$next \reg end @@ -90655,37 +91597,37 @@ module \reg_2 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90696,31 +91638,31 @@ module \reg_2 process $group_4 assign \src32__data_o$next \src32__data_o assign \src32__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src32__data_o$next \reg end @@ -90737,37 +91679,37 @@ module \reg_2 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90778,31 +91720,31 @@ module \reg_2 process $group_6 assign \r2__data_o$next \r2__data_o assign \r2__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r2__data_o$next \reg end @@ -90819,49 +91761,131 @@ module \reg_2 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r22__data_o$next \r22__data_o + assign \r22__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r22__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r22__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r22__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r22__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r22__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r22__data_o$next 4'0000 + end + sync init + update \r22__data_o 4'0000 + sync posedge \coresync_clk + update \r22__data_o \r22__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r22__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w2__data_i end @@ -90879,9 +91903,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" module \reg_3 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src13__ren @@ -90916,14 +91940,20 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w3__data_i + wire width 4 output 14 \r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 input 17 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -90931,38 +91961,38 @@ module \reg_3 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src13__data_o$next \src13__data_o assign \src13__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src13__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src13__data_o$next \dest13__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src13__data_o$next \dest23__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src13__data_o$next \w3__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src13__data_o$next \reg end @@ -90979,37 +92009,37 @@ module \reg_3 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src13__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91020,31 +92050,31 @@ module \reg_3 process $group_2 assign \src23__data_o$next \src23__data_o assign \src23__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src23__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src23__data_o$next \dest13__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src23__data_o$next \dest23__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src23__data_o$next \w3__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src23__data_o$next \reg end @@ -91061,37 +92091,37 @@ module \reg_3 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src23__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91102,31 +92132,31 @@ module \reg_3 process $group_4 assign \src33__data_o$next \src33__data_o assign \src33__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src33__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src33__data_o$next \dest13__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src33__data_o$next \dest23__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src33__data_o$next \w3__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src33__data_o$next \reg end @@ -91143,37 +92173,37 @@ module \reg_3 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src33__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91184,31 +92214,31 @@ module \reg_3 process $group_6 assign \r3__data_o$next \r3__data_o assign \r3__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r3__data_o$next \dest13__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r3__data_o$next \dest23__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r3__data_o$next \w3__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r3__data_o$next \reg end @@ -91225,49 +92255,131 @@ module \reg_3 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r23__data_o$next \r23__data_o + assign \r23__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r23__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r23__data_o$next \dest13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r23__data_o$next \dest23__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r23__data_o$next \w3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r23__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r23__data_o$next 4'0000 + end + sync init + update \r23__data_o 4'0000 + sync posedge \coresync_clk + update \r23__data_o \r23__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r23__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest13__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest23__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w3__data_i end @@ -91285,9 +92397,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" module \reg_4 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src14__ren @@ -91322,14 +92434,20 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r4__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w4__data_i + wire width 4 output 14 \r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w4__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 4 input 16 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91337,38 +92455,38 @@ module \reg_4 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src14__data_o$next \src14__data_o assign \src14__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src14__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src14__data_o$next \dest14__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src14__data_o$next \dest24__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src14__data_o$next \w4__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src14__data_o$next \reg end @@ -91385,37 +92503,37 @@ module \reg_4 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src14__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91426,31 +92544,31 @@ module \reg_4 process $group_2 assign \src24__data_o$next \src24__data_o assign \src24__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src24__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src24__data_o$next \dest14__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src24__data_o$next \dest24__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src24__data_o$next \w4__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src24__data_o$next \reg end @@ -91467,37 +92585,37 @@ module \reg_4 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src24__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91508,31 +92626,31 @@ module \reg_4 process $group_4 assign \src34__data_o$next \src34__data_o assign \src34__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src34__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src34__data_o$next \dest14__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src34__data_o$next \dest24__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src34__data_o$next \w4__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src34__data_o$next \reg end @@ -91549,37 +92667,37 @@ module \reg_4 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src34__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91590,31 +92708,31 @@ module \reg_4 process $group_6 assign \r4__data_o$next \r4__data_o assign \r4__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r4__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r4__data_o$next \dest14__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r4__data_o$next \dest24__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r4__data_o$next \w4__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r4__data_o$next \reg end @@ -91631,49 +92749,131 @@ module \reg_4 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r4__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r24__data_o$next \r24__data_o + assign \r24__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r24__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r24__data_o$next \dest14__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r24__data_o$next \dest24__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r24__data_o$next \w4__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r24__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r24__data_o$next 4'0000 + end + sync init + update \r24__data_o 4'0000 + sync posedge \coresync_clk + update \r24__data_o \r24__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r24__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest14__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest24__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w4__data_i end @@ -91691,9 +92891,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" module \reg_5 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src15__ren @@ -91728,14 +92928,20 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r5__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w5__data_i + wire width 4 output 14 \r25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w5__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 4 \r25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91743,38 +92949,38 @@ module \reg_5 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src15__data_o$next \src15__data_o assign \src15__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src15__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src15__data_o$next \dest15__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src15__data_o$next \dest25__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src15__data_o$next \w5__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src15__data_o$next \reg end @@ -91791,37 +92997,37 @@ module \reg_5 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src15__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91832,31 +93038,31 @@ module \reg_5 process $group_2 assign \src25__data_o$next \src25__data_o assign \src25__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src25__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src25__data_o$next \dest15__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src25__data_o$next \dest25__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src25__data_o$next \w5__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src25__data_o$next \reg end @@ -91873,37 +93079,37 @@ module \reg_5 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src25__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91914,31 +93120,31 @@ module \reg_5 process $group_4 assign \src35__data_o$next \src35__data_o assign \src35__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src35__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src35__data_o$next \dest15__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src35__data_o$next \dest25__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src35__data_o$next \w5__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src35__data_o$next \reg end @@ -91955,37 +93161,37 @@ module \reg_5 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src35__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -91996,31 +93202,31 @@ module \reg_5 process $group_6 assign \r5__data_o$next \r5__data_o assign \r5__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r5__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r5__data_o$next \dest15__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r5__data_o$next \dest25__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r5__data_o$next \w5__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r5__data_o$next \reg end @@ -92037,49 +93243,131 @@ module \reg_5 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r5__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r25__data_o$next \r25__data_o + assign \r25__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r25__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r25__data_o$next \dest15__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r25__data_o$next \dest25__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r25__data_o$next \w5__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r25__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r25__data_o$next 4'0000 + end + sync init + update \r25__data_o 4'0000 + sync posedge \coresync_clk + update \r25__data_o \r25__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r25__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest15__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest25__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w5__data_i end @@ -92097,9 +93385,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" module \reg_6 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src16__ren @@ -92134,14 +93422,20 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r6__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w6__data_i + wire width 4 output 14 \r26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w6__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 4 \r26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92149,38 +93443,38 @@ module \reg_6 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src16__data_o$next \src16__data_o assign \src16__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src16__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src16__data_o$next \dest16__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src16__data_o$next \dest26__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src16__data_o$next \w6__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src16__data_o$next \reg end @@ -92197,37 +93491,37 @@ module \reg_6 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src16__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92238,31 +93532,31 @@ module \reg_6 process $group_2 assign \src26__data_o$next \src26__data_o assign \src26__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src26__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src26__data_o$next \dest16__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src26__data_o$next \dest26__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src26__data_o$next \w6__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src26__data_o$next \reg end @@ -92279,37 +93573,37 @@ module \reg_6 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src26__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92320,31 +93614,31 @@ module \reg_6 process $group_4 assign \src36__data_o$next \src36__data_o assign \src36__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src36__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src36__data_o$next \dest16__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src36__data_o$next \dest26__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src36__data_o$next \w6__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src36__data_o$next \reg end @@ -92361,37 +93655,37 @@ module \reg_6 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src36__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92402,31 +93696,31 @@ module \reg_6 process $group_6 assign \r6__data_o$next \r6__data_o assign \r6__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r6__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r6__data_o$next \dest16__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r6__data_o$next \dest26__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r6__data_o$next \w6__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r6__data_o$next \reg end @@ -92443,49 +93737,131 @@ module \reg_6 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r6__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r26__data_o$next \r26__data_o + assign \r26__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r26__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r26__data_o$next \dest16__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r26__data_o$next \dest26__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r26__data_o$next \w6__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r26__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r26__data_o$next 4'0000 + end + sync init + update \r26__data_o 4'0000 + sync posedge \coresync_clk + update \r26__data_o \r26__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r26__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest16__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest26__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w6__data_i end @@ -92503,9 +93879,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" module \reg_7 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src17__ren @@ -92540,14 +93916,20 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 13 \r7__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w7__data_i + wire width 4 output 14 \r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w7__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 input 15 \r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92555,38 +93937,38 @@ module \reg_7 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next process $group_0 assign \src17__data_o$next \src17__data_o assign \src17__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src17__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src17__data_o$next \dest17__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src17__data_o$next \dest27__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src17__data_o$next \w7__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src17__data_o$next \reg end @@ -92603,37 +93985,37 @@ module \reg_7 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src17__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92644,31 +94026,31 @@ module \reg_7 process $group_2 assign \src27__data_o$next \src27__data_o assign \src27__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src27__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src27__data_o$next \dest17__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src27__data_o$next \dest27__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src27__data_o$next \w7__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src27__data_o$next \reg end @@ -92685,37 +94067,37 @@ module \reg_7 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src27__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92726,31 +94108,31 @@ module \reg_7 process $group_4 assign \src37__data_o$next \src37__data_o assign \src37__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src37__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src37__data_o$next \dest17__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src37__data_o$next \dest27__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src37__data_o$next \w7__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src37__data_o$next \reg end @@ -92767,37 +94149,37 @@ module \reg_7 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src37__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92808,31 +94190,31 @@ module \reg_7 process $group_6 assign \r7__data_o$next \r7__data_o assign \r7__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r7__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r7__data_o$next \dest17__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r7__data_o$next \dest27__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r7__data_o$next \w7__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r7__data_o$next \reg end @@ -92849,49 +94231,131 @@ module \reg_7 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r7__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $12 + end process $group_8 + assign \r27__data_o$next \r27__data_o + assign \r27__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r27__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r27__data_o$next \dest17__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r27__data_o$next \dest27__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \r27__data_o$next \w7__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \r27__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r27__data_o$next 4'0000 + end + sync init + update \r27__data_o 4'0000 + sync posedge \coresync_clk + update \r27__data_o \r27__data_o$next + end + process $group_9 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \r27__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$13 1'1 + end + end + sync init + end + process $group_10 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest17__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest27__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w7__data_i end @@ -92909,34 +94373,38 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr" module \cr - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 1 \full_rd__data_o + wire width 8 input 1 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 output 2 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 2 \full_rd__ren + wire width 32 output 3 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src1__data_o + wire width 8 input 4 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 4 \src1__ren + wire width 4 output 5 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src2__data_o + wire width 8 input 6 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 6 \src2__ren + wire width 4 output 7 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src3__data_o + wire width 8 input 8 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 8 \src3__ren + wire width 4 output 9 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 9 \full_wr__data_i + wire width 8 input 10 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 10 \full_wr__wen + wire width 32 input 11 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \data_i + wire width 8 input 12 \full_wr__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 12 \wen - attribute \src "simple/issuer.py:102" - wire width 1 input 13 \coresync_rst + wire width 4 input 13 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 14 \wen + attribute \src "simple/issuer.py:141" + wire width 1 input 15 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -92962,6 +94430,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_r20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen @@ -92980,6 +94452,8 @@ module \cr connect \dest20__data_i \reg_0_dest20__data_i connect \r0__data_o \reg_0_r0__data_o connect \r0__ren \reg_0_r0__ren + connect \r20__data_o \reg_0_r20__data_o + connect \r20__ren \reg_0_r20__ren connect \w0__data_i \reg_0_w0__data_i connect \w0__wen \reg_0_w0__wen end @@ -93008,6 +94482,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_r21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen @@ -93026,6 +94504,8 @@ module \cr connect \dest21__data_i \reg_1_dest21__data_i connect \r1__data_o \reg_1_r1__data_o connect \r1__ren \reg_1_r1__ren + connect \r21__data_o \reg_1_r21__data_o + connect \r21__ren \reg_1_r21__ren connect \w1__data_i \reg_1_w1__data_i connect \w1__wen \reg_1_w1__wen end @@ -93054,6 +94534,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_r2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen @@ -93072,6 +94556,8 @@ module \cr connect \dest22__data_i \reg_2_dest22__data_i connect \r2__data_o \reg_2_r2__data_o connect \r2__ren \reg_2_r2__ren + connect \r22__data_o \reg_2_r22__data_o + connect \r22__ren \reg_2_r22__ren connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end @@ -93100,6 +94586,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_3_r3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_3_w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_3_w3__wen @@ -93118,6 +94608,8 @@ module \cr connect \dest23__data_i \reg_3_dest23__data_i connect \r3__data_o \reg_3_r3__data_o connect \r3__ren \reg_3_r3__ren + connect \r23__data_o \reg_3_r23__data_o + connect \r23__ren \reg_3_r23__ren connect \w3__data_i \reg_3_w3__data_i connect \w3__wen \reg_3_w3__wen end @@ -93146,6 +94638,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_4_r4__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_4_w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_4_w4__wen @@ -93164,6 +94660,8 @@ module \cr connect \dest24__data_i \reg_4_dest24__data_i connect \r4__data_o \reg_4_r4__data_o connect \r4__ren \reg_4_r4__ren + connect \r24__data_o \reg_4_r24__data_o + connect \r24__ren \reg_4_r24__ren connect \w4__data_i \reg_4_w4__data_i connect \w4__wen \reg_4_w4__wen end @@ -93192,6 +94690,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_5_r5__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_5_w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_5_w5__wen @@ -93210,6 +94712,8 @@ module \cr connect \dest25__data_i \reg_5_dest25__data_i connect \r5__data_o \reg_5_r5__data_o connect \r5__ren \reg_5_r5__ren + connect \r25__data_o \reg_5_r25__data_o + connect \r25__ren \reg_5_r25__ren connect \w5__data_i \reg_5_w5__data_i connect \w5__wen \reg_5_w5__wen end @@ -93238,6 +94742,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_6_r6__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_6_w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_6_w6__wen @@ -93256,6 +94764,8 @@ module \cr connect \dest26__data_i \reg_6_dest26__data_i connect \r6__data_o \reg_6_r6__data_o connect \r6__ren \reg_6_r6__ren + connect \r26__data_o \reg_6_r26__data_o + connect \r26__ren \reg_6_r26__ren connect \w6__data_i \reg_6_w6__data_i connect \w6__wen \reg_6_w6__wen end @@ -93284,6 +94794,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_7_r7__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_7_w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_7_w7__wen @@ -93302,6 +94816,8 @@ module \cr connect \dest27__data_i \reg_7_dest27__data_i connect \r7__data_o \reg_7_r7__data_o connect \r7__ren \reg_7_r7__ren + connect \r27__data_o \reg_7_r27__data_o + connect \r27__ren \reg_7_r27__ren connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end @@ -93317,9 +94833,9 @@ module \cr assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next process $group_8 assign \ren_delay$next \ren_delay @@ -93437,9 +94953,9 @@ module \cr end process $group_9 assign \src1__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 assign \src1__data_o $15 end @@ -93457,9 +94973,9 @@ module \cr assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$17$next process $group_18 assign \ren_delay$17$next \ren_delay$17 @@ -93577,9 +95093,9 @@ module \cr end process $group_19 assign \src2__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $18 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 assign \src2__data_o $32 end @@ -93597,9 +95113,9 @@ module \cr assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34$next process $group_28 assign \ren_delay$34$next \ren_delay$34 @@ -93717,9 +95233,9 @@ module \cr end process $group_29 assign \src3__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $35 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 assign \src3__data_o $49 end @@ -93851,6 +95367,23 @@ module \cr sync init end process $group_71 + assign \full_rd2__data_o 32'00000000000000000000000000000000 + assign \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } + sync init + end + process $group_72 + assign \reg_0_r20__ren 1'0 + assign \reg_1_r21__ren 1'0 + assign \reg_2_r22__ren 1'0 + assign \reg_3_r23__ren 1'0 + assign \reg_4_r24__ren 1'0 + assign \reg_5_r25__ren 1'0 + assign \reg_6_r26__ren 1'0 + assign \reg_7_r27__ren 1'0 + assign { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren + sync init + end + process $group_80 assign \reg_0_w0__data_i 4'0000 assign \reg_1_w1__data_i 4'0000 assign \reg_2_w2__data_i 4'0000 @@ -93862,7 +95395,7 @@ module \cr assign { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i sync init end - process $group_79 + process $group_88 assign \reg_0_w0__wen 1'0 assign \reg_1_w1__wen 1'0 assign \reg_2_w2__wen 1'0 @@ -93880,9 +95413,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" module \reg_0$129 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src10__ren @@ -93924,11 +95457,11 @@ module \reg_0$129 wire width 2 input 16 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93936,44 +95469,44 @@ module \reg_0$129 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next process $group_0 assign \src10__data_o$next \src10__data_o assign \src10__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \dest30__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src10__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src10__data_o$next \reg end @@ -93990,43 +95523,43 @@ module \reg_0$129 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94037,37 +95570,37 @@ module \reg_0$129 process $group_2 assign \src20__data_o$next \src20__data_o assign \src20__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \dest30__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src20__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src20__data_o$next \reg end @@ -94084,43 +95617,43 @@ module \reg_0$129 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94131,37 +95664,37 @@ module \reg_0$129 process $group_4 assign \src30__data_o$next \src30__data_o assign \src30__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \dest30__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src30__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src30__data_o$next \reg end @@ -94178,43 +95711,43 @@ module \reg_0$129 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94225,37 +95758,37 @@ module \reg_0$129 process $group_6 assign \r0__data_o$next \r0__data_o assign \r0__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \dest30__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r0__data_o$next \w0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r0__data_o$next \reg end @@ -94272,32 +95805,32 @@ module \reg_0$129 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end @@ -94306,27 +95839,27 @@ module \reg_0$129 end process $group_8 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest20__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest30__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w0__data_i end @@ -94344,9 +95877,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" module \reg_1$130 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src11__ren @@ -94388,11 +95921,11 @@ module \reg_1$130 wire width 2 input 16 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94400,44 +95933,44 @@ module \reg_1$130 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next process $group_0 assign \src11__data_o$next \src11__data_o assign \src11__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \dest31__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src11__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src11__data_o$next \reg end @@ -94454,43 +95987,43 @@ module \reg_1$130 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94501,37 +96034,37 @@ module \reg_1$130 process $group_2 assign \src21__data_o$next \src21__data_o assign \src21__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \dest31__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src21__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src21__data_o$next \reg end @@ -94548,43 +96081,43 @@ module \reg_1$130 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94595,37 +96128,37 @@ module \reg_1$130 process $group_4 assign \src31__data_o$next \src31__data_o assign \src31__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \dest31__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src31__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src31__data_o$next \reg end @@ -94642,43 +96175,43 @@ module \reg_1$130 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94689,37 +96222,37 @@ module \reg_1$130 process $group_6 assign \r1__data_o$next \r1__data_o assign \r1__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \dest31__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r1__data_o$next \w1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r1__data_o$next \reg end @@ -94736,32 +96269,32 @@ module \reg_1$130 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end @@ -94770,27 +96303,27 @@ module \reg_1$130 end process $group_8 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest21__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest31__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w1__data_i end @@ -94808,9 +96341,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" module \reg_2$131 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \src12__ren @@ -94852,11 +96385,11 @@ module \reg_2$131 wire width 2 input 16 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94864,44 +96397,44 @@ module \reg_2$131 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next process $group_0 assign \src12__data_o$next \src12__data_o assign \src12__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \dest32__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src12__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src12__data_o$next \reg end @@ -94918,43 +96451,43 @@ module \reg_2$131 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94965,37 +96498,37 @@ module \reg_2$131 process $group_2 assign \src22__data_o$next \src22__data_o assign \src22__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \dest32__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src22__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src22__data_o$next \reg end @@ -95012,43 +96545,43 @@ module \reg_2$131 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -95059,37 +96592,37 @@ module \reg_2$131 process $group_4 assign \src32__data_o$next \src32__data_o assign \src32__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \dest32__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \src32__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \src32__data_o$next \reg end @@ -95106,43 +96639,43 @@ module \reg_2$131 end process $group_5 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$7 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $11 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -95153,37 +96686,37 @@ module \reg_2$131 process $group_6 assign \r2__data_o$next \r2__data_o assign \r2__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \dest32__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \r2__data_o$next \w2__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \r2__data_o$next \reg end @@ -95200,32 +96733,32 @@ module \reg_2$131 end process $group_7 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$10 1'1 end @@ -95234,27 +96767,27 @@ module \reg_2$131 end process $group_8 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest12__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest22__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \dest32__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \w2__data_i end @@ -95272,34 +96805,38 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer" module \xer - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 1 \src1__data_o + wire width 3 input 1 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 2 \src1__ren + wire width 6 output 2 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src2__data_o + wire width 2 output 3 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \src2__ren + wire width 3 input 4 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src3__data_o + wire width 2 output 5 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 6 \src3__ren + wire width 3 input 6 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 7 \data_i + wire width 2 output 7 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \wen + wire width 3 input 8 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \data_i$1 + wire width 2 input 9 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 10 \wen$2 + wire width 3 input 10 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \data_i$3 + wire width 2 input 11 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 12 \wen$4 - attribute \src "simple/issuer.py:102" - wire width 1 input 13 \coresync_rst + wire width 3 input 12 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \data_i$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 14 \wen$4 + attribute \src "simple/issuer.py:141" + wire width 1 input 15 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -95463,9 +97000,9 @@ module \xer assign { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$next process $group_3 assign \ren_delay$next \ren_delay @@ -95518,9 +97055,9 @@ module \xer end process $group_4 assign \src1__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 assign \src1__data_o $9 end @@ -95533,9 +97070,9 @@ module \xer assign { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$11$next process $group_8 assign \ren_delay$11$next \ren_delay$11 @@ -95588,9 +97125,9 @@ module \xer end process $group_9 assign \src2__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 assign \src2__data_o $16 end @@ -95603,9 +97140,9 @@ module \xer assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$18$next process $group_13 assign \ren_delay$18$next \ren_delay$18 @@ -95658,9 +97195,9 @@ module \xer end process $group_14 assign \src3__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 assign \src3__data_o $23 end @@ -95732,15 +97269,11 @@ module \xer assign \reg_2_dest32__data_i \data_i$1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \full_rd__data_o process $group_33 assign \full_rd__data_o 6'000000 assign \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \full_rd__ren process $group_34 assign \reg_0_r0__ren 1'0 assign \reg_1_r1__ren 1'0 @@ -95766,48 +97299,59 @@ module \xer assign { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen sync init end - connect \full_rd__ren 3'000 connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast" module \fast - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 1 \src1__data_o + wire width 3 input 1 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 2 \src1__addr + wire width 1 input 2 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 3 \src1__ren + wire width 64 output 3 \issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \src2__data_o + wire width 3 input 4 \issue__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 5 \src2__addr + wire width 1 input 5 \issue__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src2__ren + wire width 64 input 6 \issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \dest1__data_i + wire width 64 output 7 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \dest1__addr + wire width 3 input 8 \src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 9 \dest1__wen - attribute \src "simple/issuer.py:102" - wire width 1 input 10 \coresync_rst - memory width 64 size 5 \memory - cell $meminit $1 + wire width 1 input 9 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 10 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 11 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 12 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 13 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 14 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \dest1__wen + attribute \src "simple/issuer.py:141" + wire width 1 input 16 \coresync_rst + memory width 64 size 8 \memory + cell $meminit $2 parameter \MEMID "\\memory" - parameter \ABITS 3 + parameter \ABITS 4 parameter \WIDTH 64 - parameter \WORDS 5 + parameter \WORDS 8 parameter \PRIORITY 0 - connect \ADDR 3'000 - connect \DATA 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \ADDR 4'0000 + connect \DATA 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 3 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data cell $memrd \rp_src1 parameter \MEMID "\\memory" @@ -95821,10 +97365,10 @@ module \fast connect \ADDR \memory_r_addr connect \DATA \memory_r_data end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - wire width 3 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 cell $memrd \rp_src2 parameter \MEMID "\\memory" parameter \ABITS 3 @@ -95834,14 +97378,30 @@ module \fast parameter \TRANSPARENT 1 connect \CLK \coresync_clk connect \EN 1'1 - connect \ADDR \memory_r_addr$2 - connect \DATA \memory_r_data$3 + connect \ADDR \memory_r_addr$3 + connect \DATA \memory_r_data$4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + cell $memrd \rp_issue + parameter \MEMID "\\memory" + parameter \ABITS 3 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr$5 + connect \DATA \memory_r_data$6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 3 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data cell $memwr \wp_dest1 parameter \MEMID "\\memory" @@ -95855,14 +97415,32 @@ module \fast connect \ADDR \memory_w_addr connect \DATA \memory_w_data end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 1 \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + cell $memwr \wp_issue + parameter \MEMID "\\memory" + parameter \ABITS 3 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \PRIORITY 0 + connect \CLK \coresync_clk + connect \EN { { \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 } } + connect \ADDR \memory_w_addr$8 + connect \DATA \memory_w_data$9 + end process $group_0 assign \memory_r_addr 3'000 assign \memory_r_addr \src1__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$next process $group_1 assign \ren_delay$next \ren_delay @@ -95879,68 +97457,115 @@ module \fast end process $group_2 assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch { \ren_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 assign \src1__data_o \memory_r_data end sync init end process $group_3 - assign \memory_r_addr$2 3'000 - assign \memory_r_addr$2 \src2__addr + assign \memory_r_addr$3 3'000 + assign \memory_r_addr$3 \src2__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" - wire width 1 \ren_delay$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" - wire width 1 \ren_delay$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire width 1 \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire width 1 \ren_delay$10$next process $group_4 - assign \ren_delay$4$next \ren_delay$4 - assign \ren_delay$4$next \src2__ren + assign \ren_delay$10$next \ren_delay$10 + assign \ren_delay$10$next \src2__ren attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \ren_delay$4$next 1'0 + assign \ren_delay$10$next 1'0 end sync init - update \ren_delay$4 1'0 + update \ren_delay$10 1'0 sync posedge \coresync_clk - update \ren_delay$4 \ren_delay$4$next + update \ren_delay$10 \ren_delay$10$next end process $group_5 assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" - switch { \ren_delay$4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch { \ren_delay$10 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 - assign \src2__data_o \memory_r_data$3 + assign \src2__data_o \memory_r_data$4 end sync init end process $group_6 + assign \memory_r_addr$5 3'000 + assign \memory_r_addr$5 \issue__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire width 1 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire width 1 \ren_delay$11$next + process $group_7 + assign \ren_delay$11$next \ren_delay$11 + assign \ren_delay$11$next \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$11$next 1'0 + end + sync init + update \ren_delay$11 1'0 + sync posedge \coresync_clk + update \ren_delay$11 \ren_delay$11$next + end + process $group_8 + assign \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch { \ren_delay$11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + case 1'1 + assign \issue__data_o \memory_r_data$6 + end + sync init + end + process $group_9 assign \memory_w_addr 3'000 assign \memory_w_addr \dest1__addr sync init end - process $group_7 + process $group_10 assign \memory_w_en 1'0 assign \memory_w_en \dest1__wen sync init end - process $group_8 + process $group_11 assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 assign \memory_w_data \dest1__data_i sync init end + process $group_12 + assign \memory_w_addr$8 3'000 + assign \memory_w_addr$8 \issue__addr$1 + sync init + end + process $group_13 + assign \memory_w_en$7 1'0 + assign \memory_w_en$7 \issue__wen + sync init + end + process $group_14 + assign \memory_w_data$9 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \memory_w_data$9 \issue__data_i + sync init + end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" module \reg_0$132 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \cia0__ren @@ -95966,11 +97591,11 @@ module \reg_0$132 wire width 1 input 10 \d_wr10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 11 \d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -95978,38 +97603,38 @@ module \reg_0$132 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next process $group_0 assign \cia0__data_o$next \cia0__data_o assign \cia0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \cia0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \cia0__data_o$next \nia0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \cia0__data_o$next \msr0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \cia0__data_o$next \d_wr10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \cia0__data_o$next \reg end @@ -96026,37 +97651,37 @@ module \reg_0$132 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \cia0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -96067,31 +97692,31 @@ module \reg_0$132 process $group_2 assign \msr0__data_o$next \msr0__data_o assign \msr0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \msr0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \msr0__data_o$next \nia0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \msr0__data_o$next \msr0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \msr0__data_o$next \d_wr10__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \msr0__data_o$next \reg end @@ -96108,26 +97733,26 @@ module \reg_0$132 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \msr0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end @@ -96136,21 +97761,21 @@ module \reg_0$132 end process $group_4 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \nia0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \msr0__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \d_wr10__data_i end @@ -96168,9 +97793,9 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" module \reg_1$133 - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 2 \cia1__ren @@ -96196,11 +97821,11 @@ module \reg_1$133 wire width 1 input 10 \d_wr11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 11 \d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -96208,38 +97833,38 @@ module \reg_1$133 connect \A \wr_detect connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next process $group_0 assign \cia1__data_o$next \cia1__data_o assign \cia1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \cia1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \cia1__data_o$next \nia1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \cia1__data_o$next \msr1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \cia1__data_o$next \d_wr11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \cia1__data_o$next \reg end @@ -96256,37 +97881,37 @@ module \reg_1$133 end process $group_1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \cia1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -96297,31 +97922,31 @@ module \reg_1$133 process $group_2 assign \msr1__data_o$next \msr1__data_o assign \msr1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \msr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \msr1__data_o$next \nia1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \msr1__data_o$next \msr1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \msr1__data_o$next \d_wr11__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" case 1'1 assign \msr1__data_o$next \reg end @@ -96338,26 +97963,26 @@ module \reg_1$133 end process $group_3 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch { \msr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" case 1'1 assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" case 1'1 assign \wr_detect$4 1'1 end @@ -96366,21 +97991,21 @@ module \reg_1$133 end process $group_4 assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \nia1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \msr1__data_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" case 1'1 assign \reg$next \d_wr11__data_i end @@ -96396,31 +98021,491 @@ module \reg_1$133 end end attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.state.reg_2" +module \reg_2$134 + attribute \src "simple/issuer.py:141" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:141" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \d_wr12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + process $group_0 + assign \cia2__data_o$next \cia2__data_o + assign \cia2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \cia2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \cia2__data_o$next \nia2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \cia2__data_o$next \msr2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \cia2__data_o$next \d_wr12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \cia2__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cia2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \cia2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \cia2__data_o \cia2__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \cia2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \msr2__data_o$next \msr2__data_o + assign \msr2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \msr2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \msr2__data_o$next \nia2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \msr2__data_o$next \msr2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \msr2__data_o$next \d_wr12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \msr2__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \msr2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \msr2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \msr2__data_o \msr2__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \msr2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + process $group_4 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch { \nia2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + case 1'1 + assign \reg$next \nia2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch { \msr2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + case 1'1 + assign \reg$next \msr2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch { \d_wr12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + case 1'1 + assign \reg$next \d_wr12__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.state.reg_3" +module \reg_3$135 + attribute \src "simple/issuer.py:141" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:141" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \cia3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \nia3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \d_wr13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + process $group_0 + assign \cia3__data_o$next \cia3__data_o + assign \cia3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \cia3__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \cia3__data_o$next \nia3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \cia3__data_o$next \msr3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \cia3__data_o$next \d_wr13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \cia3__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cia3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \cia3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \cia3__data_o \cia3__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \cia3__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \msr3__data_o$next \msr3__data_o + assign \msr3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \msr3__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \msr3__data_o$next \nia3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \msr3__data_o$next \msr3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \msr3__data_o$next \d_wr13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + case 1'1 + assign \msr3__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \msr3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \msr3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \msr3__data_o \msr3__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch { \msr3__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \nia3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \msr3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch { \d_wr13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + process $group_4 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch { \nia3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + case 1'1 + assign \reg$next \nia3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch { \msr3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + case 1'1 + assign \reg$next \msr3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch { \d_wr13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + case 1'1 + assign \reg$next \d_wr13__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.state" module \state - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 1 \cia__ren + wire width 4 input 1 \cia__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 2 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 3 \wen + wire width 4 input 3 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 4 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 5 \msr__ren + wire width 4 input 5 \msr__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 6 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 7 \state_nia_wen + wire width 4 input 7 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 8 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 9 \data_i$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 10 \wen$3 - attribute \src "simple/issuer.py:102" + wire width 4 input 10 \wen$3 + attribute \src "simple/issuer.py:141" wire width 1 input 11 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_cia0__ren @@ -96490,26 +98575,96 @@ module \state connect \d_wr11__wen \reg_1_d_wr11__wen connect \d_wr11__data_i \reg_1_d_wr11__data_i end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_nia2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_d_wr12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_d_wr12__data_i + cell \reg_2$134 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cia2__ren \reg_2_cia2__ren + connect \cia2__data_o \reg_2_cia2__data_o + connect \msr2__ren \reg_2_msr2__ren + connect \msr2__data_o \reg_2_msr2__data_o + connect \nia2__wen \reg_2_nia2__wen + connect \nia2__data_i \reg_2_nia2__data_i + connect \msr2__wen \reg_2_msr2__wen + connect \msr2__data_i \reg_2_msr2__data_i + connect \d_wr12__wen \reg_2_d_wr12__wen + connect \d_wr12__data_i \reg_2_d_wr12__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_cia3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_nia3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_d_wr13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_d_wr13__data_i + cell \reg_3$135 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cia3__ren \reg_3_cia3__ren + connect \cia3__data_o \reg_3_cia3__data_o + connect \msr3__ren \reg_3_msr3__ren + connect \msr3__data_o \reg_3_msr3__data_o + connect \nia3__wen \reg_3_nia3__wen + connect \nia3__data_i \reg_3_nia3__data_i + connect \msr3__wen \reg_3_msr3__wen + connect \msr3__data_i \reg_3_msr3__data_i + connect \d_wr13__wen \reg_3_d_wr13__wen + connect \d_wr13__data_i \reg_3_d_wr13__data_i + end process $group_0 assign \reg_0_cia0__ren 1'0 assign \reg_1_cia1__ren 1'0 - assign { \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren + assign \reg_2_cia2__ren 1'0 + assign \reg_3_cia3__ren 1'0 + assign { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" - wire width 2 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" - wire width 2 \ren_delay$next - process $group_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$next + process $group_4 assign \ren_delay$next \ren_delay assign \ren_delay$next \cia__ren attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \ren_delay$next 2'00 + assign \ren_delay$next 4'0000 end sync init - update \ren_delay 2'00 + update \ren_delay 4'0000 sync posedge \coresync_clk update \ren_delay \ren_delay$next end @@ -96518,7 +98673,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_bool $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \ren_delay connect \Y $4 @@ -96536,53 +98691,81 @@ module \state connect \B \reg_1_cia1__data_o connect \Y $6 end - process $group_3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_cia2__data_o + connect \B \reg_3_cia3__data_o + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 $10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $6 + connect \B $8 + connect \Y $10 + end + process $group_5 assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch { $4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 - assign \cia__data_o $6 + assign \cia__data_o $10 end sync init end - process $group_4 + process $group_6 assign \reg_0_msr0__ren 1'0 assign \reg_1_msr1__ren 1'0 - assign { \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + assign \reg_2_msr2__ren 1'0 + assign \reg_3_msr3__ren 1'0 + assign { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" - wire width 2 \ren_delay$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" - wire width 2 \ren_delay$8$next - process $group_6 - assign \ren_delay$8$next \ren_delay$8 - assign \ren_delay$8$next \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12$next + process $group_10 + assign \ren_delay$12$next \ren_delay$12 + assign \ren_delay$12$next \msr__ren attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \ren_delay$8$next 2'00 + assign \ren_delay$12$next 4'0000 end sync init - update \ren_delay$8 2'00 + update \ren_delay$12 4'0000 sync posedge \coresync_clk - update \ren_delay$8 \ren_delay$8$next + update \ren_delay$12 \ren_delay$12$next end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $9 + wire width 1 $13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $10 + cell $reduce_bool $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \ren_delay$8 - connect \Y $9 + connect \A \ren_delay$12 + connect \Y $13 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $11 + wire width 64 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $12 + cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -96590,71 +98773,133 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \reg_1_msr1__data_o - connect \Y $11 + connect \Y $15 end - process $group_7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_msr2__data_o + connect \B \reg_3_msr3__data_o + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $15 + connect \B $17 + connect \Y $19 + end + process $group_11 assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" case 1'1 - assign \msr__data_o $11 + assign \msr__data_o $19 end sync init end - process $group_8 + process $group_12 assign \reg_0_nia0__wen 1'0 assign \reg_1_nia1__wen 1'0 - assign { \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + assign \reg_2_nia2__wen 1'0 + assign \reg_3_nia3__wen 1'0 + assign { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen sync init end - process $group_10 + process $group_16 assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \reg_0_nia0__data_i \data_i$1 sync init end - process $group_11 + process $group_17 assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \reg_1_nia1__data_i \data_i$1 sync init end - process $group_12 + process $group_18 + assign \reg_2_nia2__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_2_nia2__data_i \data_i$1 + sync init + end + process $group_19 + assign \reg_3_nia3__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_3_nia3__data_i \data_i$1 + sync init + end + process $group_20 assign \reg_0_msr0__wen 1'0 assign \reg_1_msr1__wen 1'0 - assign { \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 + assign \reg_2_msr2__wen 1'0 + assign \reg_3_msr3__wen 1'0 + assign { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 sync init end - process $group_14 + process $group_24 assign \reg_0_msr0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \reg_0_msr0__data_i \data_i$2 sync init end - process $group_15 + process $group_25 assign \reg_1_msr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \reg_1_msr1__data_i \data_i$2 sync init end - process $group_16 + process $group_26 + assign \reg_2_msr2__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_2_msr2__data_i \data_i$2 + sync init + end + process $group_27 + assign \reg_3_msr3__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_3_msr3__data_i \data_i$2 + sync init + end + process $group_28 assign \reg_0_d_wr10__wen 1'0 assign \reg_1_d_wr11__wen 1'0 - assign { \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + assign \reg_2_d_wr12__wen 1'0 + assign \reg_3_d_wr13__wen 1'0 + assign { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen sync init end - process $group_18 + process $group_32 assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \reg_0_d_wr10__data_i \data_i sync init end - process $group_19 + process $group_33 assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \reg_1_d_wr11__data_i \data_i sync init end + process $group_34 + assign \reg_2_d_wr12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_2_d_wr12__data_i \data_i + sync init + end + process $group_35 + assign \reg_3_d_wr13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_3_d_wr13__data_i \data_i + sync init + end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.spr" module \spr - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 1 \spr1__data_o @@ -96668,7 +98913,7 @@ module \spr wire width 7 input 5 \spr1__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 input 6 \spr1__wen - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 7 \coresync_rst memory width 64 size 110 \memory cell $meminit $2 @@ -96680,9 +98925,9 @@ module \spr connect \ADDR 7'0000000 connect \DATA 7040'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data cell $memrd \rp_spr1 parameter \MEMID "\\memory" @@ -96696,11 +98941,11 @@ module \spr connect \ADDR \memory_r_addr connect \DATA \memory_r_data end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 7 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data cell $memwr \wp_spr1 parameter \MEMID "\\memory" @@ -96719,9 +98964,9 @@ module \spr assign \memory_r_addr \spr1__addr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire width 1 \ren_delay$next process $group_1 assign \ren_delay$next \ren_delay @@ -96738,9 +98983,9 @@ module \spr end process $group_2 assign \spr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch { \ren_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" case 1'1 assign \spr1__data_o \memory_r_data end @@ -96763,566 +99008,104861 @@ module \spr end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" -module \rdpick_INT_ra - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 9 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 9 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 9 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 9 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 9 - connect \A \i - connect \Y $1 - end +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec19" +module \ALU_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch process $group_0 - assign \ni 9'000000000 - assign \ni $1 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_function_unit 11'00000000010 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_function_unit 11'00000000010 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end process $group_2 - assign \t1 1'0 - assign \t1 $3 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_internal_op 7'0100100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_internal_op 7'0000000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end process $group_3 - assign \t2 1'0 - assign \t2 $7 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_in1_sel 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_in1_sel 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end process $group_4 - assign \t3 1'0 - assign \t3 $11 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_in2_sel 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_in2_sel 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end process $group_5 - assign \t4 1'0 - assign \t4 $15 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_cr_in 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cr_in 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end process $group_6 - assign \t5 1'0 - assign \t5 $19 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_cr_out 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cr_out 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end process $group_7 - assign \t6 1'0 - assign \t6 $23 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_ldst_len 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_ldst_len 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end process $group_8 - assign \t7 1'0 - assign \t7 $27 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_rc_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_rc_sel 2'10 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] } - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \Y $31 - end process $group_9 - assign \t8 1'0 - assign \t8 $31 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_cry_in 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cry_in 2'00 + end sync init end process $group_10 - assign \o 9'000000000 - assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_inv_a 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_inv_a 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $35 - end process $group_11 - assign \en_o 1'0 - assign \en_o $35 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_inv_out 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_inv_out 1'0 + end + sync init + end + process $group_12 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_cry_out 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cry_out 1'0 + end + sync init + end + process $group_13 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_is_32b 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_is_32b 1'0 + end + sync init + end + process $group_14 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010010110 + assign \ALU_sgn 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_sgn 1'0 + end + sync init + end + process $group_15 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" -module \rdpick_INT_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \i - connect \Y $1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec30" +module \ALU_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub10" +module \ALU_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch process $group_0 - assign \ni 8'00000000 - assign \ni $1 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_function_unit 11'00000000010 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end process $group_2 - assign \t1 1'0 - assign \t1 $3 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_internal_op 7'0000010 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end process $group_3 - assign \t2 1'0 - assign \t2 $7 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_in1_sel 3'001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end process $group_4 - assign \t3 1'0 - assign \t3 $11 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_in2_sel 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end process $group_5 - assign \t4 1'0 - assign \t4 $15 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cr_in 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end process $group_6 - assign \t5 1'0 - assign \t5 $19 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cr_out 3'001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end process $group_7 - assign \t6 1'0 - assign \t6 $23 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_ldst_len 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end process $group_8 - assign \t7 1'0 - assign \t7 $27 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_rc_sel 2'10 + end sync init end process $group_9 - assign \o 8'00000000 - assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cry_in 2'10 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end process $group_10 - assign \en_o 1'0 - assign \en_o $31 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_inv_a 1'0 + end sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" -module \rdpick_INT_rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 2'00 - assign \ni $1 + process $group_11 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_inv_out 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + process $group_12 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cry_out 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 + process $group_13 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_is_32b 1'0 + end + sync init + end + process $group_14 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub28" +module \ALU_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub0" +module \ALU_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_internal_op 7'0001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_internal_op 7'0001010 + end + sync init + end + process $group_3 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_in1_sel 3'001 + end + sync init + end + process $group_4 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cr_in 3'000 + end + sync init + end + process $group_6 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cr_out 3'010 + end + sync init + end + process $group_7 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_ldst_len 4'0000 + end + sync init + end + process $group_8 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_rc_sel 2'00 + end + sync init + end + process $group_9 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cry_in 2'01 + end + sync init + end + process $group_10 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_inv_a 1'1 + end + sync init + end + process $group_11 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_inv_out 1'0 + end + sync init + end + process $group_12 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cry_out 1'0 + end + sync init + end + process $group_13 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_is_32b 1'0 + end + sync init + end + process $group_14 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub26" +module \ALU_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_internal_op 7'0011111 + end + sync init + end + process $group_3 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_in1_sel 3'100 + end + sync init + end + process $group_4 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_in2_sel 4'0000 + end + sync init + end + process $group_5 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cr_in 3'000 + end + sync init + end + process $group_6 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cr_out 3'001 + end + sync init + end + process $group_7 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_ldst_len 4'0100 + end + sync init + end + process $group_8 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_rc_sel 2'10 + end + sync init + end + process $group_9 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cry_in 2'00 + end + sync init + end + process $group_10 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_inv_a 1'0 + end + sync init + end + process $group_11 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_inv_out 1'0 + end + sync init + end + process $group_12 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cry_out 1'0 + end + sync init + end + process $group_13 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_is_32b 1'0 + end + sync init + end + process $group_14 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub19" +module \ALU_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub22" +module \ALU_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_internal_op 7'0100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_internal_op 7'0000001 + end + sync init + end + process $group_3 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_in1_sel 3'000 + end + sync init + end + process $group_4 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_in2_sel 4'0000 + end + sync init + end + process $group_5 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_cr_in 3'000 + end + sync init + end + process $group_6 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_cr_out 3'000 + end + sync init + end + process $group_7 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_ldst_len 4'0000 + end + sync init + end + process $group_8 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_rc_sel 2'00 + end + sync init + end + process $group_9 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_cry_in 2'00 + end + sync init + end + process $group_10 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_inv_a 1'0 + end + sync init + end + process $group_11 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_inv_out 1'0 + end + sync init + end + process $group_12 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_cry_out 1'0 + end + sync init + end + process $group_13 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_is_32b 1'0 + end + sync init + end + process $group_14 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \ALU_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub9" +module \ALU_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub11" +module \ALU_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub27" +module \ALU_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub15" +module \ALU_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub20" +module \ALU_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub21" +module \ALU_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub23" +module \ALU_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub16" +module \ALU_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub18" +module \ALU_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub8" +module \ALU_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_internal_op 7'0000010 + end + sync init + end + process $group_3 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_in1_sel 3'001 + end + sync init + end + process $group_4 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_in2_sel 4'0000 + end + sync init + end + process $group_5 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cr_in 3'000 + end + sync init + end + process $group_6 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cr_out 3'001 + end + sync init + end + process $group_7 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_ldst_len 4'0000 + end + sync init + end + process $group_8 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_rc_sel 2'10 + end + sync init + end + process $group_9 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cry_in 2'10 + end + sync init + end + process $group_10 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_inv_a 1'1 + end + sync init + end + process $group_11 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_inv_out 1'0 + end + sync init + end + process $group_12 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_cry_out 1'1 + end + sync init + end + process $group_13 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_is_32b 1'0 + end + sync init + end + process $group_14 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \ALU_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub24" +module \ALU_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub4" +module \ALU_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31" +module \ALU_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub10_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec_sub10_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec_sub10_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub10_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub10_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub10_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub10_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub10_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub10_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub10_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub10_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub10_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub10_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub10_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub10_ALU_sgn + cell \ALU_dec_sub10 \ALU_dec_sub10 + connect \opcode_in \ALU_dec_sub10_opcode_in + connect \ALU_function_unit \ALU_dec_sub10_ALU_function_unit + connect \ALU_internal_op \ALU_dec_sub10_ALU_internal_op + connect \ALU_in1_sel \ALU_dec_sub10_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec_sub10_ALU_in2_sel + connect \ALU_cr_in \ALU_dec_sub10_ALU_cr_in + connect \ALU_cr_out \ALU_dec_sub10_ALU_cr_out + connect \ALU_ldst_len \ALU_dec_sub10_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec_sub10_ALU_rc_sel + connect \ALU_cry_in \ALU_dec_sub10_ALU_cry_in + connect \ALU_inv_a \ALU_dec_sub10_ALU_inv_a + connect \ALU_inv_out \ALU_dec_sub10_ALU_inv_out + connect \ALU_cry_out \ALU_dec_sub10_ALU_cry_out + connect \ALU_is_32b \ALU_dec_sub10_ALU_is_32b + connect \ALU_sgn \ALU_dec_sub10_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub28_opcode_in + cell \ALU_dec_sub28 \ALU_dec_sub28 + connect \opcode_in \ALU_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub0_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec_sub0_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec_sub0_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub0_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub0_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub0_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub0_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub0_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub0_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub0_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub0_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub0_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub0_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub0_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub0_ALU_sgn + cell \ALU_dec_sub0 \ALU_dec_sub0 + connect \opcode_in \ALU_dec_sub0_opcode_in + connect \ALU_function_unit \ALU_dec_sub0_ALU_function_unit + connect \ALU_internal_op \ALU_dec_sub0_ALU_internal_op + connect \ALU_in1_sel \ALU_dec_sub0_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec_sub0_ALU_in2_sel + connect \ALU_cr_in \ALU_dec_sub0_ALU_cr_in + connect \ALU_cr_out \ALU_dec_sub0_ALU_cr_out + connect \ALU_ldst_len \ALU_dec_sub0_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec_sub0_ALU_rc_sel + connect \ALU_cry_in \ALU_dec_sub0_ALU_cry_in + connect \ALU_inv_a \ALU_dec_sub0_ALU_inv_a + connect \ALU_inv_out \ALU_dec_sub0_ALU_inv_out + connect \ALU_cry_out \ALU_dec_sub0_ALU_cry_out + connect \ALU_is_32b \ALU_dec_sub0_ALU_is_32b + connect \ALU_sgn \ALU_dec_sub0_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub26_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec_sub26_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec_sub26_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub26_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub26_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub26_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub26_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub26_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub26_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub26_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub26_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub26_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub26_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub26_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub26_ALU_sgn + cell \ALU_dec_sub26 \ALU_dec_sub26 + connect \opcode_in \ALU_dec_sub26_opcode_in + connect \ALU_function_unit \ALU_dec_sub26_ALU_function_unit + connect \ALU_internal_op \ALU_dec_sub26_ALU_internal_op + connect \ALU_in1_sel \ALU_dec_sub26_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec_sub26_ALU_in2_sel + connect \ALU_cr_in \ALU_dec_sub26_ALU_cr_in + connect \ALU_cr_out \ALU_dec_sub26_ALU_cr_out + connect \ALU_ldst_len \ALU_dec_sub26_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec_sub26_ALU_rc_sel + connect \ALU_cry_in \ALU_dec_sub26_ALU_cry_in + connect \ALU_inv_a \ALU_dec_sub26_ALU_inv_a + connect \ALU_inv_out \ALU_dec_sub26_ALU_inv_out + connect \ALU_cry_out \ALU_dec_sub26_ALU_cry_out + connect \ALU_is_32b \ALU_dec_sub26_ALU_is_32b + connect \ALU_sgn \ALU_dec_sub26_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub19_opcode_in + cell \ALU_dec_sub19 \ALU_dec_sub19 + connect \opcode_in \ALU_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub22_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec_sub22_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec_sub22_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub22_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub22_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub22_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub22_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub22_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub22_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub22_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub22_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub22_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub22_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub22_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub22_ALU_sgn + cell \ALU_dec_sub22 \ALU_dec_sub22 + connect \opcode_in \ALU_dec_sub22_opcode_in + connect \ALU_function_unit \ALU_dec_sub22_ALU_function_unit + connect \ALU_internal_op \ALU_dec_sub22_ALU_internal_op + connect \ALU_in1_sel \ALU_dec_sub22_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec_sub22_ALU_in2_sel + connect \ALU_cr_in \ALU_dec_sub22_ALU_cr_in + connect \ALU_cr_out \ALU_dec_sub22_ALU_cr_out + connect \ALU_ldst_len \ALU_dec_sub22_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec_sub22_ALU_rc_sel + connect \ALU_cry_in \ALU_dec_sub22_ALU_cry_in + connect \ALU_inv_a \ALU_dec_sub22_ALU_inv_a + connect \ALU_inv_out \ALU_dec_sub22_ALU_inv_out + connect \ALU_cry_out \ALU_dec_sub22_ALU_cry_out + connect \ALU_is_32b \ALU_dec_sub22_ALU_is_32b + connect \ALU_sgn \ALU_dec_sub22_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub9_opcode_in + cell \ALU_dec_sub9 \ALU_dec_sub9 + connect \opcode_in \ALU_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub11_opcode_in + cell \ALU_dec_sub11 \ALU_dec_sub11 + connect \opcode_in \ALU_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub27_opcode_in + cell \ALU_dec_sub27 \ALU_dec_sub27 + connect \opcode_in \ALU_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub15_opcode_in + cell \ALU_dec_sub15 \ALU_dec_sub15 + connect \opcode_in \ALU_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub20_opcode_in + cell \ALU_dec_sub20 \ALU_dec_sub20 + connect \opcode_in \ALU_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub21_opcode_in + cell \ALU_dec_sub21 \ALU_dec_sub21 + connect \opcode_in \ALU_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub23_opcode_in + cell \ALU_dec_sub23 \ALU_dec_sub23 + connect \opcode_in \ALU_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub16_opcode_in + cell \ALU_dec_sub16 \ALU_dec_sub16 + connect \opcode_in \ALU_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub18_opcode_in + cell \ALU_dec_sub18 \ALU_dec_sub18 + connect \opcode_in \ALU_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec_sub8_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec_sub8_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub8_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub8_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub8_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec_sub8_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec_sub8_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub8_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec_sub8_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub8_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub8_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub8_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub8_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec_sub8_ALU_sgn + cell \ALU_dec_sub8 \ALU_dec_sub8 + connect \opcode_in \ALU_dec_sub8_opcode_in + connect \ALU_function_unit \ALU_dec_sub8_ALU_function_unit + connect \ALU_internal_op \ALU_dec_sub8_ALU_internal_op + connect \ALU_in1_sel \ALU_dec_sub8_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec_sub8_ALU_in2_sel + connect \ALU_cr_in \ALU_dec_sub8_ALU_cr_in + connect \ALU_cr_out \ALU_dec_sub8_ALU_cr_out + connect \ALU_ldst_len \ALU_dec_sub8_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec_sub8_ALU_rc_sel + connect \ALU_cry_in \ALU_dec_sub8_ALU_cry_in + connect \ALU_inv_a \ALU_dec_sub8_ALU_inv_a + connect \ALU_inv_out \ALU_dec_sub8_ALU_inv_out + connect \ALU_cry_out \ALU_dec_sub8_ALU_cry_out + connect \ALU_is_32b \ALU_dec_sub8_ALU_is_32b + connect \ALU_sgn \ALU_dec_sub8_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub24_opcode_in + cell \ALU_dec_sub24 \ALU_dec_sub24 + connect \opcode_in \ALU_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec_sub4_opcode_in + cell \ALU_dec_sub4 \ALU_dec_sub4 + connect \opcode_in \ALU_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \ALU_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \ALU_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \ALU_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \ALU_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \ALU_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \ALU_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \ALU_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \ALU_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \ALU_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \ALU_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \ALU_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \ALU_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \ALU_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \ALU_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \ALU_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \ALU_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \ALU_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \ALU_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$13 + process $group_20 + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_function_unit \ALU_dec_sub10_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_function_unit \ALU_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_function_unit \ALU_dec_sub0_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_function_unit \ALU_dec_sub26_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_function_unit \ALU_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_function_unit \ALU_dec_sub22_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_function_unit \ALU_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_function_unit \ALU_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_function_unit \ALU_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_function_unit \ALU_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_function_unit \ALU_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_function_unit \ALU_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_function_unit \ALU_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_function_unit \ALU_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_function_unit \ALU_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_function_unit \ALU_dec_sub8_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_function_unit \ALU_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_function_unit \ALU_function_unit$13 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$15 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$26 + process $group_21 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_internal_op \ALU_dec_sub10_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_internal_op \ALU_internal_op$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_internal_op \ALU_dec_sub0_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_internal_op \ALU_dec_sub26_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_internal_op \ALU_internal_op$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_internal_op \ALU_dec_sub22_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_internal_op \ALU_internal_op$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_internal_op \ALU_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_internal_op \ALU_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_internal_op \ALU_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_internal_op \ALU_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_internal_op \ALU_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_internal_op \ALU_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_internal_op \ALU_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_internal_op \ALU_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_internal_op \ALU_dec_sub8_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_internal_op \ALU_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_internal_op \ALU_internal_op$26 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$27 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$28 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$29 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$30 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$31 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$32 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$33 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$34 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$35 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$36 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$37 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$38 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$39 + process $group_22 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_in1_sel \ALU_dec_sub10_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_in1_sel \ALU_in1_sel$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_in1_sel \ALU_dec_sub0_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_in1_sel \ALU_dec_sub26_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_in1_sel \ALU_in1_sel$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_in1_sel \ALU_dec_sub22_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_in1_sel \ALU_in1_sel$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_in1_sel \ALU_in1_sel$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_in1_sel \ALU_in1_sel$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_in1_sel \ALU_in1_sel$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_in1_sel \ALU_in1_sel$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_in1_sel \ALU_in1_sel$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_in1_sel \ALU_in1_sel$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_in1_sel \ALU_in1_sel$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_in1_sel \ALU_in1_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_in1_sel \ALU_dec_sub8_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_in1_sel \ALU_in1_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_in1_sel \ALU_in1_sel$39 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$40 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$41 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$42 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$43 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$44 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$45 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$46 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$47 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$48 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$49 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$50 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$51 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$52 + process $group_23 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_in2_sel \ALU_dec_sub10_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_in2_sel \ALU_in2_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_in2_sel \ALU_dec_sub0_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_in2_sel \ALU_dec_sub26_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_in2_sel \ALU_in2_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_in2_sel \ALU_dec_sub22_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_in2_sel \ALU_in2_sel$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_in2_sel \ALU_in2_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_in2_sel \ALU_in2_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_in2_sel \ALU_in2_sel$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_in2_sel \ALU_in2_sel$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_in2_sel \ALU_in2_sel$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_in2_sel \ALU_in2_sel$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_in2_sel \ALU_in2_sel$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_in2_sel \ALU_in2_sel$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_in2_sel \ALU_dec_sub8_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_in2_sel \ALU_in2_sel$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_in2_sel \ALU_in2_sel$52 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$53 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$54 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$55 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$56 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$57 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$58 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$59 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$60 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$61 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$62 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$63 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$64 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$65 + process $group_24 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_cr_in \ALU_dec_sub10_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_cr_in \ALU_cr_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_cr_in \ALU_dec_sub0_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_cr_in \ALU_dec_sub26_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_cr_in \ALU_cr_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_cr_in \ALU_dec_sub22_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_cr_in \ALU_cr_in$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_cr_in \ALU_cr_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_cr_in \ALU_cr_in$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_cr_in \ALU_cr_in$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_cr_in \ALU_cr_in$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_cr_in \ALU_cr_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_cr_in \ALU_cr_in$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_cr_in \ALU_cr_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_cr_in \ALU_cr_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_cr_in \ALU_dec_sub8_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_cr_in \ALU_cr_in$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_cr_in \ALU_cr_in$65 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$66 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$67 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$68 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$69 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$70 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$71 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$72 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$73 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$74 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$75 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$76 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$77 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$78 + process $group_25 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_cr_out \ALU_dec_sub10_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_cr_out \ALU_cr_out$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_cr_out \ALU_dec_sub0_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_cr_out \ALU_dec_sub26_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_cr_out \ALU_cr_out$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_cr_out \ALU_dec_sub22_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_cr_out \ALU_cr_out$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_cr_out \ALU_cr_out$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_cr_out \ALU_cr_out$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_cr_out \ALU_cr_out$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_cr_out \ALU_cr_out$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_cr_out \ALU_cr_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_cr_out \ALU_cr_out$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_cr_out \ALU_cr_out$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_cr_out \ALU_cr_out$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_cr_out \ALU_dec_sub8_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_cr_out \ALU_cr_out$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_cr_out \ALU_cr_out$78 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$79 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$80 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$81 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$82 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$83 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$84 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$85 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$86 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$87 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$88 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$89 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$90 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$91 + process $group_26 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_ldst_len \ALU_dec_sub10_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_ldst_len \ALU_ldst_len$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_ldst_len \ALU_dec_sub0_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_ldst_len \ALU_dec_sub26_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_ldst_len \ALU_ldst_len$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_ldst_len \ALU_dec_sub22_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_ldst_len \ALU_ldst_len$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_ldst_len \ALU_ldst_len$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_ldst_len \ALU_ldst_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_ldst_len \ALU_ldst_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_ldst_len \ALU_ldst_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_ldst_len \ALU_ldst_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_ldst_len \ALU_ldst_len$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_ldst_len \ALU_ldst_len$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_ldst_len \ALU_ldst_len$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_ldst_len \ALU_dec_sub8_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_ldst_len \ALU_ldst_len$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_ldst_len \ALU_ldst_len$91 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$92 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$93 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$94 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$95 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$96 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$97 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$98 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$99 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$100 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$101 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$102 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$103 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$104 + process $group_27 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_rc_sel \ALU_dec_sub10_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_rc_sel \ALU_rc_sel$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_rc_sel \ALU_dec_sub0_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_rc_sel \ALU_dec_sub26_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_rc_sel \ALU_rc_sel$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_rc_sel \ALU_dec_sub22_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_rc_sel \ALU_rc_sel$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_rc_sel \ALU_rc_sel$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_rc_sel \ALU_rc_sel$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_rc_sel \ALU_rc_sel$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_rc_sel \ALU_rc_sel$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_rc_sel \ALU_rc_sel$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_rc_sel \ALU_rc_sel$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_rc_sel \ALU_rc_sel$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_rc_sel \ALU_rc_sel$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_rc_sel \ALU_dec_sub8_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_rc_sel \ALU_rc_sel$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_rc_sel \ALU_rc_sel$104 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$105 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$106 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$107 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$108 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$109 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$112 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$113 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$114 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$115 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$116 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$117 + process $group_28 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_cry_in \ALU_dec_sub10_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_cry_in \ALU_cry_in$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_cry_in \ALU_dec_sub0_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_cry_in \ALU_dec_sub26_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_cry_in \ALU_cry_in$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_cry_in \ALU_dec_sub22_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_cry_in \ALU_cry_in$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_cry_in \ALU_cry_in$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_cry_in \ALU_cry_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_cry_in \ALU_cry_in$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_cry_in \ALU_cry_in$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_cry_in \ALU_cry_in$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_cry_in \ALU_cry_in$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_cry_in \ALU_cry_in$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_cry_in \ALU_cry_in$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_cry_in \ALU_dec_sub8_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_cry_in \ALU_cry_in$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_cry_in \ALU_cry_in$117 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$130 + process $group_29 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_inv_a \ALU_dec_sub10_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_inv_a \ALU_inv_a$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_inv_a \ALU_dec_sub0_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_inv_a \ALU_dec_sub26_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_inv_a \ALU_inv_a$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_inv_a \ALU_dec_sub22_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_inv_a \ALU_inv_a$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_inv_a \ALU_inv_a$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_inv_a \ALU_inv_a$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_inv_a \ALU_inv_a$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_inv_a \ALU_inv_a$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_inv_a \ALU_inv_a$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_inv_a \ALU_inv_a$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_inv_a \ALU_inv_a$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_inv_a \ALU_inv_a$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_inv_a \ALU_dec_sub8_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_inv_a \ALU_inv_a$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_inv_a \ALU_inv_a$130 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$143 + process $group_30 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_inv_out \ALU_dec_sub10_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_inv_out \ALU_inv_out$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_inv_out \ALU_dec_sub0_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_inv_out \ALU_dec_sub26_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_inv_out \ALU_inv_out$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_inv_out \ALU_dec_sub22_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_inv_out \ALU_inv_out$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_inv_out \ALU_inv_out$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_inv_out \ALU_inv_out$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_inv_out \ALU_inv_out$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_inv_out \ALU_inv_out$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_inv_out \ALU_inv_out$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_inv_out \ALU_inv_out$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_inv_out \ALU_inv_out$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_inv_out \ALU_inv_out$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_inv_out \ALU_dec_sub8_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_inv_out \ALU_inv_out$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_inv_out \ALU_inv_out$143 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$156 + process $group_31 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_cry_out \ALU_dec_sub10_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_cry_out \ALU_cry_out$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_cry_out \ALU_dec_sub0_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_cry_out \ALU_dec_sub26_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_cry_out \ALU_cry_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_cry_out \ALU_dec_sub22_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_cry_out \ALU_cry_out$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_cry_out \ALU_cry_out$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_cry_out \ALU_cry_out$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_cry_out \ALU_cry_out$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_cry_out \ALU_cry_out$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_cry_out \ALU_cry_out$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_cry_out \ALU_cry_out$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_cry_out \ALU_cry_out$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_cry_out \ALU_cry_out$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_cry_out \ALU_dec_sub8_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_cry_out \ALU_cry_out$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_cry_out \ALU_cry_out$156 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$169 + process $group_32 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_is_32b \ALU_dec_sub10_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_is_32b \ALU_is_32b$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_is_32b \ALU_dec_sub0_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_is_32b \ALU_dec_sub26_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_is_32b \ALU_is_32b$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_is_32b \ALU_dec_sub22_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_is_32b \ALU_is_32b$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_is_32b \ALU_is_32b$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_is_32b \ALU_is_32b$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_is_32b \ALU_is_32b$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_is_32b \ALU_is_32b$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_is_32b \ALU_is_32b$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_is_32b \ALU_is_32b$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_is_32b \ALU_is_32b$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_is_32b \ALU_is_32b$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_is_32b \ALU_dec_sub8_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_is_32b \ALU_is_32b$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_is_32b \ALU_is_32b$169 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$182 + process $group_33 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \ALU_sgn \ALU_dec_sub10_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \ALU_sgn \ALU_sgn$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \ALU_sgn \ALU_dec_sub0_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \ALU_sgn \ALU_dec_sub26_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \ALU_sgn \ALU_sgn$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \ALU_sgn \ALU_dec_sub22_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \ALU_sgn \ALU_sgn$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \ALU_sgn \ALU_sgn$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \ALU_sgn \ALU_sgn$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \ALU_sgn \ALU_sgn$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \ALU_sgn \ALU_sgn$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \ALU_sgn \ALU_sgn$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \ALU_sgn \ALU_sgn$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \ALU_sgn \ALU_sgn$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \ALU_sgn \ALU_sgn$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \ALU_sgn \ALU_dec_sub8_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \ALU_sgn \ALU_sgn$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \ALU_sgn \ALU_sgn$182 + end + sync init + end + connect \ALU_function_unit$1 11'00000000000 + connect \ALU_function_unit$2 11'00000000000 + connect \ALU_function_unit$3 11'00000000000 + connect \ALU_function_unit$4 11'00000000000 + connect \ALU_function_unit$5 11'00000000000 + connect \ALU_function_unit$6 11'00000000000 + connect \ALU_function_unit$7 11'00000000000 + connect \ALU_function_unit$8 11'00000000000 + connect \ALU_function_unit$9 11'00000000000 + connect \ALU_function_unit$10 11'00000000000 + connect \ALU_function_unit$11 11'00000000000 + connect \ALU_function_unit$12 11'00000000000 + connect \ALU_function_unit$13 11'00000000000 + connect \ALU_internal_op$14 7'0000000 + connect \ALU_internal_op$15 7'0000000 + connect \ALU_internal_op$16 7'0000000 + connect \ALU_internal_op$17 7'0000000 + connect \ALU_internal_op$18 7'0000000 + connect \ALU_internal_op$19 7'0000000 + connect \ALU_internal_op$20 7'0000000 + connect \ALU_internal_op$21 7'0000000 + connect \ALU_internal_op$22 7'0000000 + connect \ALU_internal_op$23 7'0000000 + connect \ALU_internal_op$24 7'0000000 + connect \ALU_internal_op$25 7'0000000 + connect \ALU_internal_op$26 7'0000000 + connect \ALU_in1_sel$27 3'000 + connect \ALU_in1_sel$28 3'000 + connect \ALU_in1_sel$29 3'000 + connect \ALU_in1_sel$30 3'000 + connect \ALU_in1_sel$31 3'000 + connect \ALU_in1_sel$32 3'000 + connect \ALU_in1_sel$33 3'000 + connect \ALU_in1_sel$34 3'000 + connect \ALU_in1_sel$35 3'000 + connect \ALU_in1_sel$36 3'000 + connect \ALU_in1_sel$37 3'000 + connect \ALU_in1_sel$38 3'000 + connect \ALU_in1_sel$39 3'000 + connect \ALU_in2_sel$40 4'0000 + connect \ALU_in2_sel$41 4'0000 + connect \ALU_in2_sel$42 4'0000 + connect \ALU_in2_sel$43 4'0000 + connect \ALU_in2_sel$44 4'0000 + connect \ALU_in2_sel$45 4'0000 + connect \ALU_in2_sel$46 4'0000 + connect \ALU_in2_sel$47 4'0000 + connect \ALU_in2_sel$48 4'0000 + connect \ALU_in2_sel$49 4'0000 + connect \ALU_in2_sel$50 4'0000 + connect \ALU_in2_sel$51 4'0000 + connect \ALU_in2_sel$52 4'0000 + connect \ALU_cr_in$53 3'000 + connect \ALU_cr_in$54 3'000 + connect \ALU_cr_in$55 3'000 + connect \ALU_cr_in$56 3'000 + connect \ALU_cr_in$57 3'000 + connect \ALU_cr_in$58 3'000 + connect \ALU_cr_in$59 3'000 + connect \ALU_cr_in$60 3'000 + connect \ALU_cr_in$61 3'000 + connect \ALU_cr_in$62 3'000 + connect \ALU_cr_in$63 3'000 + connect \ALU_cr_in$64 3'000 + connect \ALU_cr_in$65 3'000 + connect \ALU_cr_out$66 3'000 + connect \ALU_cr_out$67 3'000 + connect \ALU_cr_out$68 3'000 + connect \ALU_cr_out$69 3'000 + connect \ALU_cr_out$70 3'000 + connect \ALU_cr_out$71 3'000 + connect \ALU_cr_out$72 3'000 + connect \ALU_cr_out$73 3'000 + connect \ALU_cr_out$74 3'000 + connect \ALU_cr_out$75 3'000 + connect \ALU_cr_out$76 3'000 + connect \ALU_cr_out$77 3'000 + connect \ALU_cr_out$78 3'000 + connect \ALU_ldst_len$79 4'0000 + connect \ALU_ldst_len$80 4'0000 + connect \ALU_ldst_len$81 4'0000 + connect \ALU_ldst_len$82 4'0000 + connect \ALU_ldst_len$83 4'0000 + connect \ALU_ldst_len$84 4'0000 + connect \ALU_ldst_len$85 4'0000 + connect \ALU_ldst_len$86 4'0000 + connect \ALU_ldst_len$87 4'0000 + connect \ALU_ldst_len$88 4'0000 + connect \ALU_ldst_len$89 4'0000 + connect \ALU_ldst_len$90 4'0000 + connect \ALU_ldst_len$91 4'0000 + connect \ALU_rc_sel$92 2'00 + connect \ALU_rc_sel$93 2'00 + connect \ALU_rc_sel$94 2'00 + connect \ALU_rc_sel$95 2'00 + connect \ALU_rc_sel$96 2'00 + connect \ALU_rc_sel$97 2'00 + connect \ALU_rc_sel$98 2'00 + connect \ALU_rc_sel$99 2'00 + connect \ALU_rc_sel$100 2'00 + connect \ALU_rc_sel$101 2'00 + connect \ALU_rc_sel$102 2'00 + connect \ALU_rc_sel$103 2'00 + connect \ALU_rc_sel$104 2'00 + connect \ALU_cry_in$105 2'00 + connect \ALU_cry_in$106 2'00 + connect \ALU_cry_in$107 2'00 + connect \ALU_cry_in$108 2'00 + connect \ALU_cry_in$109 2'00 + connect \ALU_cry_in$110 2'00 + connect \ALU_cry_in$111 2'00 + connect \ALU_cry_in$112 2'00 + connect \ALU_cry_in$113 2'00 + connect \ALU_cry_in$114 2'00 + connect \ALU_cry_in$115 2'00 + connect \ALU_cry_in$116 2'00 + connect \ALU_cry_in$117 2'00 + connect \ALU_inv_a$118 1'0 + connect \ALU_inv_a$119 1'0 + connect \ALU_inv_a$120 1'0 + connect \ALU_inv_a$121 1'0 + connect \ALU_inv_a$122 1'0 + connect \ALU_inv_a$123 1'0 + connect \ALU_inv_a$124 1'0 + connect \ALU_inv_a$125 1'0 + connect \ALU_inv_a$126 1'0 + connect \ALU_inv_a$127 1'0 + connect \ALU_inv_a$128 1'0 + connect \ALU_inv_a$129 1'0 + connect \ALU_inv_a$130 1'0 + connect \ALU_inv_out$131 1'0 + connect \ALU_inv_out$132 1'0 + connect \ALU_inv_out$133 1'0 + connect \ALU_inv_out$134 1'0 + connect \ALU_inv_out$135 1'0 + connect \ALU_inv_out$136 1'0 + connect \ALU_inv_out$137 1'0 + connect \ALU_inv_out$138 1'0 + connect \ALU_inv_out$139 1'0 + connect \ALU_inv_out$140 1'0 + connect \ALU_inv_out$141 1'0 + connect \ALU_inv_out$142 1'0 + connect \ALU_inv_out$143 1'0 + connect \ALU_cry_out$144 1'0 + connect \ALU_cry_out$145 1'0 + connect \ALU_cry_out$146 1'0 + connect \ALU_cry_out$147 1'0 + connect \ALU_cry_out$148 1'0 + connect \ALU_cry_out$149 1'0 + connect \ALU_cry_out$150 1'0 + connect \ALU_cry_out$151 1'0 + connect \ALU_cry_out$152 1'0 + connect \ALU_cry_out$153 1'0 + connect \ALU_cry_out$154 1'0 + connect \ALU_cry_out$155 1'0 + connect \ALU_cry_out$156 1'0 + connect \ALU_is_32b$157 1'0 + connect \ALU_is_32b$158 1'0 + connect \ALU_is_32b$159 1'0 + connect \ALU_is_32b$160 1'0 + connect \ALU_is_32b$161 1'0 + connect \ALU_is_32b$162 1'0 + connect \ALU_is_32b$163 1'0 + connect \ALU_is_32b$164 1'0 + connect \ALU_is_32b$165 1'0 + connect \ALU_is_32b$166 1'0 + connect \ALU_is_32b$167 1'0 + connect \ALU_is_32b$168 1'0 + connect \ALU_is_32b$169 1'0 + connect \ALU_sgn$170 1'0 + connect \ALU_sgn$171 1'0 + connect \ALU_sgn$172 1'0 + connect \ALU_sgn$173 1'0 + connect \ALU_sgn$174 1'0 + connect \ALU_sgn$175 1'0 + connect \ALU_sgn$176 1'0 + connect \ALU_sgn$177 1'0 + connect \ALU_sgn$178 1'0 + connect \ALU_sgn$179 1'0 + connect \ALU_sgn$180 1'0 + connect \ALU_sgn$181 1'0 + connect \ALU_sgn$182 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec58" +module \ALU_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec62" +module \ALU_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec" +module \dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \ALU_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \ALU_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \ALU_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 8 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 9 \ALU_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 10 \ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \ALU_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 17 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 18 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 19 \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 20 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 21 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 22 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 23 \ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 24 \ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 25 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 26 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 27 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 28 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 29 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 30 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 31 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 32 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec19_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec19_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec19_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec19_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec19_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec19_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec19_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec19_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec19_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec19_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec19_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec19_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec19_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec19_ALU_sgn + cell \ALU_dec19 \ALU_dec19 + connect \opcode_in \ALU_dec19_opcode_in + connect \ALU_function_unit \ALU_dec19_ALU_function_unit + connect \ALU_internal_op \ALU_dec19_ALU_internal_op + connect \ALU_in1_sel \ALU_dec19_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec19_ALU_in2_sel + connect \ALU_cr_in \ALU_dec19_ALU_cr_in + connect \ALU_cr_out \ALU_dec19_ALU_cr_out + connect \ALU_ldst_len \ALU_dec19_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec19_ALU_rc_sel + connect \ALU_cry_in \ALU_dec19_ALU_cry_in + connect \ALU_inv_a \ALU_dec19_ALU_inv_a + connect \ALU_inv_out \ALU_dec19_ALU_inv_out + connect \ALU_cry_out \ALU_dec19_ALU_cry_out + connect \ALU_is_32b \ALU_dec19_ALU_is_32b + connect \ALU_sgn \ALU_dec19_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec30_opcode_in + cell \ALU_dec30 \ALU_dec30 + connect \opcode_in \ALU_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_dec31_ALU_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_dec31_ALU_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec31_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec31_ALU_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec31_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_dec31_ALU_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_dec31_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec31_ALU_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_dec31_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec31_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec31_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec31_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec31_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_dec31_ALU_sgn + cell \ALU_dec31 \ALU_dec31 + connect \opcode_in \ALU_dec31_opcode_in + connect \ALU_function_unit \ALU_dec31_ALU_function_unit + connect \ALU_internal_op \ALU_dec31_ALU_internal_op + connect \ALU_in1_sel \ALU_dec31_ALU_in1_sel + connect \ALU_in2_sel \ALU_dec31_ALU_in2_sel + connect \ALU_cr_in \ALU_dec31_ALU_cr_in + connect \ALU_cr_out \ALU_dec31_ALU_cr_out + connect \ALU_ldst_len \ALU_dec31_ALU_ldst_len + connect \ALU_rc_sel \ALU_dec31_ALU_rc_sel + connect \ALU_cry_in \ALU_dec31_ALU_cry_in + connect \ALU_inv_a \ALU_dec31_ALU_inv_a + connect \ALU_inv_out \ALU_dec31_ALU_inv_out + connect \ALU_cry_out \ALU_dec31_ALU_cry_out + connect \ALU_is_32b \ALU_dec31_ALU_is_32b + connect \ALU_sgn \ALU_dec31_ALU_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec58_opcode_in + cell \ALU_dec58 \ALU_dec58 + connect \opcode_in \ALU_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \ALU_dec62_opcode_in + cell \ALU_dec62 \ALU_dec62 + connect \opcode_in \ALU_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \ALU_dec19_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \ALU_dec30_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \ALU_dec31_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \ALU_dec58_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \ALU_dec62_opcode_in 32'00000000000000000000000000000000 + assign \ALU_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \ALU_function_unit$3 + process $group_6 + assign \ALU_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_function_unit \ALU_dec19_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_function_unit \ALU_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_function_unit \ALU_dec31_ALU_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_function_unit \ALU_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_function_unit \ALU_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_function_unit 11'00000000010 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \ALU_internal_op$6 + process $group_7 + assign \ALU_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_internal_op \ALU_dec19_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_internal_op \ALU_internal_op$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_internal_op \ALU_dec31_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_internal_op \ALU_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_internal_op \ALU_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_internal_op 7'0000010 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$7 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$8 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_in1_sel$9 + process $group_8 + assign \ALU_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_in1_sel \ALU_dec19_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_in1_sel \ALU_in1_sel$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_in1_sel \ALU_dec31_ALU_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_in1_sel \ALU_in1_sel$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_in1_sel \ALU_in1_sel$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_in1_sel 3'001 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$10 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$11 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_in2_sel$12 + process $group_9 + assign \ALU_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_in2_sel \ALU_dec19_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_in2_sel \ALU_in2_sel$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_in2_sel \ALU_dec31_ALU_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_in2_sel \ALU_in2_sel$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_in2_sel \ALU_in2_sel$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_in2_sel 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_in2_sel 4'0011 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$13 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$14 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_in$15 + process $group_10 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_cr_in \ALU_dec19_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_cr_in \ALU_cr_in$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_cr_in \ALU_dec31_ALU_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_cr_in \ALU_cr_in$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_cr_in \ALU_cr_in$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_cr_in 3'000 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$16 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$17 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \ALU_cr_out$18 + process $group_11 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_cr_out \ALU_dec19_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_cr_out \ALU_cr_out$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_cr_out \ALU_dec31_ALU_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_cr_out \ALU_cr_out$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_cr_out \ALU_cr_out$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_cr_out 3'000 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$19 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$20 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ALU_ldst_len$21 + process $group_12 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_ldst_len \ALU_dec19_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_ldst_len \ALU_ldst_len$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_ldst_len \ALU_dec31_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_ldst_len \ALU_ldst_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_ldst_len \ALU_ldst_len$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_ldst_len 4'0000 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$22 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$23 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_rc_sel$24 + process $group_13 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_rc_sel \ALU_dec19_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_rc_sel \ALU_rc_sel$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_rc_sel \ALU_dec31_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_rc_sel \ALU_rc_sel$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_rc_sel \ALU_rc_sel$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_rc_sel 2'00 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \ALU_cry_in$27 + process $group_14 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_cry_in \ALU_dec19_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_cry_in \ALU_cry_in$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_cry_in \ALU_dec31_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_cry_in \ALU_cry_in$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_cry_in \ALU_cry_in$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_cry_in 2'01 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_a$30 + process $group_15 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_inv_a \ALU_dec19_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_inv_a \ALU_inv_a$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_inv_a \ALU_dec31_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_inv_a \ALU_inv_a$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_inv_a \ALU_inv_a$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_inv_a 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_inv_out$33 + process $group_16 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_inv_out \ALU_dec19_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_inv_out \ALU_inv_out$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_inv_out \ALU_dec31_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_inv_out \ALU_inv_out$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_inv_out \ALU_inv_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_inv_out 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_cry_out$36 + process $group_17 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_cry_out \ALU_dec19_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_cry_out \ALU_cry_out$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_cry_out \ALU_dec31_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_cry_out \ALU_cry_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_cry_out \ALU_cry_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_cry_out 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_is_32b$39 + process $group_18 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_is_32b \ALU_dec19_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_is_32b \ALU_is_32b$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_is_32b \ALU_dec31_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_is_32b \ALU_is_32b$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_is_32b \ALU_is_32b$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_is_32b 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \ALU_sgn$42 + process $group_19 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \ALU_sgn \ALU_dec19_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \ALU_sgn \ALU_sgn$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \ALU_sgn \ALU_dec31_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \ALU_sgn \ALU_sgn$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \ALU_sgn \ALU_sgn$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \ALU_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \ALU_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \ALU_sgn 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$43 + process $group_20 + assign \opcode_switch$43 32'00000000000000000000000000000000 + assign \opcode_switch$43 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $45 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $44 + end + process $group_21 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $44 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_RS + process $group_22 + assign \ALU_RS 5'00000 + assign \ALU_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_RT + process $group_23 + assign \ALU_RT 5'00000 + assign \ALU_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_24 + assign \ALU_RA 5'00000 + assign \ALU_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_RB + process $group_25 + assign \ALU_RB 5'00000 + assign \ALU_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_26 + assign \ALU_SI 16'0000000000000000 + assign \ALU_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_27 + assign \ALU_UI 16'0000000000000000 + assign \ALU_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \ALU_L + process $group_28 + assign \ALU_L 1'0 + assign \ALU_L { \opcode_in [21] } + sync init + end + process $group_29 + assign \ALU_SH32 5'00000 + assign \ALU_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_30 + assign \ALU_sh 6'000000 + assign \ALU_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_MB32 + process $group_31 + assign \ALU_MB32 5'00000 + assign \ALU_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_ME32 + process $group_32 + assign \ALU_ME32 5'00000 + assign \ALU_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_33 + assign \ALU_LI 24'000000000000000000000000 + assign \ALU_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \ALU_LK + process $group_34 + assign \ALU_LK 1'0 + assign \ALU_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \ALU_AA + process $group_35 + assign \ALU_AA 1'0 + assign \ALU_AA { \opcode_in [1] } + sync init + end + process $group_36 + assign \ALU_Rc 1'0 + assign \ALU_Rc { \opcode_in [0] } + sync init + end + process $group_37 + assign \ALU_OE 1'0 + assign \ALU_OE { \opcode_in [10] } + sync init + end + process $group_38 + assign \ALU_BD 14'00000000000000 + assign \ALU_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \ALU_BF + process $group_39 + assign \ALU_BF 3'000 + assign \ALU_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \ALU_CR + process $group_40 + assign \ALU_CR 10'0000000000 + assign \ALU_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_41 + assign \ALU_BB 5'00000 + assign \ALU_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_42 + assign \ALU_BA 5'00000 + assign \ALU_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_43 + assign \ALU_BT 5'00000 + assign \ALU_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_44 + assign \ALU_FXM 8'00000000 + assign \ALU_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_BO + process $group_45 + assign \ALU_BO 5'00000 + assign \ALU_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_46 + assign \ALU_BI 5'00000 + assign \ALU_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \ALU_BH + process $group_47 + assign \ALU_BH 2'00 + assign \ALU_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \ALU_D + process $group_48 + assign \ALU_D 16'0000000000000000 + assign \ALU_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_49 + assign \ALU_DS 14'00000000000000 + assign \ALU_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_TO + process $group_50 + assign \ALU_TO 5'00000 + assign \ALU_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_51 + assign \ALU_BC 5'00000 + assign \ALU_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_SH + process $group_52 + assign \ALU_SH 5'00000 + assign \ALU_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_ME + process $group_53 + assign \ALU_ME 5'00000 + assign \ALU_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \ALU_MB + process $group_54 + assign \ALU_MB 5'00000 + assign \ALU_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \ALU_SPR + process $group_55 + assign \ALU_SPR 10'0000000000 + assign \ALU_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_56 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_57 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_58 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_59 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_60 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_61 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_62 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_63 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_64 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_65 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_66 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_67 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_68 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_69 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_70 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_71 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_72 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_73 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_74 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_75 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_76 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_77 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_78 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_79 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_80 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_81 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_82 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_83 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_84 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_85 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_86 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_87 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_88 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_89 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_90 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_91 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_92 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_93 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_94 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_95 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_96 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_97 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_98 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_99 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_100 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_101 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_102 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_103 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_104 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_105 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_106 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_107 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_108 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_109 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_110 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_111 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_112 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_113 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_114 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_115 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_116 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_117 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_118 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_119 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_120 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_121 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_122 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_123 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_124 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_125 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_126 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_127 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_128 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_129 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_130 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_131 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_132 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_133 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_134 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_135 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_136 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_137 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_138 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_139 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_140 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_141 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_142 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_143 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_144 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_145 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_146 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_147 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_148 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_149 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_150 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_151 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_152 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_153 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_154 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_155 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_156 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_157 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_158 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_159 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_160 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_161 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_162 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_163 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_164 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_165 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_166 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_167 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_168 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_169 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_170 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_171 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_172 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_173 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_174 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_175 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_176 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_177 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_178 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_179 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_180 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_181 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_182 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_183 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_184 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_185 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_186 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_187 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_188 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_189 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_190 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_191 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_192 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_193 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_194 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_195 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_196 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_197 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_198 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_199 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_200 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_201 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_202 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_203 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_204 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_205 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_206 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_207 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_208 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_209 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_210 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_211 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_212 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_213 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_214 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_215 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_216 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_217 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_218 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_219 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_220 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_221 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_222 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_223 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_224 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_225 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_226 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_227 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_228 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_229 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_230 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_231 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_232 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_233 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_234 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_235 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_236 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_237 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_238 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_239 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_240 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_241 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_242 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_243 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_244 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_245 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_246 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_247 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_248 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_249 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_250 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_251 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_252 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_253 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_254 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_255 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_256 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_257 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_258 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_259 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_260 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_261 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_262 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_263 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_264 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_265 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_266 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_267 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_268 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_269 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_270 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_271 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_272 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_273 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_274 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_275 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_276 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_277 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_278 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_279 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_280 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_281 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_282 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_283 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_284 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_285 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_286 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_287 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_288 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_289 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_290 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_291 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_292 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_293 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_294 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_295 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_296 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_297 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_298 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_299 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_300 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_301 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_302 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_303 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_304 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_305 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_306 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_307 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_308 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_309 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_310 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_311 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_312 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_313 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_314 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_315 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_316 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_317 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_318 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_319 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_320 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_321 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_322 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_323 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_324 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_325 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_326 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_327 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_328 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_329 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_330 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_331 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_332 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_333 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_334 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_335 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_336 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_337 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_338 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_339 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_340 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_341 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_342 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_343 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_344 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_345 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_346 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_347 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \ALU_function_unit$1 11'00000000000 + connect \ALU_function_unit$2 11'00000000000 + connect \ALU_function_unit$3 11'00000000000 + connect \ALU_internal_op$4 7'0000000 + connect \ALU_internal_op$5 7'0000000 + connect \ALU_internal_op$6 7'0000000 + connect \ALU_in1_sel$7 3'000 + connect \ALU_in1_sel$8 3'000 + connect \ALU_in1_sel$9 3'000 + connect \ALU_in2_sel$10 4'0000 + connect \ALU_in2_sel$11 4'0000 + connect \ALU_in2_sel$12 4'0000 + connect \ALU_cr_in$13 3'000 + connect \ALU_cr_in$14 3'000 + connect \ALU_cr_in$15 3'000 + connect \ALU_cr_out$16 3'000 + connect \ALU_cr_out$17 3'000 + connect \ALU_cr_out$18 3'000 + connect \ALU_ldst_len$19 4'0000 + connect \ALU_ldst_len$20 4'0000 + connect \ALU_ldst_len$21 4'0000 + connect \ALU_rc_sel$22 2'00 + connect \ALU_rc_sel$23 2'00 + connect \ALU_rc_sel$24 2'00 + connect \ALU_cry_in$25 2'00 + connect \ALU_cry_in$26 2'00 + connect \ALU_cry_in$27 2'00 + connect \ALU_inv_a$28 1'0 + connect \ALU_inv_a$29 1'0 + connect \ALU_inv_a$30 1'0 + connect \ALU_inv_out$31 1'0 + connect \ALU_inv_out$32 1'0 + connect \ALU_inv_out$33 1'0 + connect \ALU_cry_out$34 1'0 + connect \ALU_cry_out$35 1'0 + connect \ALU_cry_out$36 1'0 + connect \ALU_is_32b$37 1'0 + connect \ALU_is_32b$38 1'0 + connect \ALU_is_32b$39 1'0 + connect \ALU_sgn$40 1'0 + connect \ALU_sgn$41 1'0 + connect \ALU_sgn$42 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_rc" +module \dec_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \ALU_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_oe" +module \dec_oe + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \ALU_OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \ALU_OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in.ppick" +module \ppick + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in" +module \dec_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \ALU_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \ALU_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \ALU_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \ALU_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \ALU_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out.ppick" +module \ppick$136 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out" +module \dec_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 5 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$136 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \ALU_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_ai" +module \dec_ai + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 output 1 \immz_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 2 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + process $group_0 + assign \ra 5'00000 + assign \ra \ALU_RA + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B $3 + connect \Y $5 + end + process $group_1 + assign \immz_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + case 1'1 + assign \immz_out 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_bi" +module \dec_bi + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \ALU_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \ALU_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \ALU_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU" +module \dec_ALU + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \ALU_ALU__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \ALU_ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \ALU_ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \ALU_ALU__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 6 \ALU_ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 7 \ALU_ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \ALU_ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \ALU_ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \ALU_ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \ALU_ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \ALU_ALU__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \ALU_ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 17 \ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \ALU_ALU__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \ALU_ALU__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_ALU_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_ALU_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_ALU_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_ALU_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_ALU_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_ALU_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_ALU_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_cr_in \dec_ALU_cr_in + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_RA \dec_ALU_RA + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_sh \dec_ALU_sh + connect \ALU_LI \dec_ALU_LI + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_OE \dec_ALU_OE + connect \ALU_BD \dec_ALU_BD + connect \ALU_BB \dec_ALU_BB + connect \ALU_BA \dec_ALU_BA + connect \ALU_BT \dec_ALU_BT + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_BI \dec_ALU_BI + connect \ALU_DS \dec_ALU_DS + connect \ALU_BC \dec_ALU_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \ALU_Rc \dec_ALU_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe \dec_oe + connect \sel_in \dec_oe_sel_in + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \ALU_OE \dec_ALU_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_BB \dec_ALU_BB + connect \ALU_BA \dec_ALU_BA + connect \ALU_BT \dec_ALU_BT + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_BI \dec_ALU_BI + connect \ALU_BC \dec_ALU_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + cell \dec_cr_out \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \ALU_internal_op \dec_ALU_internal_op + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \ALU_FXM \dec_ALU_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 \dec_ai_immz_out + cell \dec_ai \dec_ai + connect \sel_in \dec_ai_sel_in + connect \immz_out \dec_ai_immz_out + connect \ALU_RA \dec_ALU_RA + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_sh \dec_ALU_sh + connect \ALU_LI \dec_ALU_LI + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + end + process $group_0 + assign \ALU_ALU__insn 32'00000000000000000000000000000000 + assign \ALU_ALU__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_ALU_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_ALU_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_ALU_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_ALU_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \ALU_ALU__insn_type 7'0000000 + assign \ALU_ALU__insn_type \dec_ALU_internal_op + sync init + end + process $group_11 + assign \ALU_ALU__fn_unit 11'00000000000 + assign \ALU_ALU__fn_unit \dec_ALU_function_unit + sync init + end + process $group_12 + assign \dec_ai_sel_in 3'000 + assign \dec_ai_sel_in \dec_ALU_in1_sel + sync init + end + process $group_13 + assign \ALU_ALU__zero_a 1'0 + assign \ALU_ALU__zero_a \dec_ai_immz_out + sync init + end + process $group_14 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_ALU_in2_sel + sync init + end + process $group_15 + assign \ALU_ALU__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ALU_ALU__imm_data__ok 1'0 + assign { \ALU_ALU__imm_data__ok \ALU_ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_17 + assign \ALU_ALU__rc__rc 1'0 + assign \ALU_ALU__rc__ok 1'0 + assign { \ALU_ALU__rc__ok \ALU_ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + sync init + end + process $group_19 + assign \ALU_ALU__oe__oe 1'0 + assign \ALU_ALU__oe__ok 1'0 + assign { \ALU_ALU__oe__ok \ALU_ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + sync init + end + process $group_21 + assign \ALU_ALU__write_cr0 1'0 + assign \ALU_ALU__write_cr0 \dec_cr_out_cr_bitfield_ok + sync init + end + process $group_22 + assign \ALU_ALU__data_len 4'0000 + assign \ALU_ALU__data_len \dec_ALU_ldst_len + sync init + end + process $group_23 + assign \ALU_ALU__invert_in 1'0 + assign \ALU_ALU__invert_in \dec_ALU_inv_a + sync init + end + process $group_24 + assign \ALU_ALU__invert_out 1'0 + assign \ALU_ALU__invert_out \dec_ALU_inv_out + sync init + end + process $group_25 + assign \ALU_ALU__input_carry 2'00 + assign \ALU_ALU__input_carry \dec_ALU_cry_in + sync init + end + process $group_26 + assign \ALU_ALU__output_carry 1'0 + assign \ALU_ALU__output_carry \dec_ALU_cry_out + sync init + end + process $group_27 + assign \ALU_ALU__is_32bit 1'0 + assign \ALU_ALU__is_32bit \dec_ALU_is_32b + sync init + end + process $group_28 + assign \ALU_ALU__is_signed 1'0 + assign \ALU_ALU__is_signed \dec_ALU_sgn + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec19" +module \CR_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + process $group_1 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000000000 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100000001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010000001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100100001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011100001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000100001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0111000001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0110100001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011000001 + assign \CR_function_unit 11'00001000000 + end + sync init + end + process $group_2 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000000000 + assign \CR_internal_op 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100000001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010000001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100100001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011100001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000100001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0111000001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0110100001 + assign \CR_internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011000001 + assign \CR_internal_op 7'1000101 + end + sync init + end + process $group_3 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000000000 + assign \CR_cr_in 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100000001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010000001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100100001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011100001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000100001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0111000001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0110100001 + assign \CR_cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011000001 + assign \CR_cr_in 3'100 + end + sync init + end + process $group_4 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000000000 + assign \CR_cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100000001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010000001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100100001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011100001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000100001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0111000001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0110100001 + assign \CR_cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011000001 + assign \CR_cr_out 3'011 + end + sync init + end + process $group_5 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000000000 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100000001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0010000001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0100100001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011100001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000100001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0111000001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0110100001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0011000001 + assign \CR_rc_sel 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_6 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec30" +module \CR_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub10" +module \CR_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub28" +module \CR_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub0" +module \CR_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_function_unit 11'00001000000 + end + sync init + end + process $group_2 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_internal_op 7'0111011 + end + sync init + end + process $group_3 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_cr_in 3'011 + end + sync init + end + process $group_4 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_cr_out 3'000 + end + sync init + end + process $group_5 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_rc_sel 2'00 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub26" +module \CR_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub19" +module \CR_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_function_unit 11'00001000000 + end + sync init + end + process $group_2 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_internal_op 7'0101101 + end + sync init + end + process $group_3 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_cr_in 3'110 + end + sync init + end + process $group_4 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_cr_out 3'000 + end + sync init + end + process $group_5 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_rc_sel 2'00 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub22" +module \CR_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub9" +module \CR_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub11" +module \CR_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub27" +module \CR_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub15" +module \CR_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \CR_function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \CR_function_unit 11'00001000000 + end + sync init + end + process $group_2 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \CR_internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \CR_internal_op 7'0100011 + end + sync init + end + process $group_3 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \CR_cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \CR_cr_in 3'101 + end + sync init + end + process $group_4 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \CR_cr_out 3'000 + end + sync init + end + process $group_5 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \CR_rc_sel 2'00 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub20" +module \CR_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub21" +module \CR_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub23" +module \CR_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub16" +module \CR_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_function_unit 11'00001000000 + end + sync init + end + process $group_2 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_internal_op 7'0110000 + end + sync init + end + process $group_3 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_cr_in 3'110 + end + sync init + end + process $group_4 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_cr_out 3'100 + end + sync init + end + process $group_5 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \CR_rc_sel 2'00 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub18" +module \CR_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub8" +module \CR_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub24" +module \CR_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub4" +module \CR_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31" +module \CR_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub10_opcode_in + cell \CR_dec_sub10 \CR_dec_sub10 + connect \opcode_in \CR_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub28_opcode_in + cell \CR_dec_sub28 \CR_dec_sub28 + connect \opcode_in \CR_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub0_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_dec_sub0_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_dec_sub0_CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub0_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub0_CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_dec_sub0_CR_rc_sel + cell \CR_dec_sub0 \CR_dec_sub0 + connect \opcode_in \CR_dec_sub0_opcode_in + connect \CR_function_unit \CR_dec_sub0_CR_function_unit + connect \CR_internal_op \CR_dec_sub0_CR_internal_op + connect \CR_cr_in \CR_dec_sub0_CR_cr_in + connect \CR_cr_out \CR_dec_sub0_CR_cr_out + connect \CR_rc_sel \CR_dec_sub0_CR_rc_sel + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub26_opcode_in + cell \CR_dec_sub26 \CR_dec_sub26 + connect \opcode_in \CR_dec_sub26_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_dec_sub19_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_dec_sub19_CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub19_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub19_CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_dec_sub19_CR_rc_sel + cell \CR_dec_sub19 \CR_dec_sub19 + connect \opcode_in \CR_dec_sub19_opcode_in + connect \CR_function_unit \CR_dec_sub19_CR_function_unit + connect \CR_internal_op \CR_dec_sub19_CR_internal_op + connect \CR_cr_in \CR_dec_sub19_CR_cr_in + connect \CR_cr_out \CR_dec_sub19_CR_cr_out + connect \CR_rc_sel \CR_dec_sub19_CR_rc_sel + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub22_opcode_in + cell \CR_dec_sub22 \CR_dec_sub22 + connect \opcode_in \CR_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub9_opcode_in + cell \CR_dec_sub9 \CR_dec_sub9 + connect \opcode_in \CR_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub11_opcode_in + cell \CR_dec_sub11 \CR_dec_sub11 + connect \opcode_in \CR_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub27_opcode_in + cell \CR_dec_sub27 \CR_dec_sub27 + connect \opcode_in \CR_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub15_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_dec_sub15_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_dec_sub15_CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub15_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub15_CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_dec_sub15_CR_rc_sel + cell \CR_dec_sub15 \CR_dec_sub15 + connect \opcode_in \CR_dec_sub15_opcode_in + connect \CR_function_unit \CR_dec_sub15_CR_function_unit + connect \CR_internal_op \CR_dec_sub15_CR_internal_op + connect \CR_cr_in \CR_dec_sub15_CR_cr_in + connect \CR_cr_out \CR_dec_sub15_CR_cr_out + connect \CR_rc_sel \CR_dec_sub15_CR_rc_sel + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub20_opcode_in + cell \CR_dec_sub20 \CR_dec_sub20 + connect \opcode_in \CR_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub21_opcode_in + cell \CR_dec_sub21 \CR_dec_sub21 + connect \opcode_in \CR_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub23_opcode_in + cell \CR_dec_sub23 \CR_dec_sub23 + connect \opcode_in \CR_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub16_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_dec_sub16_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_dec_sub16_CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub16_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec_sub16_CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_dec_sub16_CR_rc_sel + cell \CR_dec_sub16 \CR_dec_sub16 + connect \opcode_in \CR_dec_sub16_opcode_in + connect \CR_function_unit \CR_dec_sub16_CR_function_unit + connect \CR_internal_op \CR_dec_sub16_CR_internal_op + connect \CR_cr_in \CR_dec_sub16_CR_cr_in + connect \CR_cr_out \CR_dec_sub16_CR_cr_out + connect \CR_rc_sel \CR_dec_sub16_CR_rc_sel + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub18_opcode_in + cell \CR_dec_sub18 \CR_dec_sub18 + connect \opcode_in \CR_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub8_opcode_in + cell \CR_dec_sub8 \CR_dec_sub8 + connect \opcode_in \CR_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub24_opcode_in + cell \CR_dec_sub24 \CR_dec_sub24 + connect \opcode_in \CR_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec_sub4_opcode_in + cell \CR_dec_sub4 \CR_dec_sub4 + connect \opcode_in \CR_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \CR_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \CR_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \CR_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \CR_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \CR_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \CR_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \CR_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \CR_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \CR_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \CR_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \CR_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \CR_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \CR_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \CR_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \CR_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \CR_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \CR_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \CR_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$14 + process $group_20 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \CR_function_unit \CR_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \CR_function_unit \CR_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \CR_function_unit \CR_dec_sub0_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \CR_function_unit \CR_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \CR_function_unit \CR_dec_sub19_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \CR_function_unit \CR_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \CR_function_unit \CR_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \CR_function_unit \CR_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \CR_function_unit \CR_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \CR_function_unit \CR_dec_sub15_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \CR_function_unit \CR_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \CR_function_unit \CR_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \CR_function_unit \CR_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \CR_function_unit \CR_dec_sub16_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \CR_function_unit \CR_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \CR_function_unit \CR_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \CR_function_unit \CR_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \CR_function_unit \CR_function_unit$14 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$15 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$28 + process $group_21 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \CR_internal_op \CR_internal_op$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \CR_internal_op \CR_internal_op$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \CR_internal_op \CR_dec_sub0_CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \CR_internal_op \CR_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \CR_internal_op \CR_dec_sub19_CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \CR_internal_op \CR_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \CR_internal_op \CR_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \CR_internal_op \CR_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \CR_internal_op \CR_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \CR_internal_op \CR_dec_sub15_CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \CR_internal_op \CR_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \CR_internal_op \CR_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \CR_internal_op \CR_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \CR_internal_op \CR_dec_sub16_CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \CR_internal_op \CR_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \CR_internal_op \CR_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \CR_internal_op \CR_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \CR_internal_op \CR_internal_op$28 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$29 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$30 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$31 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$32 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$33 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$34 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$35 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$36 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$37 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$38 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$39 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$40 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$41 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$42 + process $group_22 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \CR_cr_in \CR_cr_in$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \CR_cr_in \CR_cr_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \CR_cr_in \CR_dec_sub0_CR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \CR_cr_in \CR_cr_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \CR_cr_in \CR_dec_sub19_CR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \CR_cr_in \CR_cr_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \CR_cr_in \CR_cr_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \CR_cr_in \CR_cr_in$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \CR_cr_in \CR_cr_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \CR_cr_in \CR_dec_sub15_CR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \CR_cr_in \CR_cr_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \CR_cr_in \CR_cr_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \CR_cr_in \CR_cr_in$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \CR_cr_in \CR_dec_sub16_CR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \CR_cr_in \CR_cr_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \CR_cr_in \CR_cr_in$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \CR_cr_in \CR_cr_in$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \CR_cr_in \CR_cr_in$42 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$43 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$44 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$45 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$46 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$47 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$48 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$49 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$50 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$51 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$52 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$53 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$54 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$55 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$56 + process $group_23 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \CR_cr_out \CR_cr_out$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \CR_cr_out \CR_cr_out$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \CR_cr_out \CR_dec_sub0_CR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \CR_cr_out \CR_cr_out$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \CR_cr_out \CR_dec_sub19_CR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \CR_cr_out \CR_cr_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \CR_cr_out \CR_cr_out$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \CR_cr_out \CR_cr_out$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \CR_cr_out \CR_cr_out$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \CR_cr_out \CR_dec_sub15_CR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \CR_cr_out \CR_cr_out$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \CR_cr_out \CR_cr_out$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \CR_cr_out \CR_cr_out$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \CR_cr_out \CR_dec_sub16_CR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \CR_cr_out \CR_cr_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \CR_cr_out \CR_cr_out$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \CR_cr_out \CR_cr_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \CR_cr_out \CR_cr_out$56 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$57 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$58 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$59 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$60 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$61 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$62 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$63 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$64 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$65 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$66 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$67 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$68 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$69 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$70 + process $group_24 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \CR_rc_sel \CR_rc_sel$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \CR_rc_sel \CR_rc_sel$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \CR_rc_sel \CR_dec_sub0_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \CR_rc_sel \CR_rc_sel$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \CR_rc_sel \CR_dec_sub19_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \CR_rc_sel \CR_rc_sel$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \CR_rc_sel \CR_rc_sel$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \CR_rc_sel \CR_rc_sel$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \CR_rc_sel \CR_rc_sel$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \CR_rc_sel \CR_dec_sub15_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \CR_rc_sel \CR_rc_sel$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \CR_rc_sel \CR_rc_sel$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \CR_rc_sel \CR_rc_sel$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \CR_rc_sel \CR_dec_sub16_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \CR_rc_sel \CR_rc_sel$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \CR_rc_sel \CR_rc_sel$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \CR_rc_sel \CR_rc_sel$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \CR_rc_sel \CR_rc_sel$70 + end + sync init + end + connect \CR_function_unit$1 11'00000000000 + connect \CR_function_unit$2 11'00000000000 + connect \CR_function_unit$3 11'00000000000 + connect \CR_function_unit$4 11'00000000000 + connect \CR_function_unit$5 11'00000000000 + connect \CR_function_unit$6 11'00000000000 + connect \CR_function_unit$7 11'00000000000 + connect \CR_function_unit$8 11'00000000000 + connect \CR_function_unit$9 11'00000000000 + connect \CR_function_unit$10 11'00000000000 + connect \CR_function_unit$11 11'00000000000 + connect \CR_function_unit$12 11'00000000000 + connect \CR_function_unit$13 11'00000000000 + connect \CR_function_unit$14 11'00000000000 + connect \CR_internal_op$15 7'0000000 + connect \CR_internal_op$16 7'0000000 + connect \CR_internal_op$17 7'0000000 + connect \CR_internal_op$18 7'0000000 + connect \CR_internal_op$19 7'0000000 + connect \CR_internal_op$20 7'0000000 + connect \CR_internal_op$21 7'0000000 + connect \CR_internal_op$22 7'0000000 + connect \CR_internal_op$23 7'0000000 + connect \CR_internal_op$24 7'0000000 + connect \CR_internal_op$25 7'0000000 + connect \CR_internal_op$26 7'0000000 + connect \CR_internal_op$27 7'0000000 + connect \CR_internal_op$28 7'0000000 + connect \CR_cr_in$29 3'000 + connect \CR_cr_in$30 3'000 + connect \CR_cr_in$31 3'000 + connect \CR_cr_in$32 3'000 + connect \CR_cr_in$33 3'000 + connect \CR_cr_in$34 3'000 + connect \CR_cr_in$35 3'000 + connect \CR_cr_in$36 3'000 + connect \CR_cr_in$37 3'000 + connect \CR_cr_in$38 3'000 + connect \CR_cr_in$39 3'000 + connect \CR_cr_in$40 3'000 + connect \CR_cr_in$41 3'000 + connect \CR_cr_in$42 3'000 + connect \CR_cr_out$43 3'000 + connect \CR_cr_out$44 3'000 + connect \CR_cr_out$45 3'000 + connect \CR_cr_out$46 3'000 + connect \CR_cr_out$47 3'000 + connect \CR_cr_out$48 3'000 + connect \CR_cr_out$49 3'000 + connect \CR_cr_out$50 3'000 + connect \CR_cr_out$51 3'000 + connect \CR_cr_out$52 3'000 + connect \CR_cr_out$53 3'000 + connect \CR_cr_out$54 3'000 + connect \CR_cr_out$55 3'000 + connect \CR_cr_out$56 3'000 + connect \CR_rc_sel$57 2'00 + connect \CR_rc_sel$58 2'00 + connect \CR_rc_sel$59 2'00 + connect \CR_rc_sel$60 2'00 + connect \CR_rc_sel$61 2'00 + connect \CR_rc_sel$62 2'00 + connect \CR_rc_sel$63 2'00 + connect \CR_rc_sel$64 2'00 + connect \CR_rc_sel$65 2'00 + connect \CR_rc_sel$66 2'00 + connect \CR_rc_sel$67 2'00 + connect \CR_rc_sel$68 2'00 + connect \CR_rc_sel$69 2'00 + connect \CR_rc_sel$70 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec58" +module \CR_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec62" +module \CR_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec" +module \dec$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \CR_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \CR_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \CR_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 8 \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 9 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 10 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 11 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 12 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 13 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 14 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 15 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 16 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 18 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_dec19_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_dec19_CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec19_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec19_CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_dec19_CR_rc_sel + cell \CR_dec19 \CR_dec19 + connect \opcode_in \CR_dec19_opcode_in + connect \CR_function_unit \CR_dec19_CR_function_unit + connect \CR_internal_op \CR_dec19_CR_internal_op + connect \CR_cr_in \CR_dec19_CR_cr_in + connect \CR_cr_out \CR_dec19_CR_cr_out + connect \CR_rc_sel \CR_dec19_CR_rc_sel + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec30_opcode_in + cell \CR_dec30 \CR_dec30 + connect \opcode_in \CR_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_dec31_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_dec31_CR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec31_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_dec31_CR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_dec31_CR_rc_sel + cell \CR_dec31 \CR_dec31 + connect \opcode_in \CR_dec31_opcode_in + connect \CR_function_unit \CR_dec31_CR_function_unit + connect \CR_internal_op \CR_dec31_CR_internal_op + connect \CR_cr_in \CR_dec31_CR_cr_in + connect \CR_cr_out \CR_dec31_CR_cr_out + connect \CR_rc_sel \CR_dec31_CR_rc_sel + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec58_opcode_in + cell \CR_dec58 \CR_dec58 + connect \opcode_in \CR_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \CR_dec62_opcode_in + cell \CR_dec62 \CR_dec62 + connect \opcode_in \CR_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \CR_dec19_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \CR_dec30_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \CR_dec31_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \CR_dec58_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \CR_dec62_opcode_in 32'00000000000000000000000000000000 + assign \CR_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \CR_function_unit$3 + process $group_6 + assign \CR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \CR_function_unit \CR_dec19_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \CR_function_unit \CR_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \CR_function_unit \CR_dec31_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \CR_function_unit \CR_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \CR_function_unit \CR_function_unit$3 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \CR_internal_op$6 + process $group_7 + assign \CR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \CR_internal_op \CR_dec19_CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \CR_internal_op \CR_internal_op$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \CR_internal_op \CR_dec31_CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \CR_internal_op \CR_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \CR_internal_op \CR_internal_op$6 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$7 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$8 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_in$9 + process $group_8 + assign \CR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \CR_cr_in \CR_dec19_CR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \CR_cr_in \CR_cr_in$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \CR_cr_in \CR_dec31_CR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \CR_cr_in \CR_cr_in$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \CR_cr_in \CR_cr_in$9 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$10 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$11 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \CR_cr_out$12 + process $group_9 + assign \CR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \CR_cr_out \CR_dec19_CR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \CR_cr_out \CR_cr_out$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \CR_cr_out \CR_dec31_CR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \CR_cr_out \CR_cr_out$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \CR_cr_out \CR_cr_out$12 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$13 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$14 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \CR_rc_sel$15 + process $group_10 + assign \CR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \CR_rc_sel \CR_dec19_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \CR_rc_sel \CR_rc_sel$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \CR_rc_sel \CR_dec31_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \CR_rc_sel \CR_rc_sel$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \CR_rc_sel \CR_rc_sel$15 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$16 + process $group_11 + assign \opcode_switch$16 32'00000000000000000000000000000000 + assign \opcode_switch$16 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $18 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $17 + end + process $group_12 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $17 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_RS + process $group_13 + assign \CR_RS 5'00000 + assign \CR_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_RT + process $group_14 + assign \CR_RT 5'00000 + assign \CR_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_RA + process $group_15 + assign \CR_RA 5'00000 + assign \CR_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_RB + process $group_16 + assign \CR_RB 5'00000 + assign \CR_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \CR_SI + process $group_17 + assign \CR_SI 16'0000000000000000 + assign \CR_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \CR_UI + process $group_18 + assign \CR_UI 16'0000000000000000 + assign \CR_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \CR_L + process $group_19 + assign \CR_L 1'0 + assign \CR_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_SH32 + process $group_20 + assign \CR_SH32 5'00000 + assign \CR_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \CR_sh + process $group_21 + assign \CR_sh 6'000000 + assign \CR_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_MB32 + process $group_22 + assign \CR_MB32 5'00000 + assign \CR_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_ME32 + process $group_23 + assign \CR_ME32 5'00000 + assign \CR_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \CR_LI + process $group_24 + assign \CR_LI 24'000000000000000000000000 + assign \CR_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \CR_LK + process $group_25 + assign \CR_LK 1'0 + assign \CR_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \CR_AA + process $group_26 + assign \CR_AA 1'0 + assign \CR_AA { \opcode_in [1] } + sync init + end + process $group_27 + assign \CR_Rc 1'0 + assign \CR_Rc { \opcode_in [0] } + sync init + end + process $group_28 + assign \CR_OE 1'0 + assign \CR_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \CR_BD + process $group_29 + assign \CR_BD 14'00000000000000 + assign \CR_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \CR_BF + process $group_30 + assign \CR_BF 3'000 + assign \CR_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \CR_CR + process $group_31 + assign \CR_CR 10'0000000000 + assign \CR_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_32 + assign \CR_BB 5'00000 + assign \CR_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_33 + assign \CR_BA 5'00000 + assign \CR_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_34 + assign \CR_BT 5'00000 + assign \CR_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_35 + assign \CR_FXM 8'00000000 + assign \CR_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_BO + process $group_36 + assign \CR_BO 5'00000 + assign \CR_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_37 + assign \CR_BI 5'00000 + assign \CR_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \CR_BH + process $group_38 + assign \CR_BH 2'00 + assign \CR_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \CR_D + process $group_39 + assign \CR_D 16'0000000000000000 + assign \CR_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \CR_DS + process $group_40 + assign \CR_DS 14'00000000000000 + assign \CR_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_TO + process $group_41 + assign \CR_TO 5'00000 + assign \CR_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_42 + assign \CR_BC 5'00000 + assign \CR_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_SH + process $group_43 + assign \CR_SH 5'00000 + assign \CR_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_ME + process $group_44 + assign \CR_ME 5'00000 + assign \CR_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \CR_MB + process $group_45 + assign \CR_MB 5'00000 + assign \CR_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \CR_SPR + process $group_46 + assign \CR_SPR 10'0000000000 + assign \CR_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_47 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_48 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_49 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_50 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_51 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_52 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_53 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_54 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_55 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_56 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_57 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_58 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_59 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_60 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_61 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_62 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_63 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_64 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_65 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_66 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_67 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_68 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_69 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_70 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_71 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_72 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_73 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_74 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_75 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_76 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_77 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_78 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_79 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_80 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_81 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_82 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_83 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_84 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_85 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_86 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_87 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_88 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_89 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_90 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_91 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_92 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_93 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_94 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_95 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_96 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_97 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_98 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_99 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_100 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_101 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_102 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_103 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_104 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_105 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_106 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_107 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_108 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_109 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_110 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_111 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_112 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_113 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_114 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_115 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_116 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_117 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_118 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_119 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_120 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_121 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_122 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_123 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_124 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_125 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_126 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_127 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_128 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_129 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_130 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_131 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_132 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_133 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_134 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_135 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_136 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_137 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_138 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_139 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_140 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_141 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_142 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_143 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_144 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_145 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_146 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_147 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_148 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_149 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_150 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_151 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_152 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_153 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_154 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_155 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_156 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_157 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_158 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_159 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_160 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_161 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_162 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_163 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_164 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_165 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_166 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_167 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_168 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_169 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_170 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_171 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_172 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_173 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_174 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_175 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_176 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_177 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_178 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_179 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_180 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_181 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_182 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_183 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_184 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_185 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_186 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_187 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_188 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_189 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_190 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_191 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_192 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_193 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_194 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_195 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_196 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_197 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_198 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_199 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_200 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_201 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_202 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_203 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_204 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_205 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_206 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_207 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_208 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_209 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_210 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_211 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_212 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_213 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_214 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_215 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_216 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_217 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_218 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_219 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_220 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_221 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_222 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_223 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_224 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_225 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_226 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_227 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_228 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_229 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_230 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_231 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_232 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_233 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_234 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_235 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_236 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_237 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_238 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_239 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_240 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_241 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_242 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_243 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_244 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_245 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_246 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_247 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_248 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_249 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_250 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_251 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_252 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_253 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_254 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_255 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_256 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_257 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_258 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_259 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_260 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_261 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_262 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_263 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_264 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_265 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_266 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_267 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_268 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_269 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_270 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_271 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_272 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_273 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_274 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_275 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_276 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_277 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_278 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_279 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_280 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_281 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_282 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_283 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_284 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_285 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_286 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_287 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_288 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_289 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_290 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_291 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_292 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_293 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_294 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_295 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_296 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_297 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_298 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_299 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_300 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_301 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_302 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_303 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_304 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_305 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_306 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_307 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_308 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_309 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_310 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_311 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_312 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_313 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_314 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_315 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_316 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_317 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_318 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_319 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_320 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_321 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_322 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_323 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_324 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_325 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_326 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_327 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_328 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_329 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_330 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_331 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_332 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_333 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_334 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_335 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_336 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_337 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_338 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \CR_function_unit$1 11'00000000000 + connect \CR_function_unit$2 11'00000000000 + connect \CR_function_unit$3 11'00000000000 + connect \CR_internal_op$4 7'0000000 + connect \CR_internal_op$5 7'0000000 + connect \CR_internal_op$6 7'0000000 + connect \CR_cr_in$7 3'000 + connect \CR_cr_in$8 3'000 + connect \CR_cr_in$9 3'000 + connect \CR_cr_out$10 3'000 + connect \CR_cr_out$11 3'000 + connect \CR_cr_out$12 3'000 + connect \CR_rc_sel$13 2'00 + connect \CR_rc_sel$14 2'00 + connect \CR_rc_sel$15 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_rc" +module \dec_rc$138 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 2 \CR_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rc_ok + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_oe" +module \dec_oe$139 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 2 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \CR_OE + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe_ok + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in.ppick" +module \ppick$141 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in" +module \dec_cr_in$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$141 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \CR_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \CR_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \CR_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \CR_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \CR_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out.ppick" +module \ppick$143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out" +module \dec_cr_out$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 4 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$143 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \CR_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_CR" +module \dec_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \CR_CR__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \CR_CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \CR_CR__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_CR_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_CR_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_CR_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_CR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$137 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \CR_rc_sel \dec_CR_rc_sel + connect \CR_cr_in \dec_CR_cr_in + connect \CR_cr_out \dec_CR_cr_out + connect \CR_internal_op \dec_CR_internal_op + connect \CR_function_unit \dec_CR_function_unit + connect \CR_Rc \dec_CR_Rc + connect \CR_OE \dec_CR_OE + connect \CR_BB \dec_CR_BB + connect \CR_BA \dec_CR_BA + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_BI \dec_CR_BI + connect \CR_BC \dec_CR_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + cell \dec_rc$138 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \CR_Rc \dec_CR_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + cell \dec_oe$139 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \CR_internal_op \dec_CR_internal_op + connect \CR_OE \dec_CR_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$140 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \CR_internal_op \dec_CR_internal_op + connect \CR_BB \dec_CR_BB + connect \CR_BA \dec_CR_BA + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_BI \dec_CR_BI + connect \CR_BC \dec_CR_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + cell \dec_cr_out$142 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \CR_internal_op \dec_CR_internal_op + connect \CR_FXM \dec_CR_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + process $group_0 + assign \CR_CR__insn 32'00000000000000000000000000000000 + assign \CR_CR__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_CR_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_CR_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_CR_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_CR_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \CR_CR__insn_type 7'0000000 + assign \CR_CR__insn_type \dec_CR_internal_op + sync init + end + process $group_11 + assign \CR_CR__fn_unit 11'00000000000 + assign \CR_CR__fn_unit \dec_CR_function_unit + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec19" +module \BRANCH_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \BRANCH_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \BRANCH_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \BRANCH_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 7 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + process $group_1 + assign \BRANCH_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_function_unit 11'00000100000 + end + sync init + end + process $group_2 + assign \BRANCH_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_internal_op 7'0001000 + end + sync init + end + process $group_3 + assign \BRANCH_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_in2_sel 4'1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_in2_sel 4'1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_in2_sel 4'1100 + end + sync init + end + process $group_4 + assign \BRANCH_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_cr_in 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_cr_in 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_cr_in 3'010 + end + sync init + end + process $group_5 + assign \BRANCH_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_cr_out 3'000 + end + sync init + end + process $group_6 + assign \BRANCH_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_rc_sel 2'00 + end + sync init + end + process $group_7 + assign \BRANCH_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_is_32b 1'0 + end + sync init + end + process $group_8 + assign \BRANCH_lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000010000 + assign \BRANCH_lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'0000010000 + assign \BRANCH_lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 10'1000110000 + assign \BRANCH_lk 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_9 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec30" +module \BRANCH_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub10" +module \BRANCH_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub28" +module \BRANCH_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub0" +module \BRANCH_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub26" +module \BRANCH_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub19" +module \BRANCH_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub22" +module \BRANCH_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub9" +module \BRANCH_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub11" +module \BRANCH_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub27" +module \BRANCH_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub15" +module \BRANCH_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub20" +module \BRANCH_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub21" +module \BRANCH_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub23" +module \BRANCH_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub16" +module \BRANCH_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub18" +module \BRANCH_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub8" +module \BRANCH_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub24" +module \BRANCH_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31.BRANCH_dec_sub4" +module \BRANCH_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec31" +module \BRANCH_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \BRANCH_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \BRANCH_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \BRANCH_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 7 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub10_opcode_in + cell \BRANCH_dec_sub10 \BRANCH_dec_sub10 + connect \opcode_in \BRANCH_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub28_opcode_in + cell \BRANCH_dec_sub28 \BRANCH_dec_sub28 + connect \opcode_in \BRANCH_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub0_opcode_in + cell \BRANCH_dec_sub0 \BRANCH_dec_sub0 + connect \opcode_in \BRANCH_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub26_opcode_in + cell \BRANCH_dec_sub26 \BRANCH_dec_sub26 + connect \opcode_in \BRANCH_dec_sub26_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub19_opcode_in + cell \BRANCH_dec_sub19 \BRANCH_dec_sub19 + connect \opcode_in \BRANCH_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub22_opcode_in + cell \BRANCH_dec_sub22 \BRANCH_dec_sub22 + connect \opcode_in \BRANCH_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub9_opcode_in + cell \BRANCH_dec_sub9 \BRANCH_dec_sub9 + connect \opcode_in \BRANCH_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub11_opcode_in + cell \BRANCH_dec_sub11 \BRANCH_dec_sub11 + connect \opcode_in \BRANCH_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub27_opcode_in + cell \BRANCH_dec_sub27 \BRANCH_dec_sub27 + connect \opcode_in \BRANCH_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub15_opcode_in + cell \BRANCH_dec_sub15 \BRANCH_dec_sub15 + connect \opcode_in \BRANCH_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub20_opcode_in + cell \BRANCH_dec_sub20 \BRANCH_dec_sub20 + connect \opcode_in \BRANCH_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub21_opcode_in + cell \BRANCH_dec_sub21 \BRANCH_dec_sub21 + connect \opcode_in \BRANCH_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub23_opcode_in + cell \BRANCH_dec_sub23 \BRANCH_dec_sub23 + connect \opcode_in \BRANCH_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub16_opcode_in + cell \BRANCH_dec_sub16 \BRANCH_dec_sub16 + connect \opcode_in \BRANCH_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub18_opcode_in + cell \BRANCH_dec_sub18 \BRANCH_dec_sub18 + connect \opcode_in \BRANCH_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub8_opcode_in + cell \BRANCH_dec_sub8 \BRANCH_dec_sub8 + connect \opcode_in \BRANCH_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub24_opcode_in + cell \BRANCH_dec_sub24 \BRANCH_dec_sub24 + connect \opcode_in \BRANCH_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec_sub4_opcode_in + cell \BRANCH_dec_sub4 \BRANCH_dec_sub4 + connect \opcode_in \BRANCH_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \BRANCH_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \BRANCH_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \BRANCH_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \BRANCH_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \BRANCH_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \BRANCH_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \BRANCH_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \BRANCH_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \BRANCH_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \BRANCH_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \BRANCH_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \BRANCH_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \BRANCH_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \BRANCH_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \BRANCH_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \BRANCH_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \BRANCH_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \BRANCH_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$14 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$16 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$17 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$18 + process $group_20 + assign \BRANCH_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_function_unit \BRANCH_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_function_unit \BRANCH_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_function_unit \BRANCH_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_function_unit \BRANCH_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_function_unit \BRANCH_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_function_unit \BRANCH_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_function_unit \BRANCH_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_function_unit \BRANCH_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_function_unit \BRANCH_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_function_unit \BRANCH_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_function_unit \BRANCH_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_function_unit \BRANCH_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_function_unit \BRANCH_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_function_unit \BRANCH_function_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_function_unit \BRANCH_function_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_function_unit \BRANCH_function_unit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_function_unit \BRANCH_function_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_function_unit \BRANCH_function_unit$18 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$31 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$32 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$33 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$35 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$36 + process $group_21 + assign \BRANCH_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_internal_op \BRANCH_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_internal_op \BRANCH_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_internal_op \BRANCH_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_internal_op \BRANCH_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_internal_op \BRANCH_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_internal_op \BRANCH_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_internal_op \BRANCH_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_internal_op \BRANCH_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_internal_op \BRANCH_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_internal_op \BRANCH_internal_op$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_internal_op \BRANCH_internal_op$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_internal_op \BRANCH_internal_op$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_internal_op \BRANCH_internal_op$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_internal_op \BRANCH_internal_op$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_internal_op \BRANCH_internal_op$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_internal_op \BRANCH_internal_op$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_internal_op \BRANCH_internal_op$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_internal_op \BRANCH_internal_op$36 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$37 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$38 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$39 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$40 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$41 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$42 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$43 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$44 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$45 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$46 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$47 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$48 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$49 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$50 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$51 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$52 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$53 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$54 + process $group_22 + assign \BRANCH_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_in2_sel \BRANCH_in2_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_in2_sel \BRANCH_in2_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_in2_sel \BRANCH_in2_sel$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_in2_sel \BRANCH_in2_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_in2_sel \BRANCH_in2_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_in2_sel \BRANCH_in2_sel$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_in2_sel \BRANCH_in2_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_in2_sel \BRANCH_in2_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_in2_sel \BRANCH_in2_sel$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_in2_sel \BRANCH_in2_sel$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_in2_sel \BRANCH_in2_sel$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_in2_sel \BRANCH_in2_sel$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_in2_sel \BRANCH_in2_sel$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_in2_sel \BRANCH_in2_sel$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_in2_sel \BRANCH_in2_sel$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_in2_sel \BRANCH_in2_sel$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_in2_sel \BRANCH_in2_sel$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_in2_sel \BRANCH_in2_sel$54 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$55 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$56 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$57 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$58 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$59 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$60 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$61 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$62 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$63 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$64 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$65 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$66 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$67 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$68 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$69 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$70 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$71 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$72 + process $group_23 + assign \BRANCH_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_cr_in \BRANCH_cr_in$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_cr_in \BRANCH_cr_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_cr_in \BRANCH_cr_in$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_cr_in \BRANCH_cr_in$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_cr_in \BRANCH_cr_in$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_cr_in \BRANCH_cr_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_cr_in \BRANCH_cr_in$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_cr_in \BRANCH_cr_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_cr_in \BRANCH_cr_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_cr_in \BRANCH_cr_in$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_cr_in \BRANCH_cr_in$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_cr_in \BRANCH_cr_in$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_cr_in \BRANCH_cr_in$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_cr_in \BRANCH_cr_in$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_cr_in \BRANCH_cr_in$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_cr_in \BRANCH_cr_in$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_cr_in \BRANCH_cr_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_cr_in \BRANCH_cr_in$72 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$73 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$74 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$75 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$76 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$77 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$78 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$79 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$80 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$81 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$82 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$83 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$84 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$85 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$86 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$87 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$88 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$89 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$90 + process $group_24 + assign \BRANCH_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_cr_out \BRANCH_cr_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_cr_out \BRANCH_cr_out$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_cr_out \BRANCH_cr_out$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_cr_out \BRANCH_cr_out$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_cr_out \BRANCH_cr_out$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_cr_out \BRANCH_cr_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_cr_out \BRANCH_cr_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_cr_out \BRANCH_cr_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_cr_out \BRANCH_cr_out$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_cr_out \BRANCH_cr_out$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_cr_out \BRANCH_cr_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_cr_out \BRANCH_cr_out$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_cr_out \BRANCH_cr_out$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_cr_out \BRANCH_cr_out$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_cr_out \BRANCH_cr_out$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_cr_out \BRANCH_cr_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_cr_out \BRANCH_cr_out$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_cr_out \BRANCH_cr_out$90 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$91 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$92 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$93 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$94 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$95 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$96 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$97 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$98 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$99 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$100 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$101 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$102 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$103 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$104 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$105 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$106 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$107 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$108 + process $group_25 + assign \BRANCH_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_rc_sel \BRANCH_rc_sel$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_rc_sel \BRANCH_rc_sel$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_rc_sel \BRANCH_rc_sel$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_rc_sel \BRANCH_rc_sel$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_rc_sel \BRANCH_rc_sel$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_rc_sel \BRANCH_rc_sel$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_rc_sel \BRANCH_rc_sel$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_rc_sel \BRANCH_rc_sel$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_rc_sel \BRANCH_rc_sel$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_rc_sel \BRANCH_rc_sel$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_rc_sel \BRANCH_rc_sel$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_rc_sel \BRANCH_rc_sel$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_rc_sel \BRANCH_rc_sel$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_rc_sel \BRANCH_rc_sel$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_rc_sel \BRANCH_rc_sel$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_rc_sel \BRANCH_rc_sel$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_rc_sel \BRANCH_rc_sel$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_rc_sel \BRANCH_rc_sel$108 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$126 + process $group_26 + assign \BRANCH_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_is_32b \BRANCH_is_32b$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_is_32b \BRANCH_is_32b$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_is_32b \BRANCH_is_32b$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_is_32b \BRANCH_is_32b$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_is_32b \BRANCH_is_32b$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_is_32b \BRANCH_is_32b$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_is_32b \BRANCH_is_32b$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_is_32b \BRANCH_is_32b$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_is_32b \BRANCH_is_32b$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_is_32b \BRANCH_is_32b$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_is_32b \BRANCH_is_32b$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_is_32b \BRANCH_is_32b$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_is_32b \BRANCH_is_32b$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_is_32b \BRANCH_is_32b$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_is_32b \BRANCH_is_32b$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_is_32b \BRANCH_is_32b$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_is_32b \BRANCH_is_32b$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_is_32b \BRANCH_is_32b$126 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$144 + process $group_27 + assign \BRANCH_lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \BRANCH_lk \BRANCH_lk$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \BRANCH_lk \BRANCH_lk$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \BRANCH_lk \BRANCH_lk$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \BRANCH_lk \BRANCH_lk$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \BRANCH_lk \BRANCH_lk$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \BRANCH_lk \BRANCH_lk$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \BRANCH_lk \BRANCH_lk$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \BRANCH_lk \BRANCH_lk$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \BRANCH_lk \BRANCH_lk$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \BRANCH_lk \BRANCH_lk$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \BRANCH_lk \BRANCH_lk$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \BRANCH_lk \BRANCH_lk$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \BRANCH_lk \BRANCH_lk$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \BRANCH_lk \BRANCH_lk$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \BRANCH_lk \BRANCH_lk$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \BRANCH_lk \BRANCH_lk$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \BRANCH_lk \BRANCH_lk$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \BRANCH_lk \BRANCH_lk$144 + end + sync init + end + connect \BRANCH_function_unit$1 11'00000000000 + connect \BRANCH_function_unit$2 11'00000000000 + connect \BRANCH_function_unit$3 11'00000000000 + connect \BRANCH_function_unit$4 11'00000000000 + connect \BRANCH_function_unit$5 11'00000000000 + connect \BRANCH_function_unit$6 11'00000000000 + connect \BRANCH_function_unit$7 11'00000000000 + connect \BRANCH_function_unit$8 11'00000000000 + connect \BRANCH_function_unit$9 11'00000000000 + connect \BRANCH_function_unit$10 11'00000000000 + connect \BRANCH_function_unit$11 11'00000000000 + connect \BRANCH_function_unit$12 11'00000000000 + connect \BRANCH_function_unit$13 11'00000000000 + connect \BRANCH_function_unit$14 11'00000000000 + connect \BRANCH_function_unit$15 11'00000000000 + connect \BRANCH_function_unit$16 11'00000000000 + connect \BRANCH_function_unit$17 11'00000000000 + connect \BRANCH_function_unit$18 11'00000000000 + connect \BRANCH_internal_op$19 7'0000000 + connect \BRANCH_internal_op$20 7'0000000 + connect \BRANCH_internal_op$21 7'0000000 + connect \BRANCH_internal_op$22 7'0000000 + connect \BRANCH_internal_op$23 7'0000000 + connect \BRANCH_internal_op$24 7'0000000 + connect \BRANCH_internal_op$25 7'0000000 + connect \BRANCH_internal_op$26 7'0000000 + connect \BRANCH_internal_op$27 7'0000000 + connect \BRANCH_internal_op$28 7'0000000 + connect \BRANCH_internal_op$29 7'0000000 + connect \BRANCH_internal_op$30 7'0000000 + connect \BRANCH_internal_op$31 7'0000000 + connect \BRANCH_internal_op$32 7'0000000 + connect \BRANCH_internal_op$33 7'0000000 + connect \BRANCH_internal_op$34 7'0000000 + connect \BRANCH_internal_op$35 7'0000000 + connect \BRANCH_internal_op$36 7'0000000 + connect \BRANCH_in2_sel$37 4'0000 + connect \BRANCH_in2_sel$38 4'0000 + connect \BRANCH_in2_sel$39 4'0000 + connect \BRANCH_in2_sel$40 4'0000 + connect \BRANCH_in2_sel$41 4'0000 + connect \BRANCH_in2_sel$42 4'0000 + connect \BRANCH_in2_sel$43 4'0000 + connect \BRANCH_in2_sel$44 4'0000 + connect \BRANCH_in2_sel$45 4'0000 + connect \BRANCH_in2_sel$46 4'0000 + connect \BRANCH_in2_sel$47 4'0000 + connect \BRANCH_in2_sel$48 4'0000 + connect \BRANCH_in2_sel$49 4'0000 + connect \BRANCH_in2_sel$50 4'0000 + connect \BRANCH_in2_sel$51 4'0000 + connect \BRANCH_in2_sel$52 4'0000 + connect \BRANCH_in2_sel$53 4'0000 + connect \BRANCH_in2_sel$54 4'0000 + connect \BRANCH_cr_in$55 3'000 + connect \BRANCH_cr_in$56 3'000 + connect \BRANCH_cr_in$57 3'000 + connect \BRANCH_cr_in$58 3'000 + connect \BRANCH_cr_in$59 3'000 + connect \BRANCH_cr_in$60 3'000 + connect \BRANCH_cr_in$61 3'000 + connect \BRANCH_cr_in$62 3'000 + connect \BRANCH_cr_in$63 3'000 + connect \BRANCH_cr_in$64 3'000 + connect \BRANCH_cr_in$65 3'000 + connect \BRANCH_cr_in$66 3'000 + connect \BRANCH_cr_in$67 3'000 + connect \BRANCH_cr_in$68 3'000 + connect \BRANCH_cr_in$69 3'000 + connect \BRANCH_cr_in$70 3'000 + connect \BRANCH_cr_in$71 3'000 + connect \BRANCH_cr_in$72 3'000 + connect \BRANCH_cr_out$73 3'000 + connect \BRANCH_cr_out$74 3'000 + connect \BRANCH_cr_out$75 3'000 + connect \BRANCH_cr_out$76 3'000 + connect \BRANCH_cr_out$77 3'000 + connect \BRANCH_cr_out$78 3'000 + connect \BRANCH_cr_out$79 3'000 + connect \BRANCH_cr_out$80 3'000 + connect \BRANCH_cr_out$81 3'000 + connect \BRANCH_cr_out$82 3'000 + connect \BRANCH_cr_out$83 3'000 + connect \BRANCH_cr_out$84 3'000 + connect \BRANCH_cr_out$85 3'000 + connect \BRANCH_cr_out$86 3'000 + connect \BRANCH_cr_out$87 3'000 + connect \BRANCH_cr_out$88 3'000 + connect \BRANCH_cr_out$89 3'000 + connect \BRANCH_cr_out$90 3'000 + connect \BRANCH_rc_sel$91 2'00 + connect \BRANCH_rc_sel$92 2'00 + connect \BRANCH_rc_sel$93 2'00 + connect \BRANCH_rc_sel$94 2'00 + connect \BRANCH_rc_sel$95 2'00 + connect \BRANCH_rc_sel$96 2'00 + connect \BRANCH_rc_sel$97 2'00 + connect \BRANCH_rc_sel$98 2'00 + connect \BRANCH_rc_sel$99 2'00 + connect \BRANCH_rc_sel$100 2'00 + connect \BRANCH_rc_sel$101 2'00 + connect \BRANCH_rc_sel$102 2'00 + connect \BRANCH_rc_sel$103 2'00 + connect \BRANCH_rc_sel$104 2'00 + connect \BRANCH_rc_sel$105 2'00 + connect \BRANCH_rc_sel$106 2'00 + connect \BRANCH_rc_sel$107 2'00 + connect \BRANCH_rc_sel$108 2'00 + connect \BRANCH_is_32b$109 1'0 + connect \BRANCH_is_32b$110 1'0 + connect \BRANCH_is_32b$111 1'0 + connect \BRANCH_is_32b$112 1'0 + connect \BRANCH_is_32b$113 1'0 + connect \BRANCH_is_32b$114 1'0 + connect \BRANCH_is_32b$115 1'0 + connect \BRANCH_is_32b$116 1'0 + connect \BRANCH_is_32b$117 1'0 + connect \BRANCH_is_32b$118 1'0 + connect \BRANCH_is_32b$119 1'0 + connect \BRANCH_is_32b$120 1'0 + connect \BRANCH_is_32b$121 1'0 + connect \BRANCH_is_32b$122 1'0 + connect \BRANCH_is_32b$123 1'0 + connect \BRANCH_is_32b$124 1'0 + connect \BRANCH_is_32b$125 1'0 + connect \BRANCH_is_32b$126 1'0 + connect \BRANCH_lk$127 1'0 + connect \BRANCH_lk$128 1'0 + connect \BRANCH_lk$129 1'0 + connect \BRANCH_lk$130 1'0 + connect \BRANCH_lk$131 1'0 + connect \BRANCH_lk$132 1'0 + connect \BRANCH_lk$133 1'0 + connect \BRANCH_lk$134 1'0 + connect \BRANCH_lk$135 1'0 + connect \BRANCH_lk$136 1'0 + connect \BRANCH_lk$137 1'0 + connect \BRANCH_lk$138 1'0 + connect \BRANCH_lk$139 1'0 + connect \BRANCH_lk$140 1'0 + connect \BRANCH_lk$141 1'0 + connect \BRANCH_lk$142 1'0 + connect \BRANCH_lk$143 1'0 + connect \BRANCH_lk$144 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec58" +module \BRANCH_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec62" +module \BRANCH_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec" +module \dec$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \BRANCH_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \BRANCH_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 8 \BRANCH_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 11 \BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 12 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 13 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 14 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 15 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 16 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 17 \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 18 \BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 19 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 20 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 21 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 22 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 23 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 24 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 25 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 26 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 27 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 28 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 29 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_dec19_BRANCH_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_dec19_BRANCH_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_dec19_BRANCH_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_dec19_BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_dec19_BRANCH_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_dec19_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_dec19_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_dec19_BRANCH_lk + cell \BRANCH_dec19 \BRANCH_dec19 + connect \opcode_in \BRANCH_dec19_opcode_in + connect \BRANCH_function_unit \BRANCH_dec19_BRANCH_function_unit + connect \BRANCH_internal_op \BRANCH_dec19_BRANCH_internal_op + connect \BRANCH_in2_sel \BRANCH_dec19_BRANCH_in2_sel + connect \BRANCH_cr_in \BRANCH_dec19_BRANCH_cr_in + connect \BRANCH_cr_out \BRANCH_dec19_BRANCH_cr_out + connect \BRANCH_rc_sel \BRANCH_dec19_BRANCH_rc_sel + connect \BRANCH_is_32b \BRANCH_dec19_BRANCH_is_32b + connect \BRANCH_lk \BRANCH_dec19_BRANCH_lk + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec30_opcode_in + cell \BRANCH_dec30 \BRANCH_dec30 + connect \opcode_in \BRANCH_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_dec31_BRANCH_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_dec31_BRANCH_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_dec31_BRANCH_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_dec31_BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_dec31_BRANCH_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_dec31_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_dec31_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_dec31_BRANCH_lk + cell \BRANCH_dec31 \BRANCH_dec31 + connect \opcode_in \BRANCH_dec31_opcode_in + connect \BRANCH_function_unit \BRANCH_dec31_BRANCH_function_unit + connect \BRANCH_internal_op \BRANCH_dec31_BRANCH_internal_op + connect \BRANCH_in2_sel \BRANCH_dec31_BRANCH_in2_sel + connect \BRANCH_cr_in \BRANCH_dec31_BRANCH_cr_in + connect \BRANCH_cr_out \BRANCH_dec31_BRANCH_cr_out + connect \BRANCH_rc_sel \BRANCH_dec31_BRANCH_rc_sel + connect \BRANCH_is_32b \BRANCH_dec31_BRANCH_is_32b + connect \BRANCH_lk \BRANCH_dec31_BRANCH_lk + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec58_opcode_in + cell \BRANCH_dec58 \BRANCH_dec58 + connect \opcode_in \BRANCH_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \BRANCH_dec62_opcode_in + cell \BRANCH_dec62 \BRANCH_dec62 + connect \opcode_in \BRANCH_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \BRANCH_dec19_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \BRANCH_dec30_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \BRANCH_dec31_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \BRANCH_dec58_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \BRANCH_dec62_opcode_in 32'00000000000000000000000000000000 + assign \BRANCH_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \BRANCH_function_unit$3 + process $group_6 + assign \BRANCH_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_function_unit \BRANCH_dec19_BRANCH_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_function_unit \BRANCH_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_function_unit \BRANCH_dec31_BRANCH_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_function_unit \BRANCH_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_function_unit \BRANCH_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_function_unit 11'00000100000 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \BRANCH_internal_op$6 + process $group_7 + assign \BRANCH_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_internal_op \BRANCH_dec19_BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_internal_op \BRANCH_internal_op$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_internal_op \BRANCH_dec31_BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_internal_op \BRANCH_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_internal_op \BRANCH_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_internal_op 7'0000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_internal_op 7'0000111 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$7 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$8 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \BRANCH_in2_sel$9 + process $group_8 + assign \BRANCH_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_in2_sel \BRANCH_dec19_BRANCH_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_in2_sel \BRANCH_in2_sel$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_in2_sel \BRANCH_dec31_BRANCH_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_in2_sel \BRANCH_in2_sel$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_in2_sel \BRANCH_in2_sel$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_in2_sel 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_in2_sel 4'0111 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$10 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$11 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_in$12 + process $group_9 + assign \BRANCH_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_cr_in \BRANCH_dec19_BRANCH_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_cr_in \BRANCH_cr_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_cr_in \BRANCH_dec31_BRANCH_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_cr_in \BRANCH_cr_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_cr_in \BRANCH_cr_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_cr_in 3'010 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$13 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$14 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \BRANCH_cr_out$15 + process $group_10 + assign \BRANCH_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_cr_out \BRANCH_dec19_BRANCH_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_cr_out \BRANCH_cr_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_cr_out \BRANCH_dec31_BRANCH_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_cr_out \BRANCH_cr_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_cr_out \BRANCH_cr_out$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_cr_out 3'000 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$16 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$17 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \BRANCH_rc_sel$18 + process $group_11 + assign \BRANCH_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_rc_sel \BRANCH_dec19_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_rc_sel \BRANCH_rc_sel$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_rc_sel \BRANCH_dec31_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_rc_sel \BRANCH_rc_sel$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_rc_sel \BRANCH_rc_sel$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_rc_sel 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_is_32b$21 + process $group_12 + assign \BRANCH_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_is_32b \BRANCH_dec19_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_is_32b \BRANCH_is_32b$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_is_32b \BRANCH_dec31_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_is_32b \BRANCH_is_32b$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_is_32b \BRANCH_is_32b$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_is_32b 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \BRANCH_lk$24 + process $group_13 + assign \BRANCH_lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \BRANCH_lk \BRANCH_dec19_BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \BRANCH_lk \BRANCH_lk$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \BRANCH_lk \BRANCH_dec31_BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \BRANCH_lk \BRANCH_lk$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \BRANCH_lk \BRANCH_lk$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \BRANCH_lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \BRANCH_lk 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$25 + process $group_14 + assign \opcode_switch$25 32'00000000000000000000000000000000 + assign \opcode_switch$25 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $27 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $26 + end + process $group_15 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $26 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_RS + process $group_16 + assign \BRANCH_RS 5'00000 + assign \BRANCH_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_RT + process $group_17 + assign \BRANCH_RT 5'00000 + assign \BRANCH_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_RA + process $group_18 + assign \BRANCH_RA 5'00000 + assign \BRANCH_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_RB + process $group_19 + assign \BRANCH_RB 5'00000 + assign \BRANCH_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_20 + assign \BRANCH_SI 16'0000000000000000 + assign \BRANCH_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_21 + assign \BRANCH_UI 16'0000000000000000 + assign \BRANCH_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \BRANCH_L + process $group_22 + assign \BRANCH_L 1'0 + assign \BRANCH_L { \opcode_in [21] } + sync init + end + process $group_23 + assign \BRANCH_SH32 5'00000 + assign \BRANCH_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_24 + assign \BRANCH_sh 6'000000 + assign \BRANCH_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_MB32 + process $group_25 + assign \BRANCH_MB32 5'00000 + assign \BRANCH_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_ME32 + process $group_26 + assign \BRANCH_ME32 5'00000 + assign \BRANCH_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_27 + assign \BRANCH_LI 24'000000000000000000000000 + assign \BRANCH_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + process $group_28 + assign \BRANCH_LK 1'0 + assign \BRANCH_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \BRANCH_AA + process $group_29 + assign \BRANCH_AA 1'0 + assign \BRANCH_AA { \opcode_in [1] } + sync init + end + process $group_30 + assign \BRANCH_Rc 1'0 + assign \BRANCH_Rc { \opcode_in [0] } + sync init + end + process $group_31 + assign \BRANCH_OE 1'0 + assign \BRANCH_OE { \opcode_in [10] } + sync init + end + process $group_32 + assign \BRANCH_BD 14'00000000000000 + assign \BRANCH_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \BRANCH_BF + process $group_33 + assign \BRANCH_BF 3'000 + assign \BRANCH_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \BRANCH_CR + process $group_34 + assign \BRANCH_CR 10'0000000000 + assign \BRANCH_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_35 + assign \BRANCH_BB 5'00000 + assign \BRANCH_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_36 + assign \BRANCH_BA 5'00000 + assign \BRANCH_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_37 + assign \BRANCH_BT 5'00000 + assign \BRANCH_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_38 + assign \BRANCH_FXM 8'00000000 + assign \BRANCH_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_BO + process $group_39 + assign \BRANCH_BO 5'00000 + assign \BRANCH_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_40 + assign \BRANCH_BI 5'00000 + assign \BRANCH_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \BRANCH_BH + process $group_41 + assign \BRANCH_BH 2'00 + assign \BRANCH_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \BRANCH_D + process $group_42 + assign \BRANCH_D 16'0000000000000000 + assign \BRANCH_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_43 + assign \BRANCH_DS 14'00000000000000 + assign \BRANCH_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_TO + process $group_44 + assign \BRANCH_TO 5'00000 + assign \BRANCH_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_45 + assign \BRANCH_BC 5'00000 + assign \BRANCH_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_SH + process $group_46 + assign \BRANCH_SH 5'00000 + assign \BRANCH_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_ME + process $group_47 + assign \BRANCH_ME 5'00000 + assign \BRANCH_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \BRANCH_MB + process $group_48 + assign \BRANCH_MB 5'00000 + assign \BRANCH_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \BRANCH_SPR + process $group_49 + assign \BRANCH_SPR 10'0000000000 + assign \BRANCH_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_50 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_51 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_52 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_53 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_54 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_55 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_56 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_57 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_58 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_59 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_60 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_61 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_62 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_63 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_64 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_65 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_66 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_67 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_68 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_69 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_70 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_71 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_72 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_73 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_74 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_75 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_76 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_77 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_78 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_79 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_80 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_81 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_82 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_83 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_84 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_85 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_86 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_87 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_88 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_89 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_90 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_91 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_92 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_93 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_94 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_95 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_96 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_97 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_98 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_99 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_100 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_101 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_102 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_103 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_104 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_105 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_106 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_107 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_108 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_109 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_110 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_111 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_112 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_113 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_114 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_115 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_116 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_117 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_118 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_119 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_120 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_121 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_122 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_123 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_124 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_125 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_126 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_127 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_128 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_129 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_130 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_131 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_132 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_133 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_134 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_135 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_136 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_137 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_138 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_139 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_140 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_141 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_142 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_143 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_144 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_145 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_146 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_147 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_148 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_149 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_150 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_151 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_152 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_153 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_154 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_155 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_156 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_157 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_158 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_159 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_160 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_161 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_162 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_163 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_164 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_165 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_166 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_167 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_168 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_169 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_170 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_171 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_172 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_173 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_174 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_175 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_176 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_177 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_178 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_179 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_180 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_181 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_182 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_183 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_184 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_185 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_186 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_187 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_188 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_189 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_190 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_191 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_192 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_193 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_194 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_195 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_196 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_197 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_198 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_199 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_200 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_201 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_202 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_203 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_204 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_205 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_206 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_207 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_208 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_209 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_210 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_211 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_212 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_213 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_214 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_215 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_216 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_217 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_218 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_219 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_220 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_221 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_222 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_223 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_224 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_225 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_226 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_227 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_228 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_229 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_230 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_231 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_232 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_233 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_234 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_235 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_236 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_237 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_238 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_239 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_240 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_241 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_242 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_243 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_244 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_245 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_246 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_247 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_248 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_249 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_250 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_251 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_252 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_253 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_254 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_255 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_256 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_257 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_258 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_259 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_260 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_261 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_262 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_263 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_264 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_265 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_266 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_267 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_268 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_269 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_270 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_271 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_272 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_273 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_274 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_275 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_276 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_277 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_278 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_279 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_280 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_281 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_282 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_283 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_284 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_285 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_286 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_287 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_288 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_289 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_290 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_291 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_292 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_293 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_294 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_295 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_296 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_297 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_298 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_299 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_300 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_301 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_302 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_303 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_304 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_305 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_306 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_307 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_308 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_309 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_310 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_311 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_312 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_313 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_314 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_315 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_316 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_317 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_318 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_319 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_320 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_321 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_322 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_323 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_324 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_325 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_326 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_327 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_328 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_329 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_330 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_331 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_332 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_333 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_334 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_335 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_336 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_337 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_338 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_339 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_340 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_341 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \BRANCH_function_unit$1 11'00000000000 + connect \BRANCH_function_unit$2 11'00000000000 + connect \BRANCH_function_unit$3 11'00000000000 + connect \BRANCH_internal_op$4 7'0000000 + connect \BRANCH_internal_op$5 7'0000000 + connect \BRANCH_internal_op$6 7'0000000 + connect \BRANCH_in2_sel$7 4'0000 + connect \BRANCH_in2_sel$8 4'0000 + connect \BRANCH_in2_sel$9 4'0000 + connect \BRANCH_cr_in$10 3'000 + connect \BRANCH_cr_in$11 3'000 + connect \BRANCH_cr_in$12 3'000 + connect \BRANCH_cr_out$13 3'000 + connect \BRANCH_cr_out$14 3'000 + connect \BRANCH_cr_out$15 3'000 + connect \BRANCH_rc_sel$16 2'00 + connect \BRANCH_rc_sel$17 2'00 + connect \BRANCH_rc_sel$18 2'00 + connect \BRANCH_is_32b$19 1'0 + connect \BRANCH_is_32b$20 1'0 + connect \BRANCH_is_32b$21 1'0 + connect \BRANCH_lk$22 1'0 + connect \BRANCH_lk$23 1'0 + connect \BRANCH_lk$24 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_rc" +module \dec_rc$145 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 2 \BRANCH_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rc_ok + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_oe" +module \dec_oe$146 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 2 \BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \BRANCH_OE + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe_ok + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in.ppick" +module \ppick$148 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in" +module \dec_cr_in$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$148 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \BRANCH_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \BRANCH_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \BRANCH_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \BRANCH_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \BRANCH_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out.ppick" +module \ppick$150 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out" +module \dec_cr_out$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 4 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$150 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \BRANCH_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_bi" +module \dec_bi$151 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \BRANCH_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH" +module \dec_BRANCH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 0 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 1 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 2 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 3 \BRANCH_BRANCH__cia + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 4 \BRANCH_BRANCH__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 5 \BRANCH_BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 6 \BRANCH_BRANCH__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \BRANCH_BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \BRANCH_BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \BRANCH_BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_BRANCH_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_BRANCH_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_BRANCH_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_BRANCH_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_BRANCH_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$144 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \BRANCH_rc_sel \dec_BRANCH_rc_sel + connect \BRANCH_cr_in \dec_BRANCH_cr_in + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_is_32b \dec_BRANCH_is_32b + connect \BRANCH_lk \dec_BRANCH_lk + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_sh \dec_BRANCH_sh + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_BC \dec_BRANCH_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + cell \dec_rc$145 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \BRANCH_Rc \dec_BRANCH_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + cell \dec_oe$146 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_OE \dec_BRANCH_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$147 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BC \dec_BRANCH_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + cell \dec_cr_out$149 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi$151 \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_sh \dec_BRANCH_sh + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + end + process $group_0 + assign \BRANCH_BRANCH__insn 32'00000000000000000000000000000000 + assign \BRANCH_BRANCH__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_BRANCH_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_BRANCH_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_BRANCH_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_BRANCH_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \BRANCH_BRANCH__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \BRANCH_BRANCH__cia \core_pc + sync init + end + process $group_11 + assign \BRANCH_BRANCH__insn_type 7'0000000 + assign \BRANCH_BRANCH__insn_type \dec_BRANCH_internal_op + sync init + end + process $group_12 + assign \BRANCH_BRANCH__fn_unit 11'00000000000 + assign \BRANCH_BRANCH__fn_unit \dec_BRANCH_function_unit + sync init + end + process $group_13 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_BRANCH_in2_sel + sync init + end + process $group_14 + assign \BRANCH_BRANCH__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \BRANCH_BRANCH__imm_data__ok 1'0 + assign { \BRANCH_BRANCH__imm_data__ok \BRANCH_BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_16 + assign \BRANCH_BRANCH__is_32bit 1'0 + assign \BRANCH_BRANCH__is_32bit \dec_BRANCH_is_32b + sync init + end + process $group_17 + assign \BRANCH_BRANCH__lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" + switch { \dec_BRANCH_lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" + case 1'1 + assign \BRANCH_BRANCH__lk \dec_BRANCH_LK + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec19" +module \LOGICAL_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_1 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec30" +module \LOGICAL_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub10" +module \LOGICAL_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub28" +module \LOGICAL_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LOGICAL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LOGICAL_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LOGICAL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LOGICAL_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LOGICAL_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \LOGICAL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_function_unit 11'00000010000 + end + sync init + end + process $group_2 + assign \LOGICAL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_internal_op 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_internal_op 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_internal_op 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_internal_op 7'1000011 + end + sync init + end + process $group_3 + assign \LOGICAL_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_in1_sel 3'100 + end + sync init + end + process $group_4 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_cr_out 3'001 + end + sync init + end + process $group_7 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_ldst_len 4'0000 + end + sync init + end + process $group_8 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_rc_sel 2'10 + end + sync init + end + process $group_9 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_cry_in 2'00 + end + sync init + end + process $group_10 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_inv_a 1'0 + end + sync init + end + process $group_11 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_inv_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_inv_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_inv_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_inv_out 1'0 + end + sync init + end + process $group_12 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_cry_out 1'0 + end + sync init + end + process $group_13 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_is_32b 1'0 + end + sync init + end + process $group_14 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LOGICAL_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub0" +module \LOGICAL_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub26" +module \LOGICAL_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LOGICAL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LOGICAL_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LOGICAL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LOGICAL_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LOGICAL_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \LOGICAL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_function_unit 11'00000010000 + end + sync init + end + process $group_2 + assign \LOGICAL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_internal_op 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_internal_op 7'0110111 + end + sync init + end + process $group_3 + assign \LOGICAL_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_in1_sel 3'100 + end + sync init + end + process $group_4 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_in2_sel 4'0000 + end + sync init + end + process $group_5 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_ldst_len 4'0100 + end + sync init + end + process $group_8 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_rc_sel 2'00 + end + sync init + end + process $group_9 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_cry_in 2'00 + end + sync init + end + process $group_10 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_inv_a 1'0 + end + sync init + end + process $group_11 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_inv_out 1'0 + end + sync init + end + process $group_12 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_cry_out 1'0 + end + sync init + end + process $group_13 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_is_32b 1'0 + end + sync init + end + process $group_14 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10001 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LOGICAL_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub19" +module \LOGICAL_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub22" +module \LOGICAL_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub9" +module \LOGICAL_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub11" +module \LOGICAL_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub27" +module \LOGICAL_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub15" +module \LOGICAL_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub20" +module \LOGICAL_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub21" +module \LOGICAL_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub23" +module \LOGICAL_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub16" +module \LOGICAL_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub18" +module \LOGICAL_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub8" +module \LOGICAL_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub24" +module \LOGICAL_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub4" +module \LOGICAL_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31" +module \LOGICAL_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LOGICAL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LOGICAL_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LOGICAL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LOGICAL_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LOGICAL_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub10_opcode_in + cell \LOGICAL_dec_sub10 \LOGICAL_dec_sub10 + connect \opcode_in \LOGICAL_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_dec_sub28_LOGICAL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_dec_sub28_LOGICAL_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec_sub28_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_dec_sub28_LOGICAL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec_sub28_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec_sub28_LOGICAL_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_dec_sub28_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_dec_sub28_LOGICAL_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_dec_sub28_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub28_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub28_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub28_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub28_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub28_LOGICAL_sgn + cell \LOGICAL_dec_sub28 \LOGICAL_dec_sub28 + connect \opcode_in \LOGICAL_dec_sub28_opcode_in + connect \LOGICAL_function_unit \LOGICAL_dec_sub28_LOGICAL_function_unit + connect \LOGICAL_internal_op \LOGICAL_dec_sub28_LOGICAL_internal_op + connect \LOGICAL_in1_sel \LOGICAL_dec_sub28_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \LOGICAL_dec_sub28_LOGICAL_in2_sel + connect \LOGICAL_cr_in \LOGICAL_dec_sub28_LOGICAL_cr_in + connect \LOGICAL_cr_out \LOGICAL_dec_sub28_LOGICAL_cr_out + connect \LOGICAL_ldst_len \LOGICAL_dec_sub28_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \LOGICAL_dec_sub28_LOGICAL_rc_sel + connect \LOGICAL_cry_in \LOGICAL_dec_sub28_LOGICAL_cry_in + connect \LOGICAL_inv_a \LOGICAL_dec_sub28_LOGICAL_inv_a + connect \LOGICAL_inv_out \LOGICAL_dec_sub28_LOGICAL_inv_out + connect \LOGICAL_cry_out \LOGICAL_dec_sub28_LOGICAL_cry_out + connect \LOGICAL_is_32b \LOGICAL_dec_sub28_LOGICAL_is_32b + connect \LOGICAL_sgn \LOGICAL_dec_sub28_LOGICAL_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub0_opcode_in + cell \LOGICAL_dec_sub0 \LOGICAL_dec_sub0 + connect \opcode_in \LOGICAL_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub26_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_dec_sub26_LOGICAL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_dec_sub26_LOGICAL_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec_sub26_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_dec_sub26_LOGICAL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec_sub26_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec_sub26_LOGICAL_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_dec_sub26_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_dec_sub26_LOGICAL_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_dec_sub26_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub26_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub26_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub26_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub26_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec_sub26_LOGICAL_sgn + cell \LOGICAL_dec_sub26 \LOGICAL_dec_sub26 + connect \opcode_in \LOGICAL_dec_sub26_opcode_in + connect \LOGICAL_function_unit \LOGICAL_dec_sub26_LOGICAL_function_unit + connect \LOGICAL_internal_op \LOGICAL_dec_sub26_LOGICAL_internal_op + connect \LOGICAL_in1_sel \LOGICAL_dec_sub26_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \LOGICAL_dec_sub26_LOGICAL_in2_sel + connect \LOGICAL_cr_in \LOGICAL_dec_sub26_LOGICAL_cr_in + connect \LOGICAL_cr_out \LOGICAL_dec_sub26_LOGICAL_cr_out + connect \LOGICAL_ldst_len \LOGICAL_dec_sub26_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \LOGICAL_dec_sub26_LOGICAL_rc_sel + connect \LOGICAL_cry_in \LOGICAL_dec_sub26_LOGICAL_cry_in + connect \LOGICAL_inv_a \LOGICAL_dec_sub26_LOGICAL_inv_a + connect \LOGICAL_inv_out \LOGICAL_dec_sub26_LOGICAL_inv_out + connect \LOGICAL_cry_out \LOGICAL_dec_sub26_LOGICAL_cry_out + connect \LOGICAL_is_32b \LOGICAL_dec_sub26_LOGICAL_is_32b + connect \LOGICAL_sgn \LOGICAL_dec_sub26_LOGICAL_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub19_opcode_in + cell \LOGICAL_dec_sub19 \LOGICAL_dec_sub19 + connect \opcode_in \LOGICAL_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub22_opcode_in + cell \LOGICAL_dec_sub22 \LOGICAL_dec_sub22 + connect \opcode_in \LOGICAL_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub9_opcode_in + cell \LOGICAL_dec_sub9 \LOGICAL_dec_sub9 + connect \opcode_in \LOGICAL_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub11_opcode_in + cell \LOGICAL_dec_sub11 \LOGICAL_dec_sub11 + connect \opcode_in \LOGICAL_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub27_opcode_in + cell \LOGICAL_dec_sub27 \LOGICAL_dec_sub27 + connect \opcode_in \LOGICAL_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub15_opcode_in + cell \LOGICAL_dec_sub15 \LOGICAL_dec_sub15 + connect \opcode_in \LOGICAL_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub20_opcode_in + cell \LOGICAL_dec_sub20 \LOGICAL_dec_sub20 + connect \opcode_in \LOGICAL_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub21_opcode_in + cell \LOGICAL_dec_sub21 \LOGICAL_dec_sub21 + connect \opcode_in \LOGICAL_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub23_opcode_in + cell \LOGICAL_dec_sub23 \LOGICAL_dec_sub23 + connect \opcode_in \LOGICAL_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub16_opcode_in + cell \LOGICAL_dec_sub16 \LOGICAL_dec_sub16 + connect \opcode_in \LOGICAL_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub18_opcode_in + cell \LOGICAL_dec_sub18 \LOGICAL_dec_sub18 + connect \opcode_in \LOGICAL_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub8_opcode_in + cell \LOGICAL_dec_sub8 \LOGICAL_dec_sub8 + connect \opcode_in \LOGICAL_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub24_opcode_in + cell \LOGICAL_dec_sub24 \LOGICAL_dec_sub24 + connect \opcode_in \LOGICAL_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec_sub4_opcode_in + cell \LOGICAL_dec_sub4 \LOGICAL_dec_sub4 + connect \opcode_in \LOGICAL_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \LOGICAL_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \LOGICAL_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \LOGICAL_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \LOGICAL_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \LOGICAL_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \LOGICAL_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \LOGICAL_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \LOGICAL_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \LOGICAL_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \LOGICAL_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \LOGICAL_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \LOGICAL_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \LOGICAL_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \LOGICAL_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \LOGICAL_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \LOGICAL_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \LOGICAL_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \LOGICAL_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$14 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$16 + process $group_20 + assign \LOGICAL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_function_unit \LOGICAL_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_function_unit \LOGICAL_dec_sub28_LOGICAL_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_function_unit \LOGICAL_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_function_unit \LOGICAL_dec_sub26_LOGICAL_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_function_unit \LOGICAL_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_function_unit \LOGICAL_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_function_unit \LOGICAL_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_function_unit \LOGICAL_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_function_unit \LOGICAL_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_function_unit \LOGICAL_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_function_unit \LOGICAL_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_function_unit \LOGICAL_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_function_unit \LOGICAL_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_function_unit \LOGICAL_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_function_unit \LOGICAL_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_function_unit \LOGICAL_function_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_function_unit \LOGICAL_function_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_function_unit \LOGICAL_function_unit$16 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$31 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$32 + process $group_21 + assign \LOGICAL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_internal_op \LOGICAL_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_internal_op \LOGICAL_dec_sub28_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_internal_op \LOGICAL_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_internal_op \LOGICAL_dec_sub26_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_internal_op \LOGICAL_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_internal_op \LOGICAL_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_internal_op \LOGICAL_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_internal_op \LOGICAL_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_internal_op \LOGICAL_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_internal_op \LOGICAL_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_internal_op \LOGICAL_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_internal_op \LOGICAL_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_internal_op \LOGICAL_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_internal_op \LOGICAL_internal_op$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_internal_op \LOGICAL_internal_op$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_internal_op \LOGICAL_internal_op$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_internal_op \LOGICAL_internal_op$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_internal_op \LOGICAL_internal_op$32 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$33 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$34 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$35 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$36 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$37 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$38 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$39 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$40 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$41 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$42 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$43 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$44 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$45 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$46 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$47 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$48 + process $group_22 + assign \LOGICAL_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_in1_sel \LOGICAL_dec_sub28_LOGICAL_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_in1_sel \LOGICAL_dec_sub26_LOGICAL_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$48 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$49 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$50 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$51 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$52 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$53 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$54 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$55 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$56 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$57 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$58 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$59 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$60 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$61 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$62 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$63 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$64 + process $group_23 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_in2_sel \LOGICAL_dec_sub28_LOGICAL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_in2_sel \LOGICAL_dec_sub26_LOGICAL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$64 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$65 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$66 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$67 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$68 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$69 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$70 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$71 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$72 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$73 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$74 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$75 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$76 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$77 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$78 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$79 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$80 + process $group_24 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_cr_in \LOGICAL_cr_in$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_cr_in \LOGICAL_dec_sub28_LOGICAL_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_cr_in \LOGICAL_cr_in$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_cr_in \LOGICAL_dec_sub26_LOGICAL_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_cr_in \LOGICAL_cr_in$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_cr_in \LOGICAL_cr_in$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_cr_in \LOGICAL_cr_in$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_cr_in \LOGICAL_cr_in$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_cr_in \LOGICAL_cr_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_cr_in \LOGICAL_cr_in$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_cr_in \LOGICAL_cr_in$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_cr_in \LOGICAL_cr_in$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_cr_in \LOGICAL_cr_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_cr_in \LOGICAL_cr_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_cr_in \LOGICAL_cr_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_cr_in \LOGICAL_cr_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_cr_in \LOGICAL_cr_in$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_cr_in \LOGICAL_cr_in$80 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$81 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$82 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$83 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$84 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$85 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$86 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$87 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$88 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$89 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$90 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$91 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$92 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$93 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$94 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$95 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$96 + process $group_25 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_cr_out \LOGICAL_cr_out$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_cr_out \LOGICAL_dec_sub28_LOGICAL_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_cr_out \LOGICAL_cr_out$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_cr_out \LOGICAL_dec_sub26_LOGICAL_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_cr_out \LOGICAL_cr_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_cr_out \LOGICAL_cr_out$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_cr_out \LOGICAL_cr_out$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_cr_out \LOGICAL_cr_out$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_cr_out \LOGICAL_cr_out$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_cr_out \LOGICAL_cr_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_cr_out \LOGICAL_cr_out$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_cr_out \LOGICAL_cr_out$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_cr_out \LOGICAL_cr_out$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_cr_out \LOGICAL_cr_out$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_cr_out \LOGICAL_cr_out$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_cr_out \LOGICAL_cr_out$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_cr_out \LOGICAL_cr_out$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_cr_out \LOGICAL_cr_out$96 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$97 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$98 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$99 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$100 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$101 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$102 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$103 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$104 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$105 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$106 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$107 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$108 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$109 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$110 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$111 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$112 + process $group_26 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_ldst_len \LOGICAL_dec_sub28_LOGICAL_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_ldst_len \LOGICAL_dec_sub26_LOGICAL_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$112 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$113 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$114 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$115 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$116 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$117 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$118 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$119 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$120 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$121 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$122 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$123 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$124 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$125 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$126 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$127 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$128 + process $group_27 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_rc_sel \LOGICAL_dec_sub28_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_rc_sel \LOGICAL_dec_sub26_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$128 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$129 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$130 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$131 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$132 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$133 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$134 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$135 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$136 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$137 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$138 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$139 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$140 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$141 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$142 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$144 + process $group_28 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_cry_in \LOGICAL_cry_in$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_cry_in \LOGICAL_dec_sub28_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_cry_in \LOGICAL_cry_in$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_cry_in \LOGICAL_dec_sub26_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_cry_in \LOGICAL_cry_in$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_cry_in \LOGICAL_cry_in$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_cry_in \LOGICAL_cry_in$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_cry_in \LOGICAL_cry_in$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_cry_in \LOGICAL_cry_in$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_cry_in \LOGICAL_cry_in$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_cry_in \LOGICAL_cry_in$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_cry_in \LOGICAL_cry_in$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_cry_in \LOGICAL_cry_in$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_cry_in \LOGICAL_cry_in$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_cry_in \LOGICAL_cry_in$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_cry_in \LOGICAL_cry_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_cry_in \LOGICAL_cry_in$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_cry_in \LOGICAL_cry_in$144 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$160 + process $group_29 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_inv_a \LOGICAL_inv_a$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_inv_a \LOGICAL_dec_sub28_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_inv_a \LOGICAL_inv_a$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_inv_a \LOGICAL_dec_sub26_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_inv_a \LOGICAL_inv_a$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_inv_a \LOGICAL_inv_a$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_inv_a \LOGICAL_inv_a$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_inv_a \LOGICAL_inv_a$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_inv_a \LOGICAL_inv_a$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_inv_a \LOGICAL_inv_a$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_inv_a \LOGICAL_inv_a$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_inv_a \LOGICAL_inv_a$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_inv_a \LOGICAL_inv_a$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_inv_a \LOGICAL_inv_a$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_inv_a \LOGICAL_inv_a$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_inv_a \LOGICAL_inv_a$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_inv_a \LOGICAL_inv_a$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_inv_a \LOGICAL_inv_a$160 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$176 + process $group_30 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_inv_out \LOGICAL_inv_out$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_inv_out \LOGICAL_dec_sub28_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_inv_out \LOGICAL_inv_out$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_inv_out \LOGICAL_dec_sub26_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_inv_out \LOGICAL_inv_out$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_inv_out \LOGICAL_inv_out$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_inv_out \LOGICAL_inv_out$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_inv_out \LOGICAL_inv_out$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_inv_out \LOGICAL_inv_out$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_inv_out \LOGICAL_inv_out$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_inv_out \LOGICAL_inv_out$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_inv_out \LOGICAL_inv_out$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_inv_out \LOGICAL_inv_out$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_inv_out \LOGICAL_inv_out$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_inv_out \LOGICAL_inv_out$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_inv_out \LOGICAL_inv_out$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_inv_out \LOGICAL_inv_out$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_inv_out \LOGICAL_inv_out$176 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$192 + process $group_31 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_cry_out \LOGICAL_cry_out$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_cry_out \LOGICAL_dec_sub28_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_cry_out \LOGICAL_cry_out$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_cry_out \LOGICAL_dec_sub26_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_cry_out \LOGICAL_cry_out$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_cry_out \LOGICAL_cry_out$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_cry_out \LOGICAL_cry_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_cry_out \LOGICAL_cry_out$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_cry_out \LOGICAL_cry_out$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_cry_out \LOGICAL_cry_out$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_cry_out \LOGICAL_cry_out$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_cry_out \LOGICAL_cry_out$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_cry_out \LOGICAL_cry_out$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_cry_out \LOGICAL_cry_out$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_cry_out \LOGICAL_cry_out$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_cry_out \LOGICAL_cry_out$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_cry_out \LOGICAL_cry_out$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_cry_out \LOGICAL_cry_out$192 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$208 + process $group_32 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_is_32b \LOGICAL_is_32b$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_is_32b \LOGICAL_dec_sub28_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_is_32b \LOGICAL_is_32b$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_is_32b \LOGICAL_dec_sub26_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_is_32b \LOGICAL_is_32b$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_is_32b \LOGICAL_is_32b$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_is_32b \LOGICAL_is_32b$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_is_32b \LOGICAL_is_32b$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_is_32b \LOGICAL_is_32b$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_is_32b \LOGICAL_is_32b$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_is_32b \LOGICAL_is_32b$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_is_32b \LOGICAL_is_32b$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_is_32b \LOGICAL_is_32b$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_is_32b \LOGICAL_is_32b$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_is_32b \LOGICAL_is_32b$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_is_32b \LOGICAL_is_32b$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_is_32b \LOGICAL_is_32b$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_is_32b \LOGICAL_is_32b$208 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$224 + process $group_33 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LOGICAL_sgn \LOGICAL_sgn$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LOGICAL_sgn \LOGICAL_dec_sub28_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LOGICAL_sgn \LOGICAL_sgn$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LOGICAL_sgn \LOGICAL_dec_sub26_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LOGICAL_sgn \LOGICAL_sgn$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LOGICAL_sgn \LOGICAL_sgn$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LOGICAL_sgn \LOGICAL_sgn$213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LOGICAL_sgn \LOGICAL_sgn$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LOGICAL_sgn \LOGICAL_sgn$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LOGICAL_sgn \LOGICAL_sgn$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LOGICAL_sgn \LOGICAL_sgn$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LOGICAL_sgn \LOGICAL_sgn$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LOGICAL_sgn \LOGICAL_sgn$219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LOGICAL_sgn \LOGICAL_sgn$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LOGICAL_sgn \LOGICAL_sgn$221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LOGICAL_sgn \LOGICAL_sgn$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LOGICAL_sgn \LOGICAL_sgn$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LOGICAL_sgn \LOGICAL_sgn$224 + end + sync init + end + connect \LOGICAL_function_unit$1 11'00000000000 + connect \LOGICAL_function_unit$2 11'00000000000 + connect \LOGICAL_function_unit$3 11'00000000000 + connect \LOGICAL_function_unit$4 11'00000000000 + connect \LOGICAL_function_unit$5 11'00000000000 + connect \LOGICAL_function_unit$6 11'00000000000 + connect \LOGICAL_function_unit$7 11'00000000000 + connect \LOGICAL_function_unit$8 11'00000000000 + connect \LOGICAL_function_unit$9 11'00000000000 + connect \LOGICAL_function_unit$10 11'00000000000 + connect \LOGICAL_function_unit$11 11'00000000000 + connect \LOGICAL_function_unit$12 11'00000000000 + connect \LOGICAL_function_unit$13 11'00000000000 + connect \LOGICAL_function_unit$14 11'00000000000 + connect \LOGICAL_function_unit$15 11'00000000000 + connect \LOGICAL_function_unit$16 11'00000000000 + connect \LOGICAL_internal_op$17 7'0000000 + connect \LOGICAL_internal_op$18 7'0000000 + connect \LOGICAL_internal_op$19 7'0000000 + connect \LOGICAL_internal_op$20 7'0000000 + connect \LOGICAL_internal_op$21 7'0000000 + connect \LOGICAL_internal_op$22 7'0000000 + connect \LOGICAL_internal_op$23 7'0000000 + connect \LOGICAL_internal_op$24 7'0000000 + connect \LOGICAL_internal_op$25 7'0000000 + connect \LOGICAL_internal_op$26 7'0000000 + connect \LOGICAL_internal_op$27 7'0000000 + connect \LOGICAL_internal_op$28 7'0000000 + connect \LOGICAL_internal_op$29 7'0000000 + connect \LOGICAL_internal_op$30 7'0000000 + connect \LOGICAL_internal_op$31 7'0000000 + connect \LOGICAL_internal_op$32 7'0000000 + connect \LOGICAL_in1_sel$33 3'000 + connect \LOGICAL_in1_sel$34 3'000 + connect \LOGICAL_in1_sel$35 3'000 + connect \LOGICAL_in1_sel$36 3'000 + connect \LOGICAL_in1_sel$37 3'000 + connect \LOGICAL_in1_sel$38 3'000 + connect \LOGICAL_in1_sel$39 3'000 + connect \LOGICAL_in1_sel$40 3'000 + connect \LOGICAL_in1_sel$41 3'000 + connect \LOGICAL_in1_sel$42 3'000 + connect \LOGICAL_in1_sel$43 3'000 + connect \LOGICAL_in1_sel$44 3'000 + connect \LOGICAL_in1_sel$45 3'000 + connect \LOGICAL_in1_sel$46 3'000 + connect \LOGICAL_in1_sel$47 3'000 + connect \LOGICAL_in1_sel$48 3'000 + connect \LOGICAL_in2_sel$49 4'0000 + connect \LOGICAL_in2_sel$50 4'0000 + connect \LOGICAL_in2_sel$51 4'0000 + connect \LOGICAL_in2_sel$52 4'0000 + connect \LOGICAL_in2_sel$53 4'0000 + connect \LOGICAL_in2_sel$54 4'0000 + connect \LOGICAL_in2_sel$55 4'0000 + connect \LOGICAL_in2_sel$56 4'0000 + connect \LOGICAL_in2_sel$57 4'0000 + connect \LOGICAL_in2_sel$58 4'0000 + connect \LOGICAL_in2_sel$59 4'0000 + connect \LOGICAL_in2_sel$60 4'0000 + connect \LOGICAL_in2_sel$61 4'0000 + connect \LOGICAL_in2_sel$62 4'0000 + connect \LOGICAL_in2_sel$63 4'0000 + connect \LOGICAL_in2_sel$64 4'0000 + connect \LOGICAL_cr_in$65 3'000 + connect \LOGICAL_cr_in$66 3'000 + connect \LOGICAL_cr_in$67 3'000 + connect \LOGICAL_cr_in$68 3'000 + connect \LOGICAL_cr_in$69 3'000 + connect \LOGICAL_cr_in$70 3'000 + connect \LOGICAL_cr_in$71 3'000 + connect \LOGICAL_cr_in$72 3'000 + connect \LOGICAL_cr_in$73 3'000 + connect \LOGICAL_cr_in$74 3'000 + connect \LOGICAL_cr_in$75 3'000 + connect \LOGICAL_cr_in$76 3'000 + connect \LOGICAL_cr_in$77 3'000 + connect \LOGICAL_cr_in$78 3'000 + connect \LOGICAL_cr_in$79 3'000 + connect \LOGICAL_cr_in$80 3'000 + connect \LOGICAL_cr_out$81 3'000 + connect \LOGICAL_cr_out$82 3'000 + connect \LOGICAL_cr_out$83 3'000 + connect \LOGICAL_cr_out$84 3'000 + connect \LOGICAL_cr_out$85 3'000 + connect \LOGICAL_cr_out$86 3'000 + connect \LOGICAL_cr_out$87 3'000 + connect \LOGICAL_cr_out$88 3'000 + connect \LOGICAL_cr_out$89 3'000 + connect \LOGICAL_cr_out$90 3'000 + connect \LOGICAL_cr_out$91 3'000 + connect \LOGICAL_cr_out$92 3'000 + connect \LOGICAL_cr_out$93 3'000 + connect \LOGICAL_cr_out$94 3'000 + connect \LOGICAL_cr_out$95 3'000 + connect \LOGICAL_cr_out$96 3'000 + connect \LOGICAL_ldst_len$97 4'0000 + connect \LOGICAL_ldst_len$98 4'0000 + connect \LOGICAL_ldst_len$99 4'0000 + connect \LOGICAL_ldst_len$100 4'0000 + connect \LOGICAL_ldst_len$101 4'0000 + connect \LOGICAL_ldst_len$102 4'0000 + connect \LOGICAL_ldst_len$103 4'0000 + connect \LOGICAL_ldst_len$104 4'0000 + connect \LOGICAL_ldst_len$105 4'0000 + connect \LOGICAL_ldst_len$106 4'0000 + connect \LOGICAL_ldst_len$107 4'0000 + connect \LOGICAL_ldst_len$108 4'0000 + connect \LOGICAL_ldst_len$109 4'0000 + connect \LOGICAL_ldst_len$110 4'0000 + connect \LOGICAL_ldst_len$111 4'0000 + connect \LOGICAL_ldst_len$112 4'0000 + connect \LOGICAL_rc_sel$113 2'00 + connect \LOGICAL_rc_sel$114 2'00 + connect \LOGICAL_rc_sel$115 2'00 + connect \LOGICAL_rc_sel$116 2'00 + connect \LOGICAL_rc_sel$117 2'00 + connect \LOGICAL_rc_sel$118 2'00 + connect \LOGICAL_rc_sel$119 2'00 + connect \LOGICAL_rc_sel$120 2'00 + connect \LOGICAL_rc_sel$121 2'00 + connect \LOGICAL_rc_sel$122 2'00 + connect \LOGICAL_rc_sel$123 2'00 + connect \LOGICAL_rc_sel$124 2'00 + connect \LOGICAL_rc_sel$125 2'00 + connect \LOGICAL_rc_sel$126 2'00 + connect \LOGICAL_rc_sel$127 2'00 + connect \LOGICAL_rc_sel$128 2'00 + connect \LOGICAL_cry_in$129 2'00 + connect \LOGICAL_cry_in$130 2'00 + connect \LOGICAL_cry_in$131 2'00 + connect \LOGICAL_cry_in$132 2'00 + connect \LOGICAL_cry_in$133 2'00 + connect \LOGICAL_cry_in$134 2'00 + connect \LOGICAL_cry_in$135 2'00 + connect \LOGICAL_cry_in$136 2'00 + connect \LOGICAL_cry_in$137 2'00 + connect \LOGICAL_cry_in$138 2'00 + connect \LOGICAL_cry_in$139 2'00 + connect \LOGICAL_cry_in$140 2'00 + connect \LOGICAL_cry_in$141 2'00 + connect \LOGICAL_cry_in$142 2'00 + connect \LOGICAL_cry_in$143 2'00 + connect \LOGICAL_cry_in$144 2'00 + connect \LOGICAL_inv_a$145 1'0 + connect \LOGICAL_inv_a$146 1'0 + connect \LOGICAL_inv_a$147 1'0 + connect \LOGICAL_inv_a$148 1'0 + connect \LOGICAL_inv_a$149 1'0 + connect \LOGICAL_inv_a$150 1'0 + connect \LOGICAL_inv_a$151 1'0 + connect \LOGICAL_inv_a$152 1'0 + connect \LOGICAL_inv_a$153 1'0 + connect \LOGICAL_inv_a$154 1'0 + connect \LOGICAL_inv_a$155 1'0 + connect \LOGICAL_inv_a$156 1'0 + connect \LOGICAL_inv_a$157 1'0 + connect \LOGICAL_inv_a$158 1'0 + connect \LOGICAL_inv_a$159 1'0 + connect \LOGICAL_inv_a$160 1'0 + connect \LOGICAL_inv_out$161 1'0 + connect \LOGICAL_inv_out$162 1'0 + connect \LOGICAL_inv_out$163 1'0 + connect \LOGICAL_inv_out$164 1'0 + connect \LOGICAL_inv_out$165 1'0 + connect \LOGICAL_inv_out$166 1'0 + connect \LOGICAL_inv_out$167 1'0 + connect \LOGICAL_inv_out$168 1'0 + connect \LOGICAL_inv_out$169 1'0 + connect \LOGICAL_inv_out$170 1'0 + connect \LOGICAL_inv_out$171 1'0 + connect \LOGICAL_inv_out$172 1'0 + connect \LOGICAL_inv_out$173 1'0 + connect \LOGICAL_inv_out$174 1'0 + connect \LOGICAL_inv_out$175 1'0 + connect \LOGICAL_inv_out$176 1'0 + connect \LOGICAL_cry_out$177 1'0 + connect \LOGICAL_cry_out$178 1'0 + connect \LOGICAL_cry_out$179 1'0 + connect \LOGICAL_cry_out$180 1'0 + connect \LOGICAL_cry_out$181 1'0 + connect \LOGICAL_cry_out$182 1'0 + connect \LOGICAL_cry_out$183 1'0 + connect \LOGICAL_cry_out$184 1'0 + connect \LOGICAL_cry_out$185 1'0 + connect \LOGICAL_cry_out$186 1'0 + connect \LOGICAL_cry_out$187 1'0 + connect \LOGICAL_cry_out$188 1'0 + connect \LOGICAL_cry_out$189 1'0 + connect \LOGICAL_cry_out$190 1'0 + connect \LOGICAL_cry_out$191 1'0 + connect \LOGICAL_cry_out$192 1'0 + connect \LOGICAL_is_32b$193 1'0 + connect \LOGICAL_is_32b$194 1'0 + connect \LOGICAL_is_32b$195 1'0 + connect \LOGICAL_is_32b$196 1'0 + connect \LOGICAL_is_32b$197 1'0 + connect \LOGICAL_is_32b$198 1'0 + connect \LOGICAL_is_32b$199 1'0 + connect \LOGICAL_is_32b$200 1'0 + connect \LOGICAL_is_32b$201 1'0 + connect \LOGICAL_is_32b$202 1'0 + connect \LOGICAL_is_32b$203 1'0 + connect \LOGICAL_is_32b$204 1'0 + connect \LOGICAL_is_32b$205 1'0 + connect \LOGICAL_is_32b$206 1'0 + connect \LOGICAL_is_32b$207 1'0 + connect \LOGICAL_is_32b$208 1'0 + connect \LOGICAL_sgn$209 1'0 + connect \LOGICAL_sgn$210 1'0 + connect \LOGICAL_sgn$211 1'0 + connect \LOGICAL_sgn$212 1'0 + connect \LOGICAL_sgn$213 1'0 + connect \LOGICAL_sgn$214 1'0 + connect \LOGICAL_sgn$215 1'0 + connect \LOGICAL_sgn$216 1'0 + connect \LOGICAL_sgn$217 1'0 + connect \LOGICAL_sgn$218 1'0 + connect \LOGICAL_sgn$219 1'0 + connect \LOGICAL_sgn$220 1'0 + connect \LOGICAL_sgn$221 1'0 + connect \LOGICAL_sgn$222 1'0 + connect \LOGICAL_sgn$223 1'0 + connect \LOGICAL_sgn$224 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec58" +module \LOGICAL_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec62" +module \LOGICAL_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec" +module \dec$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \LOGICAL_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LOGICAL_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \LOGICAL_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 8 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 9 \LOGICAL_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 10 \LOGICAL_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LOGICAL_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 17 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 18 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 19 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 20 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 21 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 22 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 23 \LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 24 \LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 25 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 26 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 27 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 28 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 29 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 30 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 31 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 32 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec19_opcode_in + cell \LOGICAL_dec19 \LOGICAL_dec19 + connect \opcode_in \LOGICAL_dec19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec30_opcode_in + cell \LOGICAL_dec30 \LOGICAL_dec30 + connect \opcode_in \LOGICAL_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_dec31_LOGICAL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_dec31_LOGICAL_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec31_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_dec31_LOGICAL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec31_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_dec31_LOGICAL_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_dec31_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_dec31_LOGICAL_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_dec31_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec31_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec31_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec31_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec31_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_dec31_LOGICAL_sgn + cell \LOGICAL_dec31 \LOGICAL_dec31 + connect \opcode_in \LOGICAL_dec31_opcode_in + connect \LOGICAL_function_unit \LOGICAL_dec31_LOGICAL_function_unit + connect \LOGICAL_internal_op \LOGICAL_dec31_LOGICAL_internal_op + connect \LOGICAL_in1_sel \LOGICAL_dec31_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \LOGICAL_dec31_LOGICAL_in2_sel + connect \LOGICAL_cr_in \LOGICAL_dec31_LOGICAL_cr_in + connect \LOGICAL_cr_out \LOGICAL_dec31_LOGICAL_cr_out + connect \LOGICAL_ldst_len \LOGICAL_dec31_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \LOGICAL_dec31_LOGICAL_rc_sel + connect \LOGICAL_cry_in \LOGICAL_dec31_LOGICAL_cry_in + connect \LOGICAL_inv_a \LOGICAL_dec31_LOGICAL_inv_a + connect \LOGICAL_inv_out \LOGICAL_dec31_LOGICAL_inv_out + connect \LOGICAL_cry_out \LOGICAL_dec31_LOGICAL_cry_out + connect \LOGICAL_is_32b \LOGICAL_dec31_LOGICAL_is_32b + connect \LOGICAL_sgn \LOGICAL_dec31_LOGICAL_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec58_opcode_in + cell \LOGICAL_dec58 \LOGICAL_dec58 + connect \opcode_in \LOGICAL_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LOGICAL_dec62_opcode_in + cell \LOGICAL_dec62 \LOGICAL_dec62 + connect \opcode_in \LOGICAL_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \LOGICAL_dec19_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \LOGICAL_dec30_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \LOGICAL_dec31_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \LOGICAL_dec58_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \LOGICAL_dec62_opcode_in 32'00000000000000000000000000000000 + assign \LOGICAL_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LOGICAL_function_unit$4 + process $group_6 + assign \LOGICAL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_function_unit \LOGICAL_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_function_unit \LOGICAL_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_function_unit \LOGICAL_dec31_LOGICAL_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_function_unit \LOGICAL_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_function_unit \LOGICAL_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_function_unit 11'00000010000 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LOGICAL_internal_op$8 + process $group_7 + assign \LOGICAL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_internal_op \LOGICAL_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_internal_op \LOGICAL_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_internal_op \LOGICAL_dec31_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_internal_op \LOGICAL_internal_op$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_internal_op \LOGICAL_internal_op$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_internal_op 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_internal_op 7'1000011 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$9 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$10 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$11 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_in1_sel$12 + process $group_8 + assign \LOGICAL_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_in1_sel \LOGICAL_dec31_LOGICAL_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_in1_sel \LOGICAL_in1_sel$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_in1_sel 3'100 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$13 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$14 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$15 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_in2_sel$16 + process $group_9 + assign \LOGICAL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_in2_sel \LOGICAL_dec31_LOGICAL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_in2_sel \LOGICAL_in2_sel$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_in2_sel 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_in2_sel 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_in2_sel 4'0100 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$17 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$18 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$19 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_in$20 + process $group_10 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_cr_in \LOGICAL_cr_in$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_cr_in \LOGICAL_cr_in$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_cr_in \LOGICAL_dec31_LOGICAL_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_cr_in \LOGICAL_cr_in$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_cr_in \LOGICAL_cr_in$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_cr_in 3'000 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$21 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$22 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$23 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LOGICAL_cr_out$24 + process $group_11 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_cr_out \LOGICAL_cr_out$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_cr_out \LOGICAL_cr_out$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_cr_out \LOGICAL_dec31_LOGICAL_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_cr_out \LOGICAL_cr_out$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_cr_out \LOGICAL_cr_out$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_cr_out 3'000 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$25 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$26 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$27 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LOGICAL_ldst_len$28 + process $group_12 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_ldst_len \LOGICAL_dec31_LOGICAL_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_ldst_len \LOGICAL_ldst_len$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_ldst_len 4'0000 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$29 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$30 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$31 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_rc_sel$32 + process $group_13 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_rc_sel \LOGICAL_dec31_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_rc_sel \LOGICAL_rc_sel$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_rc_sel 2'00 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$33 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$35 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LOGICAL_cry_in$36 + process $group_14 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_cry_in \LOGICAL_cry_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_cry_in \LOGICAL_cry_in$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_cry_in \LOGICAL_dec31_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_cry_in \LOGICAL_cry_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_cry_in \LOGICAL_cry_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_cry_in 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_a$40 + process $group_15 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_inv_a \LOGICAL_inv_a$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_inv_a \LOGICAL_inv_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_inv_a \LOGICAL_dec31_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_inv_a \LOGICAL_inv_a$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_inv_a \LOGICAL_inv_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_inv_a 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_inv_out$44 + process $group_16 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_inv_out \LOGICAL_inv_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_inv_out \LOGICAL_inv_out$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_inv_out \LOGICAL_dec31_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_inv_out \LOGICAL_inv_out$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_inv_out \LOGICAL_inv_out$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_inv_out 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_cry_out$48 + process $group_17 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_cry_out \LOGICAL_cry_out$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_cry_out \LOGICAL_cry_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_cry_out \LOGICAL_dec31_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_cry_out \LOGICAL_cry_out$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_cry_out \LOGICAL_cry_out$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_cry_out 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_is_32b$52 + process $group_18 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_is_32b \LOGICAL_is_32b$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_is_32b \LOGICAL_is_32b$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_is_32b \LOGICAL_dec31_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_is_32b \LOGICAL_is_32b$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_is_32b \LOGICAL_is_32b$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_is_32b 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LOGICAL_sgn$56 + process $group_19 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LOGICAL_sgn \LOGICAL_sgn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LOGICAL_sgn \LOGICAL_sgn$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LOGICAL_sgn \LOGICAL_dec31_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LOGICAL_sgn \LOGICAL_sgn$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LOGICAL_sgn \LOGICAL_sgn$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \LOGICAL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \LOGICAL_sgn 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$57 + process $group_20 + assign \opcode_switch$57 32'00000000000000000000000000000000 + assign \opcode_switch$57 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $59 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $58 + end + process $group_21 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $58 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_RS + process $group_22 + assign \LOGICAL_RS 5'00000 + assign \LOGICAL_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_RT + process $group_23 + assign \LOGICAL_RT 5'00000 + assign \LOGICAL_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_24 + assign \LOGICAL_RA 5'00000 + assign \LOGICAL_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_RB + process $group_25 + assign \LOGICAL_RB 5'00000 + assign \LOGICAL_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_26 + assign \LOGICAL_SI 16'0000000000000000 + assign \LOGICAL_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_27 + assign \LOGICAL_UI 16'0000000000000000 + assign \LOGICAL_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \LOGICAL_L + process $group_28 + assign \LOGICAL_L 1'0 + assign \LOGICAL_L { \opcode_in [21] } + sync init + end + process $group_29 + assign \LOGICAL_SH32 5'00000 + assign \LOGICAL_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_30 + assign \LOGICAL_sh 6'000000 + assign \LOGICAL_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_MB32 + process $group_31 + assign \LOGICAL_MB32 5'00000 + assign \LOGICAL_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_ME32 + process $group_32 + assign \LOGICAL_ME32 5'00000 + assign \LOGICAL_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_33 + assign \LOGICAL_LI 24'000000000000000000000000 + assign \LOGICAL_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \LOGICAL_LK + process $group_34 + assign \LOGICAL_LK 1'0 + assign \LOGICAL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \LOGICAL_AA + process $group_35 + assign \LOGICAL_AA 1'0 + assign \LOGICAL_AA { \opcode_in [1] } + sync init + end + process $group_36 + assign \LOGICAL_Rc 1'0 + assign \LOGICAL_Rc { \opcode_in [0] } + sync init + end + process $group_37 + assign \LOGICAL_OE 1'0 + assign \LOGICAL_OE { \opcode_in [10] } + sync init + end + process $group_38 + assign \LOGICAL_BD 14'00000000000000 + assign \LOGICAL_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \LOGICAL_BF + process $group_39 + assign \LOGICAL_BF 3'000 + assign \LOGICAL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \LOGICAL_CR + process $group_40 + assign \LOGICAL_CR 10'0000000000 + assign \LOGICAL_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_41 + assign \LOGICAL_BB 5'00000 + assign \LOGICAL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_42 + assign \LOGICAL_BA 5'00000 + assign \LOGICAL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_43 + assign \LOGICAL_BT 5'00000 + assign \LOGICAL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_44 + assign \LOGICAL_FXM 8'00000000 + assign \LOGICAL_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_BO + process $group_45 + assign \LOGICAL_BO 5'00000 + assign \LOGICAL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_46 + assign \LOGICAL_BI 5'00000 + assign \LOGICAL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \LOGICAL_BH + process $group_47 + assign \LOGICAL_BH 2'00 + assign \LOGICAL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \LOGICAL_D + process $group_48 + assign \LOGICAL_D 16'0000000000000000 + assign \LOGICAL_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_49 + assign \LOGICAL_DS 14'00000000000000 + assign \LOGICAL_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_TO + process $group_50 + assign \LOGICAL_TO 5'00000 + assign \LOGICAL_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_51 + assign \LOGICAL_BC 5'00000 + assign \LOGICAL_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_SH + process $group_52 + assign \LOGICAL_SH 5'00000 + assign \LOGICAL_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_ME + process $group_53 + assign \LOGICAL_ME 5'00000 + assign \LOGICAL_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LOGICAL_MB + process $group_54 + assign \LOGICAL_MB 5'00000 + assign \LOGICAL_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \LOGICAL_SPR + process $group_55 + assign \LOGICAL_SPR 10'0000000000 + assign \LOGICAL_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_56 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_57 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_58 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_59 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_60 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_61 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_62 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_63 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_64 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_65 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_66 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_67 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_68 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_69 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_70 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_71 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_72 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_73 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_74 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_75 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_76 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_77 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_78 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_79 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_80 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_81 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_82 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_83 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_84 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_85 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_86 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_87 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_88 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_89 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_90 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_91 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_92 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_93 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_94 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_95 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_96 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_97 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_98 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_99 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_100 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_101 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_102 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_103 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_104 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_105 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_106 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_107 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_108 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_109 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_110 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_111 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_112 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_113 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_114 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_115 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_116 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_117 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_118 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_119 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_120 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_121 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_122 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_123 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_124 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_125 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_126 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_127 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_128 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_129 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_130 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_131 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_132 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_133 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_134 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_135 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_136 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_137 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_138 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_139 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_140 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_141 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_142 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_143 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_144 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_145 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_146 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_147 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_148 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_149 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_150 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_151 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_152 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_153 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_154 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_155 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_156 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_157 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_158 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_159 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_160 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_161 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_162 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_163 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_164 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_165 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_166 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_167 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_168 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_169 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_170 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_171 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_172 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_173 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_174 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_175 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_176 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_177 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_178 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_179 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_180 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_181 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_182 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_183 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_184 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_185 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_186 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_187 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_188 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_189 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_190 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_191 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_192 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_193 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_194 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_195 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_196 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_197 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_198 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_199 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_200 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_201 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_202 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_203 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_204 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_205 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_206 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_207 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_208 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_209 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_210 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_211 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_212 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_213 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_214 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_215 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_216 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_217 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_218 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_219 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_220 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_221 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_222 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_223 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_224 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_225 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_226 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_227 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_228 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_229 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_230 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_231 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_232 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_233 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_234 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_235 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_236 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_237 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_238 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_239 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_240 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_241 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_242 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_243 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_244 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_245 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_246 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_247 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_248 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_249 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_250 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_251 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_252 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_253 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_254 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_255 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_256 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_257 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_258 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_259 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_260 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_261 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_262 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_263 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_264 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_265 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_266 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_267 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_268 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_269 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_270 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_271 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_272 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_273 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_274 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_275 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_276 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_277 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_278 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_279 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_280 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_281 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_282 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_283 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_284 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_285 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_286 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_287 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_288 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_289 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_290 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_291 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_292 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_293 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_294 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_295 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_296 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_297 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_298 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_299 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_300 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_301 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_302 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_303 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_304 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_305 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_306 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_307 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_308 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_309 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_310 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_311 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_312 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_313 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_314 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_315 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_316 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_317 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_318 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_319 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_320 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_321 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_322 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_323 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_324 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_325 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_326 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_327 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_328 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_329 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_330 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_331 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_332 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_333 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_334 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_335 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_336 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_337 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_338 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_339 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_340 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_341 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_342 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_343 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_344 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_345 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_346 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_347 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \LOGICAL_function_unit$1 11'00000000000 + connect \LOGICAL_function_unit$2 11'00000000000 + connect \LOGICAL_function_unit$3 11'00000000000 + connect \LOGICAL_function_unit$4 11'00000000000 + connect \LOGICAL_internal_op$5 7'0000000 + connect \LOGICAL_internal_op$6 7'0000000 + connect \LOGICAL_internal_op$7 7'0000000 + connect \LOGICAL_internal_op$8 7'0000000 + connect \LOGICAL_in1_sel$9 3'000 + connect \LOGICAL_in1_sel$10 3'000 + connect \LOGICAL_in1_sel$11 3'000 + connect \LOGICAL_in1_sel$12 3'000 + connect \LOGICAL_in2_sel$13 4'0000 + connect \LOGICAL_in2_sel$14 4'0000 + connect \LOGICAL_in2_sel$15 4'0000 + connect \LOGICAL_in2_sel$16 4'0000 + connect \LOGICAL_cr_in$17 3'000 + connect \LOGICAL_cr_in$18 3'000 + connect \LOGICAL_cr_in$19 3'000 + connect \LOGICAL_cr_in$20 3'000 + connect \LOGICAL_cr_out$21 3'000 + connect \LOGICAL_cr_out$22 3'000 + connect \LOGICAL_cr_out$23 3'000 + connect \LOGICAL_cr_out$24 3'000 + connect \LOGICAL_ldst_len$25 4'0000 + connect \LOGICAL_ldst_len$26 4'0000 + connect \LOGICAL_ldst_len$27 4'0000 + connect \LOGICAL_ldst_len$28 4'0000 + connect \LOGICAL_rc_sel$29 2'00 + connect \LOGICAL_rc_sel$30 2'00 + connect \LOGICAL_rc_sel$31 2'00 + connect \LOGICAL_rc_sel$32 2'00 + connect \LOGICAL_cry_in$33 2'00 + connect \LOGICAL_cry_in$34 2'00 + connect \LOGICAL_cry_in$35 2'00 + connect \LOGICAL_cry_in$36 2'00 + connect \LOGICAL_inv_a$37 1'0 + connect \LOGICAL_inv_a$38 1'0 + connect \LOGICAL_inv_a$39 1'0 + connect \LOGICAL_inv_a$40 1'0 + connect \LOGICAL_inv_out$41 1'0 + connect \LOGICAL_inv_out$42 1'0 + connect \LOGICAL_inv_out$43 1'0 + connect \LOGICAL_inv_out$44 1'0 + connect \LOGICAL_cry_out$45 1'0 + connect \LOGICAL_cry_out$46 1'0 + connect \LOGICAL_cry_out$47 1'0 + connect \LOGICAL_cry_out$48 1'0 + connect \LOGICAL_is_32b$49 1'0 + connect \LOGICAL_is_32b$50 1'0 + connect \LOGICAL_is_32b$51 1'0 + connect \LOGICAL_is_32b$52 1'0 + connect \LOGICAL_sgn$53 1'0 + connect \LOGICAL_sgn$54 1'0 + connect \LOGICAL_sgn$55 1'0 + connect \LOGICAL_sgn$56 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_rc" +module \dec_rc$153 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \LOGICAL_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_oe" +module \dec_oe$154 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \LOGICAL_OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \LOGICAL_OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in.ppick" +module \ppick$156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in" +module \dec_cr_in$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$156 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \LOGICAL_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \LOGICAL_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \LOGICAL_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \LOGICAL_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \LOGICAL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out.ppick" +module \ppick$158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out" +module \dec_cr_out$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 5 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$158 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \LOGICAL_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_ai" +module \dec_ai$159 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 output 1 \immz_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 2 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + process $group_0 + assign \ra 5'00000 + assign \ra \LOGICAL_RA + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B $3 + connect \Y $5 + end + process $group_1 + assign \immz_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + case 1'1 + assign \immz_out 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_bi" +module \dec_bi$160 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL" +module \dec_LOGICAL + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LOGICAL_LOGICAL__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \LOGICAL_LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LOGICAL_LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \LOGICAL_LOGICAL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 6 \LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 7 \LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \LOGICAL_LOGICAL__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 17 \LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \LOGICAL_LOGICAL__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \LOGICAL_LOGICAL__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_LOGICAL_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_LOGICAL_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_LOGICAL_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_LOGICAL_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_LOGICAL_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LOGICAL_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LOGICAL_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LOGICAL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$152 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_cr_in \dec_LOGICAL_cr_in + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc$153 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \LOGICAL_Rc \dec_LOGICAL_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe$154 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \LOGICAL_OE \dec_LOGICAL_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$155 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + cell \dec_cr_out$157 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 \dec_ai_immz_out + cell \dec_ai$159 \dec_ai + connect \sel_in \dec_ai_sel_in + connect \immz_out \dec_ai_immz_out + connect \LOGICAL_RA \dec_LOGICAL_RA + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi$160 \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + end + process $group_0 + assign \LOGICAL_LOGICAL__insn 32'00000000000000000000000000000000 + assign \LOGICAL_LOGICAL__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_LOGICAL_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_LOGICAL_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_LOGICAL_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_LOGICAL_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \LOGICAL_LOGICAL__insn_type 7'0000000 + assign \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_internal_op + sync init + end + process $group_11 + assign \LOGICAL_LOGICAL__fn_unit 11'00000000000 + assign \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_function_unit + sync init + end + process $group_12 + assign \dec_ai_sel_in 3'000 + assign \dec_ai_sel_in \dec_LOGICAL_in1_sel + sync init + end + process $group_13 + assign \LOGICAL_LOGICAL__zero_a 1'0 + assign \LOGICAL_LOGICAL__zero_a \dec_ai_immz_out + sync init + end + process $group_14 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_LOGICAL_in2_sel + sync init + end + process $group_15 + assign \LOGICAL_LOGICAL__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \LOGICAL_LOGICAL__imm_data__ok 1'0 + assign { \LOGICAL_LOGICAL__imm_data__ok \LOGICAL_LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_17 + assign \LOGICAL_LOGICAL__rc__rc 1'0 + assign \LOGICAL_LOGICAL__rc__ok 1'0 + assign { \LOGICAL_LOGICAL__rc__ok \LOGICAL_LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + sync init + end + process $group_19 + assign \LOGICAL_LOGICAL__oe__oe 1'0 + assign \LOGICAL_LOGICAL__oe__ok 1'0 + assign { \LOGICAL_LOGICAL__oe__ok \LOGICAL_LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + sync init + end + process $group_21 + assign \LOGICAL_LOGICAL__write_cr0 1'0 + assign \LOGICAL_LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok + sync init + end + process $group_22 + assign \LOGICAL_LOGICAL__data_len 4'0000 + assign \LOGICAL_LOGICAL__data_len \dec_LOGICAL_ldst_len + sync init + end + process $group_23 + assign \LOGICAL_LOGICAL__invert_in 1'0 + assign \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_inv_a + sync init + end + process $group_24 + assign \LOGICAL_LOGICAL__invert_out 1'0 + assign \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_inv_out + sync init + end + process $group_25 + assign \LOGICAL_LOGICAL__input_carry 2'00 + assign \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_cry_in + sync init + end + process $group_26 + assign \LOGICAL_LOGICAL__output_carry 1'0 + assign \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_cry_out + sync init + end + process $group_27 + assign \LOGICAL_LOGICAL__is_32bit 1'0 + assign \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_is_32b + sync init + end + process $group_28 + assign \LOGICAL_LOGICAL__is_signed 1'0 + assign \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_sgn + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec19" +module \SPR_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_1 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec30" +module \SPR_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub10" +module \SPR_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub28" +module \SPR_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub0" +module \SPR_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub26" +module \SPR_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub19" +module \SPR_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SPR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SPR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 6 \SPR_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \SPR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \SPR_function_unit 11'10000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \SPR_function_unit 11'10000000000 + end + sync init + end + process $group_2 + assign \SPR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \SPR_internal_op 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \SPR_internal_op 7'0110001 + end + sync init + end + process $group_3 + assign \SPR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \SPR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \SPR_cr_in 3'000 + end + sync init + end + process $group_4 + assign \SPR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \SPR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \SPR_cr_out 3'000 + end + sync init + end + process $group_5 + assign \SPR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \SPR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \SPR_rc_sel 2'00 + end + sync init + end + process $group_6 + assign \SPR_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \SPR_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \SPR_is_32b 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub22" +module \SPR_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub9" +module \SPR_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub11" +module \SPR_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub27" +module \SPR_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub15" +module \SPR_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub20" +module \SPR_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub21" +module \SPR_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub23" +module \SPR_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub16" +module \SPR_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub18" +module \SPR_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub8" +module \SPR_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub24" +module \SPR_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec_sub4" +module \SPR_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31" +module \SPR_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SPR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SPR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 5 \SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 6 \SPR_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub10_opcode_in + cell \SPR_dec_sub10 \SPR_dec_sub10 + connect \opcode_in \SPR_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub28_opcode_in + cell \SPR_dec_sub28 \SPR_dec_sub28 + connect \opcode_in \SPR_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub0_opcode_in + cell \SPR_dec_sub0 \SPR_dec_sub0 + connect \opcode_in \SPR_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub26_opcode_in + cell \SPR_dec_sub26 \SPR_dec_sub26 + connect \opcode_in \SPR_dec_sub26_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_dec_sub19_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_dec_sub19_SPR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_dec_sub19_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_dec_sub19_SPR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_dec_sub19_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_dec_sub19_SPR_is_32b + cell \SPR_dec_sub19 \SPR_dec_sub19 + connect \opcode_in \SPR_dec_sub19_opcode_in + connect \SPR_function_unit \SPR_dec_sub19_SPR_function_unit + connect \SPR_internal_op \SPR_dec_sub19_SPR_internal_op + connect \SPR_cr_in \SPR_dec_sub19_SPR_cr_in + connect \SPR_cr_out \SPR_dec_sub19_SPR_cr_out + connect \SPR_rc_sel \SPR_dec_sub19_SPR_rc_sel + connect \SPR_is_32b \SPR_dec_sub19_SPR_is_32b + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub22_opcode_in + cell \SPR_dec_sub22 \SPR_dec_sub22 + connect \opcode_in \SPR_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub9_opcode_in + cell \SPR_dec_sub9 \SPR_dec_sub9 + connect \opcode_in \SPR_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub11_opcode_in + cell \SPR_dec_sub11 \SPR_dec_sub11 + connect \opcode_in \SPR_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub27_opcode_in + cell \SPR_dec_sub27 \SPR_dec_sub27 + connect \opcode_in \SPR_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub15_opcode_in + cell \SPR_dec_sub15 \SPR_dec_sub15 + connect \opcode_in \SPR_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub20_opcode_in + cell \SPR_dec_sub20 \SPR_dec_sub20 + connect \opcode_in \SPR_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub21_opcode_in + cell \SPR_dec_sub21 \SPR_dec_sub21 + connect \opcode_in \SPR_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub23_opcode_in + cell \SPR_dec_sub23 \SPR_dec_sub23 + connect \opcode_in \SPR_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub16_opcode_in + cell \SPR_dec_sub16 \SPR_dec_sub16 + connect \opcode_in \SPR_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub18_opcode_in + cell \SPR_dec_sub18 \SPR_dec_sub18 + connect \opcode_in \SPR_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub8_opcode_in + cell \SPR_dec_sub8 \SPR_dec_sub8 + connect \opcode_in \SPR_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub24_opcode_in + cell \SPR_dec_sub24 \SPR_dec_sub24 + connect \opcode_in \SPR_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec_sub4_opcode_in + cell \SPR_dec_sub4 \SPR_dec_sub4 + connect \opcode_in \SPR_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \SPR_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \SPR_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \SPR_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \SPR_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \SPR_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \SPR_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \SPR_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \SPR_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \SPR_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \SPR_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \SPR_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \SPR_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \SPR_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \SPR_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \SPR_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \SPR_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \SPR_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \SPR_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$14 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$16 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$17 + process $group_20 + assign \SPR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SPR_function_unit \SPR_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SPR_function_unit \SPR_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SPR_function_unit \SPR_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SPR_function_unit \SPR_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SPR_function_unit \SPR_dec_sub19_SPR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SPR_function_unit \SPR_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SPR_function_unit \SPR_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SPR_function_unit \SPR_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SPR_function_unit \SPR_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SPR_function_unit \SPR_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SPR_function_unit \SPR_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SPR_function_unit \SPR_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SPR_function_unit \SPR_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SPR_function_unit \SPR_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SPR_function_unit \SPR_function_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SPR_function_unit \SPR_function_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SPR_function_unit \SPR_function_unit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SPR_function_unit \SPR_function_unit$17 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$31 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$32 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$33 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$34 + process $group_21 + assign \SPR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SPR_internal_op \SPR_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SPR_internal_op \SPR_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SPR_internal_op \SPR_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SPR_internal_op \SPR_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SPR_internal_op \SPR_dec_sub19_SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SPR_internal_op \SPR_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SPR_internal_op \SPR_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SPR_internal_op \SPR_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SPR_internal_op \SPR_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SPR_internal_op \SPR_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SPR_internal_op \SPR_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SPR_internal_op \SPR_internal_op$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SPR_internal_op \SPR_internal_op$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SPR_internal_op \SPR_internal_op$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SPR_internal_op \SPR_internal_op$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SPR_internal_op \SPR_internal_op$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SPR_internal_op \SPR_internal_op$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SPR_internal_op \SPR_internal_op$34 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$35 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$36 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$37 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$38 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$39 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$40 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$41 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$42 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$43 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$44 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$45 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$46 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$47 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$48 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$49 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$50 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$51 + process $group_22 + assign \SPR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SPR_cr_in \SPR_cr_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SPR_cr_in \SPR_cr_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SPR_cr_in \SPR_cr_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SPR_cr_in \SPR_cr_in$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SPR_cr_in \SPR_dec_sub19_SPR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SPR_cr_in \SPR_cr_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SPR_cr_in \SPR_cr_in$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SPR_cr_in \SPR_cr_in$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SPR_cr_in \SPR_cr_in$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SPR_cr_in \SPR_cr_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SPR_cr_in \SPR_cr_in$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SPR_cr_in \SPR_cr_in$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SPR_cr_in \SPR_cr_in$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SPR_cr_in \SPR_cr_in$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SPR_cr_in \SPR_cr_in$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SPR_cr_in \SPR_cr_in$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SPR_cr_in \SPR_cr_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SPR_cr_in \SPR_cr_in$51 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$52 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$53 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$54 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$55 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$56 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$57 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$58 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$59 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$60 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$61 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$62 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$63 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$64 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$65 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$66 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$67 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$68 + process $group_23 + assign \SPR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SPR_cr_out \SPR_cr_out$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SPR_cr_out \SPR_cr_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SPR_cr_out \SPR_cr_out$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SPR_cr_out \SPR_cr_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SPR_cr_out \SPR_dec_sub19_SPR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SPR_cr_out \SPR_cr_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SPR_cr_out \SPR_cr_out$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SPR_cr_out \SPR_cr_out$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SPR_cr_out \SPR_cr_out$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SPR_cr_out \SPR_cr_out$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SPR_cr_out \SPR_cr_out$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SPR_cr_out \SPR_cr_out$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SPR_cr_out \SPR_cr_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SPR_cr_out \SPR_cr_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SPR_cr_out \SPR_cr_out$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SPR_cr_out \SPR_cr_out$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SPR_cr_out \SPR_cr_out$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SPR_cr_out \SPR_cr_out$68 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$69 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$70 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$71 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$72 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$73 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$74 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$75 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$76 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$77 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$78 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$79 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$80 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$81 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$82 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$83 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$84 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$85 + process $group_24 + assign \SPR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SPR_rc_sel \SPR_rc_sel$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SPR_rc_sel \SPR_rc_sel$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SPR_rc_sel \SPR_rc_sel$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SPR_rc_sel \SPR_rc_sel$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SPR_rc_sel \SPR_dec_sub19_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SPR_rc_sel \SPR_rc_sel$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SPR_rc_sel \SPR_rc_sel$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SPR_rc_sel \SPR_rc_sel$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SPR_rc_sel \SPR_rc_sel$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SPR_rc_sel \SPR_rc_sel$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SPR_rc_sel \SPR_rc_sel$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SPR_rc_sel \SPR_rc_sel$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SPR_rc_sel \SPR_rc_sel$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SPR_rc_sel \SPR_rc_sel$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SPR_rc_sel \SPR_rc_sel$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SPR_rc_sel \SPR_rc_sel$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SPR_rc_sel \SPR_rc_sel$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SPR_rc_sel \SPR_rc_sel$85 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$102 + process $group_25 + assign \SPR_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SPR_is_32b \SPR_is_32b$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SPR_is_32b \SPR_is_32b$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SPR_is_32b \SPR_is_32b$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SPR_is_32b \SPR_is_32b$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SPR_is_32b \SPR_dec_sub19_SPR_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SPR_is_32b \SPR_is_32b$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SPR_is_32b \SPR_is_32b$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SPR_is_32b \SPR_is_32b$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SPR_is_32b \SPR_is_32b$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SPR_is_32b \SPR_is_32b$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SPR_is_32b \SPR_is_32b$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SPR_is_32b \SPR_is_32b$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SPR_is_32b \SPR_is_32b$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SPR_is_32b \SPR_is_32b$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SPR_is_32b \SPR_is_32b$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SPR_is_32b \SPR_is_32b$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SPR_is_32b \SPR_is_32b$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SPR_is_32b \SPR_is_32b$102 + end + sync init + end + connect \SPR_function_unit$1 11'00000000000 + connect \SPR_function_unit$2 11'00000000000 + connect \SPR_function_unit$3 11'00000000000 + connect \SPR_function_unit$4 11'00000000000 + connect \SPR_function_unit$5 11'00000000000 + connect \SPR_function_unit$6 11'00000000000 + connect \SPR_function_unit$7 11'00000000000 + connect \SPR_function_unit$8 11'00000000000 + connect \SPR_function_unit$9 11'00000000000 + connect \SPR_function_unit$10 11'00000000000 + connect \SPR_function_unit$11 11'00000000000 + connect \SPR_function_unit$12 11'00000000000 + connect \SPR_function_unit$13 11'00000000000 + connect \SPR_function_unit$14 11'00000000000 + connect \SPR_function_unit$15 11'00000000000 + connect \SPR_function_unit$16 11'00000000000 + connect \SPR_function_unit$17 11'00000000000 + connect \SPR_internal_op$18 7'0000000 + connect \SPR_internal_op$19 7'0000000 + connect \SPR_internal_op$20 7'0000000 + connect \SPR_internal_op$21 7'0000000 + connect \SPR_internal_op$22 7'0000000 + connect \SPR_internal_op$23 7'0000000 + connect \SPR_internal_op$24 7'0000000 + connect \SPR_internal_op$25 7'0000000 + connect \SPR_internal_op$26 7'0000000 + connect \SPR_internal_op$27 7'0000000 + connect \SPR_internal_op$28 7'0000000 + connect \SPR_internal_op$29 7'0000000 + connect \SPR_internal_op$30 7'0000000 + connect \SPR_internal_op$31 7'0000000 + connect \SPR_internal_op$32 7'0000000 + connect \SPR_internal_op$33 7'0000000 + connect \SPR_internal_op$34 7'0000000 + connect \SPR_cr_in$35 3'000 + connect \SPR_cr_in$36 3'000 + connect \SPR_cr_in$37 3'000 + connect \SPR_cr_in$38 3'000 + connect \SPR_cr_in$39 3'000 + connect \SPR_cr_in$40 3'000 + connect \SPR_cr_in$41 3'000 + connect \SPR_cr_in$42 3'000 + connect \SPR_cr_in$43 3'000 + connect \SPR_cr_in$44 3'000 + connect \SPR_cr_in$45 3'000 + connect \SPR_cr_in$46 3'000 + connect \SPR_cr_in$47 3'000 + connect \SPR_cr_in$48 3'000 + connect \SPR_cr_in$49 3'000 + connect \SPR_cr_in$50 3'000 + connect \SPR_cr_in$51 3'000 + connect \SPR_cr_out$52 3'000 + connect \SPR_cr_out$53 3'000 + connect \SPR_cr_out$54 3'000 + connect \SPR_cr_out$55 3'000 + connect \SPR_cr_out$56 3'000 + connect \SPR_cr_out$57 3'000 + connect \SPR_cr_out$58 3'000 + connect \SPR_cr_out$59 3'000 + connect \SPR_cr_out$60 3'000 + connect \SPR_cr_out$61 3'000 + connect \SPR_cr_out$62 3'000 + connect \SPR_cr_out$63 3'000 + connect \SPR_cr_out$64 3'000 + connect \SPR_cr_out$65 3'000 + connect \SPR_cr_out$66 3'000 + connect \SPR_cr_out$67 3'000 + connect \SPR_cr_out$68 3'000 + connect \SPR_rc_sel$69 2'00 + connect \SPR_rc_sel$70 2'00 + connect \SPR_rc_sel$71 2'00 + connect \SPR_rc_sel$72 2'00 + connect \SPR_rc_sel$73 2'00 + connect \SPR_rc_sel$74 2'00 + connect \SPR_rc_sel$75 2'00 + connect \SPR_rc_sel$76 2'00 + connect \SPR_rc_sel$77 2'00 + connect \SPR_rc_sel$78 2'00 + connect \SPR_rc_sel$79 2'00 + connect \SPR_rc_sel$80 2'00 + connect \SPR_rc_sel$81 2'00 + connect \SPR_rc_sel$82 2'00 + connect \SPR_rc_sel$83 2'00 + connect \SPR_rc_sel$84 2'00 + connect \SPR_rc_sel$85 2'00 + connect \SPR_is_32b$86 1'0 + connect \SPR_is_32b$87 1'0 + connect \SPR_is_32b$88 1'0 + connect \SPR_is_32b$89 1'0 + connect \SPR_is_32b$90 1'0 + connect \SPR_is_32b$91 1'0 + connect \SPR_is_32b$92 1'0 + connect \SPR_is_32b$93 1'0 + connect \SPR_is_32b$94 1'0 + connect \SPR_is_32b$95 1'0 + connect \SPR_is_32b$96 1'0 + connect \SPR_is_32b$97 1'0 + connect \SPR_is_32b$98 1'0 + connect \SPR_is_32b$99 1'0 + connect \SPR_is_32b$100 1'0 + connect \SPR_is_32b$101 1'0 + connect \SPR_is_32b$102 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec58" +module \SPR_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec62" +module \SPR_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec" +module \dec$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \SPR_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SPR_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \SPR_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \SPR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \SPR_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 9 \SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 10 \SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 11 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 12 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 13 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 14 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 15 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 16 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 17 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 18 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 19 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec19_opcode_in + cell \SPR_dec19 \SPR_dec19 + connect \opcode_in \SPR_dec19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec30_opcode_in + cell \SPR_dec30 \SPR_dec30 + connect \opcode_in \SPR_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_dec31_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_dec31_SPR_internal_op + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_dec31_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_dec31_SPR_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_dec31_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_dec31_SPR_is_32b + cell \SPR_dec31 \SPR_dec31 + connect \opcode_in \SPR_dec31_opcode_in + connect \SPR_function_unit \SPR_dec31_SPR_function_unit + connect \SPR_internal_op \SPR_dec31_SPR_internal_op + connect \SPR_cr_in \SPR_dec31_SPR_cr_in + connect \SPR_cr_out \SPR_dec31_SPR_cr_out + connect \SPR_rc_sel \SPR_dec31_SPR_rc_sel + connect \SPR_is_32b \SPR_dec31_SPR_is_32b + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec58_opcode_in + cell \SPR_dec58 \SPR_dec58 + connect \opcode_in \SPR_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SPR_dec62_opcode_in + cell \SPR_dec62 \SPR_dec62 + connect \opcode_in \SPR_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \SPR_dec19_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \SPR_dec30_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \SPR_dec31_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \SPR_dec58_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \SPR_dec62_opcode_in 32'00000000000000000000000000000000 + assign \SPR_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SPR_function_unit$4 + process $group_6 + assign \SPR_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SPR_function_unit \SPR_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SPR_function_unit \SPR_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SPR_function_unit \SPR_dec31_SPR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SPR_function_unit \SPR_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SPR_function_unit \SPR_function_unit$4 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SPR_internal_op$8 + process $group_7 + assign \SPR_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SPR_internal_op \SPR_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SPR_internal_op \SPR_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SPR_internal_op \SPR_dec31_SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SPR_internal_op \SPR_internal_op$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SPR_internal_op \SPR_internal_op$8 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$9 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$10 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$11 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_in$12 + process $group_8 + assign \SPR_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SPR_cr_in \SPR_cr_in$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SPR_cr_in \SPR_cr_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SPR_cr_in \SPR_dec31_SPR_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SPR_cr_in \SPR_cr_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SPR_cr_in \SPR_cr_in$12 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$13 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$14 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$15 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SPR_cr_out$16 + process $group_9 + assign \SPR_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SPR_cr_out \SPR_cr_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SPR_cr_out \SPR_cr_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SPR_cr_out \SPR_dec31_SPR_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SPR_cr_out \SPR_cr_out$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SPR_cr_out \SPR_cr_out$16 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$17 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$18 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$19 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SPR_rc_sel$20 + process $group_10 + assign \SPR_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SPR_rc_sel \SPR_rc_sel$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SPR_rc_sel \SPR_rc_sel$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SPR_rc_sel \SPR_dec31_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SPR_rc_sel \SPR_rc_sel$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SPR_rc_sel \SPR_rc_sel$20 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SPR_is_32b$24 + process $group_11 + assign \SPR_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SPR_is_32b \SPR_is_32b$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SPR_is_32b \SPR_is_32b$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SPR_is_32b \SPR_dec31_SPR_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SPR_is_32b \SPR_is_32b$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SPR_is_32b \SPR_is_32b$24 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$25 + process $group_12 + assign \opcode_switch$25 32'00000000000000000000000000000000 + assign \opcode_switch$25 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $27 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $26 + end + process $group_13 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $26 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_RS + process $group_14 + assign \SPR_RS 5'00000 + assign \SPR_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_RT + process $group_15 + assign \SPR_RT 5'00000 + assign \SPR_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_RA + process $group_16 + assign \SPR_RA 5'00000 + assign \SPR_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_RB + process $group_17 + assign \SPR_RB 5'00000 + assign \SPR_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \SPR_SI + process $group_18 + assign \SPR_SI 16'0000000000000000 + assign \SPR_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \SPR_UI + process $group_19 + assign \SPR_UI 16'0000000000000000 + assign \SPR_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \SPR_L + process $group_20 + assign \SPR_L 1'0 + assign \SPR_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_SH32 + process $group_21 + assign \SPR_SH32 5'00000 + assign \SPR_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \SPR_sh + process $group_22 + assign \SPR_sh 6'000000 + assign \SPR_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_MB32 + process $group_23 + assign \SPR_MB32 5'00000 + assign \SPR_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_ME32 + process $group_24 + assign \SPR_ME32 5'00000 + assign \SPR_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \SPR_LI + process $group_25 + assign \SPR_LI 24'000000000000000000000000 + assign \SPR_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \SPR_LK + process $group_26 + assign \SPR_LK 1'0 + assign \SPR_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \SPR_AA + process $group_27 + assign \SPR_AA 1'0 + assign \SPR_AA { \opcode_in [1] } + sync init + end + process $group_28 + assign \SPR_Rc 1'0 + assign \SPR_Rc { \opcode_in [0] } + sync init + end + process $group_29 + assign \SPR_OE 1'0 + assign \SPR_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \SPR_BD + process $group_30 + assign \SPR_BD 14'00000000000000 + assign \SPR_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \SPR_BF + process $group_31 + assign \SPR_BF 3'000 + assign \SPR_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \SPR_CR + process $group_32 + assign \SPR_CR 10'0000000000 + assign \SPR_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_33 + assign \SPR_BB 5'00000 + assign \SPR_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_34 + assign \SPR_BA 5'00000 + assign \SPR_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_35 + assign \SPR_BT 5'00000 + assign \SPR_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_36 + assign \SPR_FXM 8'00000000 + assign \SPR_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_BO + process $group_37 + assign \SPR_BO 5'00000 + assign \SPR_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_38 + assign \SPR_BI 5'00000 + assign \SPR_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \SPR_BH + process $group_39 + assign \SPR_BH 2'00 + assign \SPR_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \SPR_D + process $group_40 + assign \SPR_D 16'0000000000000000 + assign \SPR_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \SPR_DS + process $group_41 + assign \SPR_DS 14'00000000000000 + assign \SPR_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_TO + process $group_42 + assign \SPR_TO 5'00000 + assign \SPR_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_43 + assign \SPR_BC 5'00000 + assign \SPR_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_SH + process $group_44 + assign \SPR_SH 5'00000 + assign \SPR_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_ME + process $group_45 + assign \SPR_ME 5'00000 + assign \SPR_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SPR_MB + process $group_46 + assign \SPR_MB 5'00000 + assign \SPR_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \SPR_SPR + process $group_47 + assign \SPR_SPR 10'0000000000 + assign \SPR_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_48 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_49 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_50 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_51 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_52 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_53 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_54 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_55 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_56 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_57 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_58 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_59 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_60 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_61 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_62 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_63 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_64 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_65 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_66 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_67 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_68 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_69 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_70 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_71 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_72 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_73 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_74 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_75 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_76 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_77 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_78 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_79 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_80 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_81 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_82 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_83 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_84 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_85 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_86 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_87 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_88 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_89 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_90 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_91 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_92 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_93 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_94 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_95 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_96 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_97 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_98 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_99 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_100 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_101 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_102 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_103 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_104 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_105 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_106 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_107 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_108 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_109 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_110 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_111 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_112 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_113 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_114 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_115 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_116 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_117 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_118 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_119 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_120 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_121 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_122 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_123 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_124 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_125 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_126 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_127 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_128 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_129 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_130 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_131 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_132 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_133 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_134 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_135 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_136 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_137 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_138 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_139 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_140 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_141 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_142 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_143 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_144 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_145 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_146 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_147 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_148 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_149 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_150 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_151 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_152 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_153 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_154 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_155 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_156 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_157 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_158 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_159 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_160 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_161 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_162 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_163 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_164 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_165 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_166 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_167 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_168 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_169 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_170 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_171 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_172 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_173 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_174 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_175 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_176 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_177 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_178 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_179 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_180 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_181 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_182 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_183 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_184 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_185 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_186 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_187 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_188 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_189 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_190 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_191 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_192 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_193 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_194 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_195 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_196 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_197 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_198 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_199 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_200 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_201 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_202 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_203 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_204 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_205 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_206 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_207 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_208 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_209 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_210 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_211 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_212 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_213 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_214 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_215 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_216 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_217 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_218 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_219 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_220 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_221 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_222 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_223 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_224 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_225 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_226 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_227 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_228 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_229 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_230 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_231 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_232 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_233 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_234 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_235 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_236 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_237 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_238 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_239 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_240 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_241 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_242 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_243 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_244 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_245 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_246 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_247 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_248 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_249 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_250 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_251 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_252 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_253 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_254 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_255 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_256 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_257 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_258 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_259 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_260 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_261 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_262 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_263 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_264 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_265 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_266 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_267 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_268 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_269 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_270 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_271 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_272 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_273 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_274 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_275 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_276 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_277 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_278 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_279 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_280 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_281 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_282 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_283 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_284 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_285 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_286 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_287 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_288 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_289 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_290 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_291 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_292 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_293 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_294 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_295 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_296 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_297 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_298 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_299 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_300 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_301 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_302 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_303 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_304 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_305 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_306 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_307 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_308 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_309 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_310 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_311 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_312 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_313 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_314 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_315 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_316 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_317 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_318 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_319 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_320 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_321 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_322 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_323 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_324 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_325 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_326 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_327 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_328 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_329 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_330 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_331 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_332 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_333 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_334 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_335 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_336 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_337 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_338 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_339 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \SPR_function_unit$1 11'00000000000 + connect \SPR_function_unit$2 11'00000000000 + connect \SPR_function_unit$3 11'00000000000 + connect \SPR_function_unit$4 11'00000000000 + connect \SPR_internal_op$5 7'0000000 + connect \SPR_internal_op$6 7'0000000 + connect \SPR_internal_op$7 7'0000000 + connect \SPR_internal_op$8 7'0000000 + connect \SPR_cr_in$9 3'000 + connect \SPR_cr_in$10 3'000 + connect \SPR_cr_in$11 3'000 + connect \SPR_cr_in$12 3'000 + connect \SPR_cr_out$13 3'000 + connect \SPR_cr_out$14 3'000 + connect \SPR_cr_out$15 3'000 + connect \SPR_cr_out$16 3'000 + connect \SPR_rc_sel$17 2'00 + connect \SPR_rc_sel$18 2'00 + connect \SPR_rc_sel$19 2'00 + connect \SPR_rc_sel$20 2'00 + connect \SPR_is_32b$21 1'0 + connect \SPR_is_32b$22 1'0 + connect \SPR_is_32b$23 1'0 + connect \SPR_is_32b$24 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_rc" +module \dec_rc$162 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 2 \SPR_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rc_ok + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_oe" +module \dec_oe$163 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 2 \SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \SPR_OE + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe_ok + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in.ppick" +module \ppick$165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in" +module \dec_cr_in$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$165 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \SPR_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \SPR_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \SPR_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \SPR_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \SPR_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out.ppick" +module \ppick$167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out" +module \dec_cr_out$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 4 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$167 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \SPR_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR" +module \dec_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR_SPR__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR_SPR__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_SPR_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_SPR_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_SPR_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_SPR_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$161 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \SPR_rc_sel \dec_SPR_rc_sel + connect \SPR_cr_in \dec_SPR_cr_in + connect \SPR_cr_out \dec_SPR_cr_out + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_function_unit \dec_SPR_function_unit + connect \SPR_is_32b \dec_SPR_is_32b + connect \SPR_Rc \dec_SPR_Rc + connect \SPR_OE \dec_SPR_OE + connect \SPR_BB \dec_SPR_BB + connect \SPR_BA \dec_SPR_BA + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_BI \dec_SPR_BI + connect \SPR_BC \dec_SPR_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + cell \dec_rc$162 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \SPR_Rc \dec_SPR_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + cell \dec_oe$163 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_OE \dec_SPR_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$164 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_BB \dec_SPR_BB + connect \SPR_BA \dec_SPR_BA + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_BI \dec_SPR_BI + connect \SPR_BC \dec_SPR_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + cell \dec_cr_out$166 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_FXM \dec_SPR_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + process $group_0 + assign \SPR_SPR__insn 32'00000000000000000000000000000000 + assign \SPR_SPR__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_SPR_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_SPR_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_SPR_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_SPR_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \SPR_SPR__insn_type 7'0000000 + assign \SPR_SPR__insn_type \dec_SPR_internal_op + sync init + end + process $group_11 + assign \SPR_SPR__fn_unit 11'00000000000 + assign \SPR_SPR__fn_unit \dec_SPR_function_unit + sync init + end + process $group_12 + assign \SPR_SPR__is_32bit 1'0 + assign \SPR_SPR__is_32bit \dec_SPR_is_32b + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec19" +module \DIV_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_1 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec30" +module \DIV_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub10" +module \DIV_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub28" +module \DIV_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub0" +module \DIV_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub26" +module \DIV_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub19" +module \DIV_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub22" +module \DIV_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub9" +module \DIV_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \DIV_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \DIV_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \DIV_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \DIV_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \DIV_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \DIV_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_function_unit 11'01000000000 + end + sync init + end + process $group_2 + assign \DIV_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_internal_op 7'0101111 + end + sync init + end + process $group_3 + assign \DIV_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_in1_sel 3'001 + end + sync init + end + process $group_4 + assign \DIV_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cr_in 3'000 + end + sync init + end + process $group_6 + assign \DIV_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cr_out 3'000 + end + sync init + end + process $group_7 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_ldst_len 4'0000 + end + sync init + end + process $group_8 + assign \DIV_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_rc_sel 2'00 + end + sync init + end + process $group_9 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cry_in 2'00 + end + sync init + end + process $group_10 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_inv_a 1'0 + end + sync init + end + process $group_11 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_inv_out 1'0 + end + sync init + end + process $group_12 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cry_out 1'0 + end + sync init + end + process $group_13 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_is_32b 1'0 + end + sync init + end + process $group_14 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_sgn 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub11" +module \DIV_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \DIV_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \DIV_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \DIV_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \DIV_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \DIV_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \DIV_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_function_unit 11'01000000000 + end + sync init + end + process $group_2 + assign \DIV_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_internal_op 7'0101111 + end + sync init + end + process $group_3 + assign \DIV_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_in1_sel 3'001 + end + sync init + end + process $group_4 + assign \DIV_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cr_in 3'000 + end + sync init + end + process $group_6 + assign \DIV_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cr_out 3'000 + end + sync init + end + process $group_7 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_ldst_len 4'0000 + end + sync init + end + process $group_8 + assign \DIV_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_rc_sel 2'00 + end + sync init + end + process $group_9 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cry_in 2'00 + end + sync init + end + process $group_10 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_inv_a 1'0 + end + sync init + end + process $group_11 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_inv_out 1'0 + end + sync init + end + process $group_12 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_cry_out 1'0 + end + sync init + end + process $group_13 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_is_32b 1'1 + end + sync init + end + process $group_14 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01110 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \DIV_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \DIV_sgn 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub27" +module \DIV_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub15" +module \DIV_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub20" +module \DIV_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub21" +module \DIV_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub23" +module \DIV_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub16" +module \DIV_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub18" +module \DIV_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub8" +module \DIV_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub24" +module \DIV_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub4" +module \DIV_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31" +module \DIV_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \DIV_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \DIV_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \DIV_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \DIV_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \DIV_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub10_opcode_in + cell \DIV_dec_sub10 \DIV_dec_sub10 + connect \opcode_in \DIV_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub28_opcode_in + cell \DIV_dec_sub28 \DIV_dec_sub28 + connect \opcode_in \DIV_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub0_opcode_in + cell \DIV_dec_sub0 \DIV_dec_sub0 + connect \opcode_in \DIV_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub26_opcode_in + cell \DIV_dec_sub26 \DIV_dec_sub26 + connect \opcode_in \DIV_dec_sub26_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub19_opcode_in + cell \DIV_dec_sub19 \DIV_dec_sub19 + connect \opcode_in \DIV_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub22_opcode_in + cell \DIV_dec_sub22 \DIV_dec_sub22 + connect \opcode_in \DIV_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_dec_sub9_DIV_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_dec_sub9_DIV_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec_sub9_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_dec_sub9_DIV_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec_sub9_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec_sub9_DIV_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_dec_sub9_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_dec_sub9_DIV_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_dec_sub9_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub9_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub9_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub9_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub9_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub9_DIV_sgn + cell \DIV_dec_sub9 \DIV_dec_sub9 + connect \opcode_in \DIV_dec_sub9_opcode_in + connect \DIV_function_unit \DIV_dec_sub9_DIV_function_unit + connect \DIV_internal_op \DIV_dec_sub9_DIV_internal_op + connect \DIV_in1_sel \DIV_dec_sub9_DIV_in1_sel + connect \DIV_in2_sel \DIV_dec_sub9_DIV_in2_sel + connect \DIV_cr_in \DIV_dec_sub9_DIV_cr_in + connect \DIV_cr_out \DIV_dec_sub9_DIV_cr_out + connect \DIV_ldst_len \DIV_dec_sub9_DIV_ldst_len + connect \DIV_rc_sel \DIV_dec_sub9_DIV_rc_sel + connect \DIV_cry_in \DIV_dec_sub9_DIV_cry_in + connect \DIV_inv_a \DIV_dec_sub9_DIV_inv_a + connect \DIV_inv_out \DIV_dec_sub9_DIV_inv_out + connect \DIV_cry_out \DIV_dec_sub9_DIV_cry_out + connect \DIV_is_32b \DIV_dec_sub9_DIV_is_32b + connect \DIV_sgn \DIV_dec_sub9_DIV_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub11_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_dec_sub11_DIV_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_dec_sub11_DIV_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec_sub11_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_dec_sub11_DIV_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec_sub11_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec_sub11_DIV_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_dec_sub11_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_dec_sub11_DIV_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_dec_sub11_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub11_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub11_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub11_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub11_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec_sub11_DIV_sgn + cell \DIV_dec_sub11 \DIV_dec_sub11 + connect \opcode_in \DIV_dec_sub11_opcode_in + connect \DIV_function_unit \DIV_dec_sub11_DIV_function_unit + connect \DIV_internal_op \DIV_dec_sub11_DIV_internal_op + connect \DIV_in1_sel \DIV_dec_sub11_DIV_in1_sel + connect \DIV_in2_sel \DIV_dec_sub11_DIV_in2_sel + connect \DIV_cr_in \DIV_dec_sub11_DIV_cr_in + connect \DIV_cr_out \DIV_dec_sub11_DIV_cr_out + connect \DIV_ldst_len \DIV_dec_sub11_DIV_ldst_len + connect \DIV_rc_sel \DIV_dec_sub11_DIV_rc_sel + connect \DIV_cry_in \DIV_dec_sub11_DIV_cry_in + connect \DIV_inv_a \DIV_dec_sub11_DIV_inv_a + connect \DIV_inv_out \DIV_dec_sub11_DIV_inv_out + connect \DIV_cry_out \DIV_dec_sub11_DIV_cry_out + connect \DIV_is_32b \DIV_dec_sub11_DIV_is_32b + connect \DIV_sgn \DIV_dec_sub11_DIV_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub27_opcode_in + cell \DIV_dec_sub27 \DIV_dec_sub27 + connect \opcode_in \DIV_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub15_opcode_in + cell \DIV_dec_sub15 \DIV_dec_sub15 + connect \opcode_in \DIV_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub20_opcode_in + cell \DIV_dec_sub20 \DIV_dec_sub20 + connect \opcode_in \DIV_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub21_opcode_in + cell \DIV_dec_sub21 \DIV_dec_sub21 + connect \opcode_in \DIV_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub23_opcode_in + cell \DIV_dec_sub23 \DIV_dec_sub23 + connect \opcode_in \DIV_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub16_opcode_in + cell \DIV_dec_sub16 \DIV_dec_sub16 + connect \opcode_in \DIV_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub18_opcode_in + cell \DIV_dec_sub18 \DIV_dec_sub18 + connect \opcode_in \DIV_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub8_opcode_in + cell \DIV_dec_sub8 \DIV_dec_sub8 + connect \opcode_in \DIV_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub24_opcode_in + cell \DIV_dec_sub24 \DIV_dec_sub24 + connect \opcode_in \DIV_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec_sub4_opcode_in + cell \DIV_dec_sub4 \DIV_dec_sub4 + connect \opcode_in \DIV_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \DIV_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \DIV_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \DIV_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \DIV_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \DIV_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \DIV_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \DIV_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \DIV_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \DIV_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \DIV_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \DIV_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \DIV_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \DIV_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \DIV_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \DIV_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \DIV_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \DIV_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \DIV_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$14 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$16 + process $group_20 + assign \DIV_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_function_unit \DIV_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_function_unit \DIV_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_function_unit \DIV_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_function_unit \DIV_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_function_unit \DIV_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_function_unit \DIV_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_function_unit \DIV_dec_sub9_DIV_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_function_unit \DIV_dec_sub11_DIV_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_function_unit \DIV_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_function_unit \DIV_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_function_unit \DIV_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_function_unit \DIV_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_function_unit \DIV_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_function_unit \DIV_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_function_unit \DIV_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_function_unit \DIV_function_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_function_unit \DIV_function_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_function_unit \DIV_function_unit$16 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$31 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$32 + process $group_21 + assign \DIV_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_internal_op \DIV_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_internal_op \DIV_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_internal_op \DIV_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_internal_op \DIV_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_internal_op \DIV_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_internal_op \DIV_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_internal_op \DIV_dec_sub9_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_internal_op \DIV_dec_sub11_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_internal_op \DIV_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_internal_op \DIV_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_internal_op \DIV_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_internal_op \DIV_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_internal_op \DIV_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_internal_op \DIV_internal_op$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_internal_op \DIV_internal_op$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_internal_op \DIV_internal_op$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_internal_op \DIV_internal_op$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_internal_op \DIV_internal_op$32 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$33 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$34 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$35 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$36 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$37 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$38 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$39 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$40 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$41 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$42 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$43 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$44 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$45 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$46 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$47 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$48 + process $group_22 + assign \DIV_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_in1_sel \DIV_in1_sel$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_in1_sel \DIV_in1_sel$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_in1_sel \DIV_in1_sel$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_in1_sel \DIV_in1_sel$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_in1_sel \DIV_in1_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_in1_sel \DIV_in1_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_in1_sel \DIV_dec_sub9_DIV_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_in1_sel \DIV_dec_sub11_DIV_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_in1_sel \DIV_in1_sel$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_in1_sel \DIV_in1_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_in1_sel \DIV_in1_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_in1_sel \DIV_in1_sel$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_in1_sel \DIV_in1_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_in1_sel \DIV_in1_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_in1_sel \DIV_in1_sel$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_in1_sel \DIV_in1_sel$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_in1_sel \DIV_in1_sel$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_in1_sel \DIV_in1_sel$48 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$49 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$50 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$51 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$52 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$53 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$54 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$55 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$56 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$57 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$58 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$59 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$60 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$61 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$62 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$63 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$64 + process $group_23 + assign \DIV_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_in2_sel \DIV_in2_sel$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_in2_sel \DIV_in2_sel$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_in2_sel \DIV_in2_sel$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_in2_sel \DIV_in2_sel$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_in2_sel \DIV_in2_sel$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_in2_sel \DIV_in2_sel$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_in2_sel \DIV_dec_sub9_DIV_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_in2_sel \DIV_dec_sub11_DIV_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_in2_sel \DIV_in2_sel$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_in2_sel \DIV_in2_sel$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_in2_sel \DIV_in2_sel$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_in2_sel \DIV_in2_sel$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_in2_sel \DIV_in2_sel$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_in2_sel \DIV_in2_sel$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_in2_sel \DIV_in2_sel$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_in2_sel \DIV_in2_sel$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_in2_sel \DIV_in2_sel$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_in2_sel \DIV_in2_sel$64 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$65 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$66 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$67 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$68 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$69 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$70 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$71 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$72 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$73 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$74 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$75 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$76 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$77 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$78 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$79 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$80 + process $group_24 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_cr_in \DIV_cr_in$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_cr_in \DIV_cr_in$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_cr_in \DIV_cr_in$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_cr_in \DIV_cr_in$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_cr_in \DIV_cr_in$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_cr_in \DIV_cr_in$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_cr_in \DIV_dec_sub9_DIV_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_cr_in \DIV_dec_sub11_DIV_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_cr_in \DIV_cr_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_cr_in \DIV_cr_in$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_cr_in \DIV_cr_in$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_cr_in \DIV_cr_in$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_cr_in \DIV_cr_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_cr_in \DIV_cr_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_cr_in \DIV_cr_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_cr_in \DIV_cr_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_cr_in \DIV_cr_in$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_cr_in \DIV_cr_in$80 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$81 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$82 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$83 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$84 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$85 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$86 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$87 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$88 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$89 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$90 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$91 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$92 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$93 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$94 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$95 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$96 + process $group_25 + assign \DIV_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_cr_out \DIV_cr_out$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_cr_out \DIV_cr_out$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_cr_out \DIV_cr_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_cr_out \DIV_cr_out$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_cr_out \DIV_cr_out$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_cr_out \DIV_cr_out$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_cr_out \DIV_dec_sub9_DIV_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_cr_out \DIV_dec_sub11_DIV_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_cr_out \DIV_cr_out$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_cr_out \DIV_cr_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_cr_out \DIV_cr_out$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_cr_out \DIV_cr_out$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_cr_out \DIV_cr_out$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_cr_out \DIV_cr_out$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_cr_out \DIV_cr_out$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_cr_out \DIV_cr_out$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_cr_out \DIV_cr_out$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_cr_out \DIV_cr_out$96 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$97 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$98 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$99 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$100 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$101 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$102 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$103 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$104 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$105 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$106 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$107 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$108 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$109 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$110 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$111 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$112 + process $group_26 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_ldst_len \DIV_ldst_len$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_ldst_len \DIV_ldst_len$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_ldst_len \DIV_ldst_len$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_ldst_len \DIV_ldst_len$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_ldst_len \DIV_ldst_len$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_ldst_len \DIV_ldst_len$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_ldst_len \DIV_dec_sub9_DIV_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_ldst_len \DIV_dec_sub11_DIV_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_ldst_len \DIV_ldst_len$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_ldst_len \DIV_ldst_len$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_ldst_len \DIV_ldst_len$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_ldst_len \DIV_ldst_len$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_ldst_len \DIV_ldst_len$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_ldst_len \DIV_ldst_len$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_ldst_len \DIV_ldst_len$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_ldst_len \DIV_ldst_len$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_ldst_len \DIV_ldst_len$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_ldst_len \DIV_ldst_len$112 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$113 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$114 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$115 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$116 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$117 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$118 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$119 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$120 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$121 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$122 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$123 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$124 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$125 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$126 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$127 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$128 + process $group_27 + assign \DIV_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_rc_sel \DIV_rc_sel$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_rc_sel \DIV_rc_sel$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_rc_sel \DIV_rc_sel$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_rc_sel \DIV_rc_sel$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_rc_sel \DIV_rc_sel$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_rc_sel \DIV_rc_sel$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_rc_sel \DIV_dec_sub9_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_rc_sel \DIV_dec_sub11_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_rc_sel \DIV_rc_sel$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_rc_sel \DIV_rc_sel$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_rc_sel \DIV_rc_sel$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_rc_sel \DIV_rc_sel$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_rc_sel \DIV_rc_sel$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_rc_sel \DIV_rc_sel$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_rc_sel \DIV_rc_sel$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_rc_sel \DIV_rc_sel$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_rc_sel \DIV_rc_sel$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_rc_sel \DIV_rc_sel$128 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$129 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$130 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$131 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$132 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$133 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$134 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$135 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$136 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$137 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$138 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$139 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$140 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$141 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$142 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$144 + process $group_28 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_cry_in \DIV_cry_in$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_cry_in \DIV_cry_in$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_cry_in \DIV_cry_in$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_cry_in \DIV_cry_in$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_cry_in \DIV_cry_in$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_cry_in \DIV_cry_in$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_cry_in \DIV_dec_sub9_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_cry_in \DIV_dec_sub11_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_cry_in \DIV_cry_in$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_cry_in \DIV_cry_in$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_cry_in \DIV_cry_in$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_cry_in \DIV_cry_in$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_cry_in \DIV_cry_in$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_cry_in \DIV_cry_in$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_cry_in \DIV_cry_in$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_cry_in \DIV_cry_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_cry_in \DIV_cry_in$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_cry_in \DIV_cry_in$144 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$160 + process $group_29 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_inv_a \DIV_inv_a$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_inv_a \DIV_inv_a$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_inv_a \DIV_inv_a$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_inv_a \DIV_inv_a$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_inv_a \DIV_inv_a$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_inv_a \DIV_inv_a$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_inv_a \DIV_dec_sub9_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_inv_a \DIV_dec_sub11_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_inv_a \DIV_inv_a$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_inv_a \DIV_inv_a$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_inv_a \DIV_inv_a$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_inv_a \DIV_inv_a$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_inv_a \DIV_inv_a$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_inv_a \DIV_inv_a$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_inv_a \DIV_inv_a$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_inv_a \DIV_inv_a$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_inv_a \DIV_inv_a$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_inv_a \DIV_inv_a$160 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$176 + process $group_30 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_inv_out \DIV_inv_out$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_inv_out \DIV_inv_out$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_inv_out \DIV_inv_out$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_inv_out \DIV_inv_out$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_inv_out \DIV_inv_out$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_inv_out \DIV_inv_out$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_inv_out \DIV_dec_sub9_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_inv_out \DIV_dec_sub11_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_inv_out \DIV_inv_out$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_inv_out \DIV_inv_out$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_inv_out \DIV_inv_out$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_inv_out \DIV_inv_out$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_inv_out \DIV_inv_out$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_inv_out \DIV_inv_out$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_inv_out \DIV_inv_out$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_inv_out \DIV_inv_out$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_inv_out \DIV_inv_out$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_inv_out \DIV_inv_out$176 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$192 + process $group_31 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_cry_out \DIV_cry_out$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_cry_out \DIV_cry_out$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_cry_out \DIV_cry_out$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_cry_out \DIV_cry_out$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_cry_out \DIV_cry_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_cry_out \DIV_cry_out$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_cry_out \DIV_dec_sub9_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_cry_out \DIV_dec_sub11_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_cry_out \DIV_cry_out$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_cry_out \DIV_cry_out$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_cry_out \DIV_cry_out$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_cry_out \DIV_cry_out$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_cry_out \DIV_cry_out$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_cry_out \DIV_cry_out$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_cry_out \DIV_cry_out$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_cry_out \DIV_cry_out$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_cry_out \DIV_cry_out$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_cry_out \DIV_cry_out$192 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$208 + process $group_32 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_is_32b \DIV_is_32b$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_is_32b \DIV_is_32b$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_is_32b \DIV_is_32b$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_is_32b \DIV_is_32b$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_is_32b \DIV_is_32b$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_is_32b \DIV_is_32b$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_is_32b \DIV_dec_sub9_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_is_32b \DIV_dec_sub11_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_is_32b \DIV_is_32b$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_is_32b \DIV_is_32b$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_is_32b \DIV_is_32b$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_is_32b \DIV_is_32b$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_is_32b \DIV_is_32b$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_is_32b \DIV_is_32b$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_is_32b \DIV_is_32b$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_is_32b \DIV_is_32b$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_is_32b \DIV_is_32b$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_is_32b \DIV_is_32b$208 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$224 + process $group_33 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \DIV_sgn \DIV_sgn$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \DIV_sgn \DIV_sgn$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \DIV_sgn \DIV_sgn$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \DIV_sgn \DIV_sgn$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \DIV_sgn \DIV_sgn$213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \DIV_sgn \DIV_sgn$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \DIV_sgn \DIV_dec_sub9_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \DIV_sgn \DIV_dec_sub11_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \DIV_sgn \DIV_sgn$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \DIV_sgn \DIV_sgn$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \DIV_sgn \DIV_sgn$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \DIV_sgn \DIV_sgn$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \DIV_sgn \DIV_sgn$219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \DIV_sgn \DIV_sgn$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \DIV_sgn \DIV_sgn$221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \DIV_sgn \DIV_sgn$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \DIV_sgn \DIV_sgn$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \DIV_sgn \DIV_sgn$224 + end + sync init + end + connect \DIV_function_unit$1 11'00000000000 + connect \DIV_function_unit$2 11'00000000000 + connect \DIV_function_unit$3 11'00000000000 + connect \DIV_function_unit$4 11'00000000000 + connect \DIV_function_unit$5 11'00000000000 + connect \DIV_function_unit$6 11'00000000000 + connect \DIV_function_unit$7 11'00000000000 + connect \DIV_function_unit$8 11'00000000000 + connect \DIV_function_unit$9 11'00000000000 + connect \DIV_function_unit$10 11'00000000000 + connect \DIV_function_unit$11 11'00000000000 + connect \DIV_function_unit$12 11'00000000000 + connect \DIV_function_unit$13 11'00000000000 + connect \DIV_function_unit$14 11'00000000000 + connect \DIV_function_unit$15 11'00000000000 + connect \DIV_function_unit$16 11'00000000000 + connect \DIV_internal_op$17 7'0000000 + connect \DIV_internal_op$18 7'0000000 + connect \DIV_internal_op$19 7'0000000 + connect \DIV_internal_op$20 7'0000000 + connect \DIV_internal_op$21 7'0000000 + connect \DIV_internal_op$22 7'0000000 + connect \DIV_internal_op$23 7'0000000 + connect \DIV_internal_op$24 7'0000000 + connect \DIV_internal_op$25 7'0000000 + connect \DIV_internal_op$26 7'0000000 + connect \DIV_internal_op$27 7'0000000 + connect \DIV_internal_op$28 7'0000000 + connect \DIV_internal_op$29 7'0000000 + connect \DIV_internal_op$30 7'0000000 + connect \DIV_internal_op$31 7'0000000 + connect \DIV_internal_op$32 7'0000000 + connect \DIV_in1_sel$33 3'000 + connect \DIV_in1_sel$34 3'000 + connect \DIV_in1_sel$35 3'000 + connect \DIV_in1_sel$36 3'000 + connect \DIV_in1_sel$37 3'000 + connect \DIV_in1_sel$38 3'000 + connect \DIV_in1_sel$39 3'000 + connect \DIV_in1_sel$40 3'000 + connect \DIV_in1_sel$41 3'000 + connect \DIV_in1_sel$42 3'000 + connect \DIV_in1_sel$43 3'000 + connect \DIV_in1_sel$44 3'000 + connect \DIV_in1_sel$45 3'000 + connect \DIV_in1_sel$46 3'000 + connect \DIV_in1_sel$47 3'000 + connect \DIV_in1_sel$48 3'000 + connect \DIV_in2_sel$49 4'0000 + connect \DIV_in2_sel$50 4'0000 + connect \DIV_in2_sel$51 4'0000 + connect \DIV_in2_sel$52 4'0000 + connect \DIV_in2_sel$53 4'0000 + connect \DIV_in2_sel$54 4'0000 + connect \DIV_in2_sel$55 4'0000 + connect \DIV_in2_sel$56 4'0000 + connect \DIV_in2_sel$57 4'0000 + connect \DIV_in2_sel$58 4'0000 + connect \DIV_in2_sel$59 4'0000 + connect \DIV_in2_sel$60 4'0000 + connect \DIV_in2_sel$61 4'0000 + connect \DIV_in2_sel$62 4'0000 + connect \DIV_in2_sel$63 4'0000 + connect \DIV_in2_sel$64 4'0000 + connect \DIV_cr_in$65 3'000 + connect \DIV_cr_in$66 3'000 + connect \DIV_cr_in$67 3'000 + connect \DIV_cr_in$68 3'000 + connect \DIV_cr_in$69 3'000 + connect \DIV_cr_in$70 3'000 + connect \DIV_cr_in$71 3'000 + connect \DIV_cr_in$72 3'000 + connect \DIV_cr_in$73 3'000 + connect \DIV_cr_in$74 3'000 + connect \DIV_cr_in$75 3'000 + connect \DIV_cr_in$76 3'000 + connect \DIV_cr_in$77 3'000 + connect \DIV_cr_in$78 3'000 + connect \DIV_cr_in$79 3'000 + connect \DIV_cr_in$80 3'000 + connect \DIV_cr_out$81 3'000 + connect \DIV_cr_out$82 3'000 + connect \DIV_cr_out$83 3'000 + connect \DIV_cr_out$84 3'000 + connect \DIV_cr_out$85 3'000 + connect \DIV_cr_out$86 3'000 + connect \DIV_cr_out$87 3'000 + connect \DIV_cr_out$88 3'000 + connect \DIV_cr_out$89 3'000 + connect \DIV_cr_out$90 3'000 + connect \DIV_cr_out$91 3'000 + connect \DIV_cr_out$92 3'000 + connect \DIV_cr_out$93 3'000 + connect \DIV_cr_out$94 3'000 + connect \DIV_cr_out$95 3'000 + connect \DIV_cr_out$96 3'000 + connect \DIV_ldst_len$97 4'0000 + connect \DIV_ldst_len$98 4'0000 + connect \DIV_ldst_len$99 4'0000 + connect \DIV_ldst_len$100 4'0000 + connect \DIV_ldst_len$101 4'0000 + connect \DIV_ldst_len$102 4'0000 + connect \DIV_ldst_len$103 4'0000 + connect \DIV_ldst_len$104 4'0000 + connect \DIV_ldst_len$105 4'0000 + connect \DIV_ldst_len$106 4'0000 + connect \DIV_ldst_len$107 4'0000 + connect \DIV_ldst_len$108 4'0000 + connect \DIV_ldst_len$109 4'0000 + connect \DIV_ldst_len$110 4'0000 + connect \DIV_ldst_len$111 4'0000 + connect \DIV_ldst_len$112 4'0000 + connect \DIV_rc_sel$113 2'00 + connect \DIV_rc_sel$114 2'00 + connect \DIV_rc_sel$115 2'00 + connect \DIV_rc_sel$116 2'00 + connect \DIV_rc_sel$117 2'00 + connect \DIV_rc_sel$118 2'00 + connect \DIV_rc_sel$119 2'00 + connect \DIV_rc_sel$120 2'00 + connect \DIV_rc_sel$121 2'00 + connect \DIV_rc_sel$122 2'00 + connect \DIV_rc_sel$123 2'00 + connect \DIV_rc_sel$124 2'00 + connect \DIV_rc_sel$125 2'00 + connect \DIV_rc_sel$126 2'00 + connect \DIV_rc_sel$127 2'00 + connect \DIV_rc_sel$128 2'00 + connect \DIV_cry_in$129 2'00 + connect \DIV_cry_in$130 2'00 + connect \DIV_cry_in$131 2'00 + connect \DIV_cry_in$132 2'00 + connect \DIV_cry_in$133 2'00 + connect \DIV_cry_in$134 2'00 + connect \DIV_cry_in$135 2'00 + connect \DIV_cry_in$136 2'00 + connect \DIV_cry_in$137 2'00 + connect \DIV_cry_in$138 2'00 + connect \DIV_cry_in$139 2'00 + connect \DIV_cry_in$140 2'00 + connect \DIV_cry_in$141 2'00 + connect \DIV_cry_in$142 2'00 + connect \DIV_cry_in$143 2'00 + connect \DIV_cry_in$144 2'00 + connect \DIV_inv_a$145 1'0 + connect \DIV_inv_a$146 1'0 + connect \DIV_inv_a$147 1'0 + connect \DIV_inv_a$148 1'0 + connect \DIV_inv_a$149 1'0 + connect \DIV_inv_a$150 1'0 + connect \DIV_inv_a$151 1'0 + connect \DIV_inv_a$152 1'0 + connect \DIV_inv_a$153 1'0 + connect \DIV_inv_a$154 1'0 + connect \DIV_inv_a$155 1'0 + connect \DIV_inv_a$156 1'0 + connect \DIV_inv_a$157 1'0 + connect \DIV_inv_a$158 1'0 + connect \DIV_inv_a$159 1'0 + connect \DIV_inv_a$160 1'0 + connect \DIV_inv_out$161 1'0 + connect \DIV_inv_out$162 1'0 + connect \DIV_inv_out$163 1'0 + connect \DIV_inv_out$164 1'0 + connect \DIV_inv_out$165 1'0 + connect \DIV_inv_out$166 1'0 + connect \DIV_inv_out$167 1'0 + connect \DIV_inv_out$168 1'0 + connect \DIV_inv_out$169 1'0 + connect \DIV_inv_out$170 1'0 + connect \DIV_inv_out$171 1'0 + connect \DIV_inv_out$172 1'0 + connect \DIV_inv_out$173 1'0 + connect \DIV_inv_out$174 1'0 + connect \DIV_inv_out$175 1'0 + connect \DIV_inv_out$176 1'0 + connect \DIV_cry_out$177 1'0 + connect \DIV_cry_out$178 1'0 + connect \DIV_cry_out$179 1'0 + connect \DIV_cry_out$180 1'0 + connect \DIV_cry_out$181 1'0 + connect \DIV_cry_out$182 1'0 + connect \DIV_cry_out$183 1'0 + connect \DIV_cry_out$184 1'0 + connect \DIV_cry_out$185 1'0 + connect \DIV_cry_out$186 1'0 + connect \DIV_cry_out$187 1'0 + connect \DIV_cry_out$188 1'0 + connect \DIV_cry_out$189 1'0 + connect \DIV_cry_out$190 1'0 + connect \DIV_cry_out$191 1'0 + connect \DIV_cry_out$192 1'0 + connect \DIV_is_32b$193 1'0 + connect \DIV_is_32b$194 1'0 + connect \DIV_is_32b$195 1'0 + connect \DIV_is_32b$196 1'0 + connect \DIV_is_32b$197 1'0 + connect \DIV_is_32b$198 1'0 + connect \DIV_is_32b$199 1'0 + connect \DIV_is_32b$200 1'0 + connect \DIV_is_32b$201 1'0 + connect \DIV_is_32b$202 1'0 + connect \DIV_is_32b$203 1'0 + connect \DIV_is_32b$204 1'0 + connect \DIV_is_32b$205 1'0 + connect \DIV_is_32b$206 1'0 + connect \DIV_is_32b$207 1'0 + connect \DIV_is_32b$208 1'0 + connect \DIV_sgn$209 1'0 + connect \DIV_sgn$210 1'0 + connect \DIV_sgn$211 1'0 + connect \DIV_sgn$212 1'0 + connect \DIV_sgn$213 1'0 + connect \DIV_sgn$214 1'0 + connect \DIV_sgn$215 1'0 + connect \DIV_sgn$216 1'0 + connect \DIV_sgn$217 1'0 + connect \DIV_sgn$218 1'0 + connect \DIV_sgn$219 1'0 + connect \DIV_sgn$220 1'0 + connect \DIV_sgn$221 1'0 + connect \DIV_sgn$222 1'0 + connect \DIV_sgn$223 1'0 + connect \DIV_sgn$224 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec58" +module \DIV_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec62" +module \DIV_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec" +module \dec$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \DIV_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \DIV_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \DIV_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 8 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 9 \DIV_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 10 \DIV_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \DIV_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 17 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 18 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 19 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 20 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 21 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 22 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 23 \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 24 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 25 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 26 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 27 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 28 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 29 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 30 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 31 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 32 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec19_opcode_in + cell \DIV_dec19 \DIV_dec19 + connect \opcode_in \DIV_dec19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec30_opcode_in + cell \DIV_dec30 \DIV_dec30 + connect \opcode_in \DIV_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_dec31_DIV_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_dec31_DIV_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec31_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_dec31_DIV_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec31_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_dec31_DIV_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_dec31_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_dec31_DIV_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_dec31_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec31_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec31_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec31_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec31_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_dec31_DIV_sgn + cell \DIV_dec31 \DIV_dec31 + connect \opcode_in \DIV_dec31_opcode_in + connect \DIV_function_unit \DIV_dec31_DIV_function_unit + connect \DIV_internal_op \DIV_dec31_DIV_internal_op + connect \DIV_in1_sel \DIV_dec31_DIV_in1_sel + connect \DIV_in2_sel \DIV_dec31_DIV_in2_sel + connect \DIV_cr_in \DIV_dec31_DIV_cr_in + connect \DIV_cr_out \DIV_dec31_DIV_cr_out + connect \DIV_ldst_len \DIV_dec31_DIV_ldst_len + connect \DIV_rc_sel \DIV_dec31_DIV_rc_sel + connect \DIV_cry_in \DIV_dec31_DIV_cry_in + connect \DIV_inv_a \DIV_dec31_DIV_inv_a + connect \DIV_inv_out \DIV_dec31_DIV_inv_out + connect \DIV_cry_out \DIV_dec31_DIV_cry_out + connect \DIV_is_32b \DIV_dec31_DIV_is_32b + connect \DIV_sgn \DIV_dec31_DIV_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec58_opcode_in + cell \DIV_dec58 \DIV_dec58 + connect \opcode_in \DIV_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \DIV_dec62_opcode_in + cell \DIV_dec62 \DIV_dec62 + connect \opcode_in \DIV_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \DIV_dec19_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \DIV_dec30_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \DIV_dec31_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \DIV_dec58_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \DIV_dec62_opcode_in 32'00000000000000000000000000000000 + assign \DIV_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \DIV_function_unit$4 + process $group_6 + assign \DIV_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_function_unit \DIV_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_function_unit \DIV_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_function_unit \DIV_dec31_DIV_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_function_unit \DIV_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_function_unit \DIV_function_unit$4 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \DIV_internal_op$8 + process $group_7 + assign \DIV_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_internal_op \DIV_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_internal_op \DIV_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_internal_op \DIV_dec31_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_internal_op \DIV_internal_op$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_internal_op \DIV_internal_op$8 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$9 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$10 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$11 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_in1_sel$12 + process $group_8 + assign \DIV_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_in1_sel \DIV_in1_sel$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_in1_sel \DIV_in1_sel$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_in1_sel \DIV_dec31_DIV_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_in1_sel \DIV_in1_sel$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_in1_sel \DIV_in1_sel$12 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$13 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$14 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$15 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_in2_sel$16 + process $group_9 + assign \DIV_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_in2_sel \DIV_in2_sel$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_in2_sel \DIV_in2_sel$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_in2_sel \DIV_dec31_DIV_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_in2_sel \DIV_in2_sel$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_in2_sel \DIV_in2_sel$16 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$17 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$18 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$19 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_in$20 + process $group_10 + assign \DIV_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_cr_in \DIV_cr_in$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_cr_in \DIV_cr_in$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_cr_in \DIV_dec31_DIV_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_cr_in \DIV_cr_in$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_cr_in \DIV_cr_in$20 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$21 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$22 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$23 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \DIV_cr_out$24 + process $group_11 + assign \DIV_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_cr_out \DIV_cr_out$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_cr_out \DIV_cr_out$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_cr_out \DIV_dec31_DIV_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_cr_out \DIV_cr_out$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_cr_out \DIV_cr_out$24 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$25 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$26 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$27 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \DIV_ldst_len$28 + process $group_12 + assign \DIV_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_ldst_len \DIV_ldst_len$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_ldst_len \DIV_ldst_len$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_ldst_len \DIV_dec31_DIV_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_ldst_len \DIV_ldst_len$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_ldst_len \DIV_ldst_len$28 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$29 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$30 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$31 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_rc_sel$32 + process $group_13 + assign \DIV_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_rc_sel \DIV_rc_sel$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_rc_sel \DIV_rc_sel$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_rc_sel \DIV_dec31_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_rc_sel \DIV_rc_sel$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_rc_sel \DIV_rc_sel$32 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$33 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$35 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \DIV_cry_in$36 + process $group_14 + assign \DIV_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_cry_in \DIV_cry_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_cry_in \DIV_cry_in$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_cry_in \DIV_dec31_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_cry_in \DIV_cry_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_cry_in \DIV_cry_in$36 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_a$40 + process $group_15 + assign \DIV_inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_inv_a \DIV_inv_a$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_inv_a \DIV_inv_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_inv_a \DIV_dec31_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_inv_a \DIV_inv_a$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_inv_a \DIV_inv_a$40 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_inv_out$44 + process $group_16 + assign \DIV_inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_inv_out \DIV_inv_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_inv_out \DIV_inv_out$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_inv_out \DIV_dec31_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_inv_out \DIV_inv_out$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_inv_out \DIV_inv_out$44 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_cry_out$48 + process $group_17 + assign \DIV_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_cry_out \DIV_cry_out$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_cry_out \DIV_cry_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_cry_out \DIV_dec31_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_cry_out \DIV_cry_out$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_cry_out \DIV_cry_out$48 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_is_32b$52 + process $group_18 + assign \DIV_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_is_32b \DIV_is_32b$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_is_32b \DIV_is_32b$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_is_32b \DIV_dec31_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_is_32b \DIV_is_32b$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_is_32b \DIV_is_32b$52 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \DIV_sgn$56 + process $group_19 + assign \DIV_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \DIV_sgn \DIV_sgn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \DIV_sgn \DIV_sgn$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \DIV_sgn \DIV_dec31_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \DIV_sgn \DIV_sgn$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \DIV_sgn \DIV_sgn$56 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$57 + process $group_20 + assign \opcode_switch$57 32'00000000000000000000000000000000 + assign \opcode_switch$57 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $59 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $58 + end + process $group_21 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $58 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_RS + process $group_22 + assign \DIV_RS 5'00000 + assign \DIV_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_RT + process $group_23 + assign \DIV_RT 5'00000 + assign \DIV_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_24 + assign \DIV_RA 5'00000 + assign \DIV_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_RB + process $group_25 + assign \DIV_RB 5'00000 + assign \DIV_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_26 + assign \DIV_SI 16'0000000000000000 + assign \DIV_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_27 + assign \DIV_UI 16'0000000000000000 + assign \DIV_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \DIV_L + process $group_28 + assign \DIV_L 1'0 + assign \DIV_L { \opcode_in [21] } + sync init + end + process $group_29 + assign \DIV_SH32 5'00000 + assign \DIV_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_30 + assign \DIV_sh 6'000000 + assign \DIV_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_MB32 + process $group_31 + assign \DIV_MB32 5'00000 + assign \DIV_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_ME32 + process $group_32 + assign \DIV_ME32 5'00000 + assign \DIV_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_33 + assign \DIV_LI 24'000000000000000000000000 + assign \DIV_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \DIV_LK + process $group_34 + assign \DIV_LK 1'0 + assign \DIV_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \DIV_AA + process $group_35 + assign \DIV_AA 1'0 + assign \DIV_AA { \opcode_in [1] } + sync init + end + process $group_36 + assign \DIV_Rc 1'0 + assign \DIV_Rc { \opcode_in [0] } + sync init + end + process $group_37 + assign \DIV_OE 1'0 + assign \DIV_OE { \opcode_in [10] } + sync init + end + process $group_38 + assign \DIV_BD 14'00000000000000 + assign \DIV_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \DIV_BF + process $group_39 + assign \DIV_BF 3'000 + assign \DIV_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \DIV_CR + process $group_40 + assign \DIV_CR 10'0000000000 + assign \DIV_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_41 + assign \DIV_BB 5'00000 + assign \DIV_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_42 + assign \DIV_BA 5'00000 + assign \DIV_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_43 + assign \DIV_BT 5'00000 + assign \DIV_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_44 + assign \DIV_FXM 8'00000000 + assign \DIV_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_BO + process $group_45 + assign \DIV_BO 5'00000 + assign \DIV_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_46 + assign \DIV_BI 5'00000 + assign \DIV_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \DIV_BH + process $group_47 + assign \DIV_BH 2'00 + assign \DIV_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \DIV_D + process $group_48 + assign \DIV_D 16'0000000000000000 + assign \DIV_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_49 + assign \DIV_DS 14'00000000000000 + assign \DIV_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_TO + process $group_50 + assign \DIV_TO 5'00000 + assign \DIV_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_51 + assign \DIV_BC 5'00000 + assign \DIV_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_SH + process $group_52 + assign \DIV_SH 5'00000 + assign \DIV_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_ME + process $group_53 + assign \DIV_ME 5'00000 + assign \DIV_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \DIV_MB + process $group_54 + assign \DIV_MB 5'00000 + assign \DIV_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \DIV_SPR + process $group_55 + assign \DIV_SPR 10'0000000000 + assign \DIV_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_56 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_57 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_58 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_59 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_60 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_61 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_62 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_63 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_64 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_65 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_66 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_67 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_68 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_69 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_70 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_71 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_72 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_73 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_74 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_75 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_76 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_77 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_78 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_79 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_80 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_81 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_82 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_83 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_84 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_85 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_86 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_87 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_88 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_89 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_90 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_91 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_92 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_93 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_94 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_95 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_96 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_97 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_98 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_99 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_100 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_101 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_102 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_103 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_104 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_105 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_106 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_107 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_108 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_109 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_110 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_111 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_112 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_113 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_114 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_115 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_116 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_117 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_118 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_119 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_120 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_121 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_122 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_123 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_124 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_125 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_126 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_127 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_128 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_129 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_130 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_131 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_132 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_133 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_134 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_135 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_136 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_137 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_138 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_139 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_140 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_141 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_142 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_143 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_144 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_145 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_146 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_147 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_148 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_149 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_150 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_151 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_152 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_153 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_154 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_155 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_156 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_157 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_158 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_159 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_160 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_161 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_162 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_163 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_164 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_165 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_166 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_167 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_168 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_169 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_170 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_171 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_172 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_173 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_174 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_175 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_176 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_177 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_178 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_179 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_180 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_181 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_182 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_183 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_184 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_185 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_186 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_187 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_188 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_189 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_190 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_191 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_192 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_193 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_194 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_195 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_196 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_197 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_198 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_199 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_200 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_201 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_202 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_203 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_204 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_205 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_206 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_207 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_208 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_209 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_210 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_211 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_212 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_213 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_214 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_215 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_216 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_217 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_218 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_219 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_220 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_221 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_222 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_223 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_224 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_225 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_226 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_227 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_228 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_229 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_230 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_231 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_232 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_233 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_234 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_235 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_236 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_237 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_238 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_239 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_240 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_241 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_242 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_243 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_244 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_245 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_246 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_247 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_248 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_249 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_250 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_251 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_252 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_253 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_254 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_255 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_256 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_257 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_258 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_259 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_260 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_261 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_262 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_263 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_264 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_265 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_266 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_267 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_268 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_269 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_270 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_271 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_272 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_273 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_274 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_275 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_276 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_277 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_278 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_279 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_280 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_281 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_282 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_283 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_284 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_285 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_286 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_287 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_288 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_289 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_290 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_291 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_292 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_293 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_294 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_295 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_296 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_297 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_298 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_299 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_300 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_301 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_302 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_303 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_304 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_305 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_306 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_307 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_308 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_309 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_310 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_311 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_312 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_313 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_314 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_315 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_316 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_317 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_318 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_319 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_320 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_321 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_322 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_323 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_324 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_325 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_326 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_327 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_328 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_329 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_330 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_331 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_332 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_333 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_334 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_335 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_336 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_337 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_338 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_339 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_340 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_341 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_342 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_343 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_344 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_345 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_346 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_347 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \DIV_function_unit$1 11'00000000000 + connect \DIV_function_unit$2 11'00000000000 + connect \DIV_function_unit$3 11'00000000000 + connect \DIV_function_unit$4 11'00000000000 + connect \DIV_internal_op$5 7'0000000 + connect \DIV_internal_op$6 7'0000000 + connect \DIV_internal_op$7 7'0000000 + connect \DIV_internal_op$8 7'0000000 + connect \DIV_in1_sel$9 3'000 + connect \DIV_in1_sel$10 3'000 + connect \DIV_in1_sel$11 3'000 + connect \DIV_in1_sel$12 3'000 + connect \DIV_in2_sel$13 4'0000 + connect \DIV_in2_sel$14 4'0000 + connect \DIV_in2_sel$15 4'0000 + connect \DIV_in2_sel$16 4'0000 + connect \DIV_cr_in$17 3'000 + connect \DIV_cr_in$18 3'000 + connect \DIV_cr_in$19 3'000 + connect \DIV_cr_in$20 3'000 + connect \DIV_cr_out$21 3'000 + connect \DIV_cr_out$22 3'000 + connect \DIV_cr_out$23 3'000 + connect \DIV_cr_out$24 3'000 + connect \DIV_ldst_len$25 4'0000 + connect \DIV_ldst_len$26 4'0000 + connect \DIV_ldst_len$27 4'0000 + connect \DIV_ldst_len$28 4'0000 + connect \DIV_rc_sel$29 2'00 + connect \DIV_rc_sel$30 2'00 + connect \DIV_rc_sel$31 2'00 + connect \DIV_rc_sel$32 2'00 + connect \DIV_cry_in$33 2'00 + connect \DIV_cry_in$34 2'00 + connect \DIV_cry_in$35 2'00 + connect \DIV_cry_in$36 2'00 + connect \DIV_inv_a$37 1'0 + connect \DIV_inv_a$38 1'0 + connect \DIV_inv_a$39 1'0 + connect \DIV_inv_a$40 1'0 + connect \DIV_inv_out$41 1'0 + connect \DIV_inv_out$42 1'0 + connect \DIV_inv_out$43 1'0 + connect \DIV_inv_out$44 1'0 + connect \DIV_cry_out$45 1'0 + connect \DIV_cry_out$46 1'0 + connect \DIV_cry_out$47 1'0 + connect \DIV_cry_out$48 1'0 + connect \DIV_is_32b$49 1'0 + connect \DIV_is_32b$50 1'0 + connect \DIV_is_32b$51 1'0 + connect \DIV_is_32b$52 1'0 + connect \DIV_sgn$53 1'0 + connect \DIV_sgn$54 1'0 + connect \DIV_sgn$55 1'0 + connect \DIV_sgn$56 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_rc" +module \dec_rc$169 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \DIV_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_oe" +module \dec_oe$170 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \DIV_OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \DIV_OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in.ppick" +module \ppick$172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in" +module \dec_cr_in$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$172 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \DIV_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \DIV_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \DIV_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \DIV_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \DIV_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out.ppick" +module \ppick$174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out" +module \dec_cr_out$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 5 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$174 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \DIV_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_ai" +module \dec_ai$175 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 output 1 \immz_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 2 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + process $group_0 + assign \ra 5'00000 + assign \ra \DIV_RA + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B $3 + connect \Y $5 + end + process $group_1 + assign \immz_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + case 1'1 + assign \immz_out 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_bi" +module \dec_bi$176 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV" +module \dec_DIV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \DIV_DIV__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \DIV_DIV__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 6 \DIV_DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 7 \DIV_DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \DIV_DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \DIV_DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \DIV_DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \DIV_DIV__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 17 \DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \DIV_DIV__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \DIV_DIV__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_DIV_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_DIV_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_DIV_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_DIV_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_DIV_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_DIV_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_DIV_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_DIV_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$168 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_cr_in \dec_DIV_cr_in + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_RA \dec_DIV_RA + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_sh \dec_DIV_sh + connect \DIV_LI \dec_DIV_LI + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_OE \dec_DIV_OE + connect \DIV_BD \dec_DIV_BD + connect \DIV_BB \dec_DIV_BB + connect \DIV_BA \dec_DIV_BA + connect \DIV_BT \dec_DIV_BT + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_BI \dec_DIV_BI + connect \DIV_DS \dec_DIV_DS + connect \DIV_BC \dec_DIV_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc$169 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \DIV_Rc \dec_DIV_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe$170 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \DIV_OE \dec_DIV_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$171 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_BB \dec_DIV_BB + connect \DIV_BA \dec_DIV_BA + connect \DIV_BT \dec_DIV_BT + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_BI \dec_DIV_BI + connect \DIV_BC \dec_DIV_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + cell \dec_cr_out$173 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \DIV_internal_op \dec_DIV_internal_op + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \DIV_FXM \dec_DIV_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 \dec_ai_immz_out + cell \dec_ai$175 \dec_ai + connect \sel_in \dec_ai_sel_in + connect \immz_out \dec_ai_immz_out + connect \DIV_RA \dec_DIV_RA + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi$176 \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_sh \dec_DIV_sh + connect \DIV_LI \dec_DIV_LI + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + end + process $group_0 + assign \DIV_DIV__insn 32'00000000000000000000000000000000 + assign \DIV_DIV__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_DIV_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_DIV_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_DIV_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_DIV_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \DIV_DIV__insn_type 7'0000000 + assign \DIV_DIV__insn_type \dec_DIV_internal_op + sync init + end + process $group_11 + assign \DIV_DIV__fn_unit 11'00000000000 + assign \DIV_DIV__fn_unit \dec_DIV_function_unit + sync init + end + process $group_12 + assign \dec_ai_sel_in 3'000 + assign \dec_ai_sel_in \dec_DIV_in1_sel + sync init + end + process $group_13 + assign \DIV_DIV__zero_a 1'0 + assign \DIV_DIV__zero_a \dec_ai_immz_out + sync init + end + process $group_14 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_DIV_in2_sel + sync init + end + process $group_15 + assign \DIV_DIV__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \DIV_DIV__imm_data__ok 1'0 + assign { \DIV_DIV__imm_data__ok \DIV_DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_17 + assign \DIV_DIV__rc__rc 1'0 + assign \DIV_DIV__rc__ok 1'0 + assign { \DIV_DIV__rc__ok \DIV_DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + sync init + end + process $group_19 + assign \DIV_DIV__oe__oe 1'0 + assign \DIV_DIV__oe__ok 1'0 + assign { \DIV_DIV__oe__ok \DIV_DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + sync init + end + process $group_21 + assign \DIV_DIV__write_cr0 1'0 + assign \DIV_DIV__write_cr0 \dec_cr_out_cr_bitfield_ok + sync init + end + process $group_22 + assign \DIV_DIV__data_len 4'0000 + assign \DIV_DIV__data_len \dec_DIV_ldst_len + sync init + end + process $group_23 + assign \DIV_DIV__invert_in 1'0 + assign \DIV_DIV__invert_in \dec_DIV_inv_a + sync init + end + process $group_24 + assign \DIV_DIV__invert_out 1'0 + assign \DIV_DIV__invert_out \dec_DIV_inv_out + sync init + end + process $group_25 + assign \DIV_DIV__input_carry 2'00 + assign \DIV_DIV__input_carry \dec_DIV_cry_in + sync init + end + process $group_26 + assign \DIV_DIV__output_carry 1'0 + assign \DIV_DIV__output_carry \dec_DIV_cry_out + sync init + end + process $group_27 + assign \DIV_DIV__is_32bit 1'0 + assign \DIV_DIV__is_32bit \dec_DIV_is_32b + sync init + end + process $group_28 + assign \DIV_DIV__is_signed 1'0 + assign \DIV_DIV__is_signed \dec_DIV_sgn + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec19" +module \MUL_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_1 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec30" +module \MUL_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub10" +module \MUL_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub28" +module \MUL_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub0" +module \MUL_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub26" +module \MUL_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub19" +module \MUL_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub22" +module \MUL_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub9" +module \MUL_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \MUL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \MUL_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \MUL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 7 \MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \MUL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_function_unit 11'00100000000 + end + sync init + end + process $group_2 + assign \MUL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_internal_op 7'0110010 + end + sync init + end + process $group_3 + assign \MUL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_in2_sel 4'0001 + end + sync init + end + process $group_4 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_cr_in 3'000 + end + sync init + end + process $group_5 + assign \MUL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_cr_out 3'001 + end + sync init + end + process $group_6 + assign \MUL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_rc_sel 2'10 + end + sync init + end + process $group_7 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_is_32b 1'0 + end + sync init + end + process $group_8 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_sgn 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub11" +module \MUL_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \MUL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \MUL_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \MUL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 7 \MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \MUL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_function_unit 11'00100000000 + end + sync init + end + process $group_2 + assign \MUL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_internal_op 7'0110010 + end + sync init + end + process $group_3 + assign \MUL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_in2_sel 4'0001 + end + sync init + end + process $group_4 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_cr_in 3'000 + end + sync init + end + process $group_5 + assign \MUL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_cr_out 3'001 + end + sync init + end + process $group_6 + assign \MUL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_rc_sel 2'10 + end + sync init + end + process $group_7 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_is_32b 1'1 + end + sync init + end + process $group_8 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \MUL_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10010 + assign \MUL_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \MUL_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \MUL_sgn 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub27" +module \MUL_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub15" +module \MUL_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub20" +module \MUL_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub21" +module \MUL_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub23" +module \MUL_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub16" +module \MUL_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub18" +module \MUL_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub8" +module \MUL_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub24" +module \MUL_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub4" +module \MUL_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31" +module \MUL_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \MUL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \MUL_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \MUL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 7 \MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub10_opcode_in + cell \MUL_dec_sub10 \MUL_dec_sub10 + connect \opcode_in \MUL_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub28_opcode_in + cell \MUL_dec_sub28 \MUL_dec_sub28 + connect \opcode_in \MUL_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub0_opcode_in + cell \MUL_dec_sub0 \MUL_dec_sub0 + connect \opcode_in \MUL_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub26_opcode_in + cell \MUL_dec_sub26 \MUL_dec_sub26 + connect \opcode_in \MUL_dec_sub26_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub19_opcode_in + cell \MUL_dec_sub19 \MUL_dec_sub19 + connect \opcode_in \MUL_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub22_opcode_in + cell \MUL_dec_sub22 \MUL_dec_sub22 + connect \opcode_in \MUL_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_dec_sub9_MUL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_dec_sub9_MUL_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_dec_sub9_MUL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_dec_sub9_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_dec_sub9_MUL_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_dec_sub9_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_dec_sub9_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_dec_sub9_MUL_sgn + cell \MUL_dec_sub9 \MUL_dec_sub9 + connect \opcode_in \MUL_dec_sub9_opcode_in + connect \MUL_function_unit \MUL_dec_sub9_MUL_function_unit + connect \MUL_internal_op \MUL_dec_sub9_MUL_internal_op + connect \MUL_in2_sel \MUL_dec_sub9_MUL_in2_sel + connect \MUL_cr_in \MUL_dec_sub9_MUL_cr_in + connect \MUL_cr_out \MUL_dec_sub9_MUL_cr_out + connect \MUL_rc_sel \MUL_dec_sub9_MUL_rc_sel + connect \MUL_is_32b \MUL_dec_sub9_MUL_is_32b + connect \MUL_sgn \MUL_dec_sub9_MUL_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub11_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_dec_sub11_MUL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_dec_sub11_MUL_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_dec_sub11_MUL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_dec_sub11_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_dec_sub11_MUL_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_dec_sub11_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_dec_sub11_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_dec_sub11_MUL_sgn + cell \MUL_dec_sub11 \MUL_dec_sub11 + connect \opcode_in \MUL_dec_sub11_opcode_in + connect \MUL_function_unit \MUL_dec_sub11_MUL_function_unit + connect \MUL_internal_op \MUL_dec_sub11_MUL_internal_op + connect \MUL_in2_sel \MUL_dec_sub11_MUL_in2_sel + connect \MUL_cr_in \MUL_dec_sub11_MUL_cr_in + connect \MUL_cr_out \MUL_dec_sub11_MUL_cr_out + connect \MUL_rc_sel \MUL_dec_sub11_MUL_rc_sel + connect \MUL_is_32b \MUL_dec_sub11_MUL_is_32b + connect \MUL_sgn \MUL_dec_sub11_MUL_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub27_opcode_in + cell \MUL_dec_sub27 \MUL_dec_sub27 + connect \opcode_in \MUL_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub15_opcode_in + cell \MUL_dec_sub15 \MUL_dec_sub15 + connect \opcode_in \MUL_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub20_opcode_in + cell \MUL_dec_sub20 \MUL_dec_sub20 + connect \opcode_in \MUL_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub21_opcode_in + cell \MUL_dec_sub21 \MUL_dec_sub21 + connect \opcode_in \MUL_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub23_opcode_in + cell \MUL_dec_sub23 \MUL_dec_sub23 + connect \opcode_in \MUL_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub16_opcode_in + cell \MUL_dec_sub16 \MUL_dec_sub16 + connect \opcode_in \MUL_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub18_opcode_in + cell \MUL_dec_sub18 \MUL_dec_sub18 + connect \opcode_in \MUL_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub8_opcode_in + cell \MUL_dec_sub8 \MUL_dec_sub8 + connect \opcode_in \MUL_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub24_opcode_in + cell \MUL_dec_sub24 \MUL_dec_sub24 + connect \opcode_in \MUL_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec_sub4_opcode_in + cell \MUL_dec_sub4 \MUL_dec_sub4 + connect \opcode_in \MUL_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \MUL_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \MUL_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \MUL_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \MUL_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \MUL_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \MUL_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \MUL_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \MUL_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \MUL_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \MUL_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \MUL_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \MUL_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \MUL_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \MUL_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \MUL_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \MUL_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \MUL_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \MUL_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$14 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$16 + process $group_20 + assign \MUL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_function_unit \MUL_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_function_unit \MUL_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_function_unit \MUL_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_function_unit \MUL_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_function_unit \MUL_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_function_unit \MUL_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_function_unit \MUL_dec_sub9_MUL_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_function_unit \MUL_dec_sub11_MUL_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_function_unit \MUL_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_function_unit \MUL_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_function_unit \MUL_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_function_unit \MUL_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_function_unit \MUL_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_function_unit \MUL_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_function_unit \MUL_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_function_unit \MUL_function_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_function_unit \MUL_function_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_function_unit \MUL_function_unit$16 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$31 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$32 + process $group_21 + assign \MUL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_internal_op \MUL_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_internal_op \MUL_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_internal_op \MUL_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_internal_op \MUL_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_internal_op \MUL_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_internal_op \MUL_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_internal_op \MUL_dec_sub9_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_internal_op \MUL_dec_sub11_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_internal_op \MUL_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_internal_op \MUL_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_internal_op \MUL_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_internal_op \MUL_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_internal_op \MUL_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_internal_op \MUL_internal_op$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_internal_op \MUL_internal_op$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_internal_op \MUL_internal_op$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_internal_op \MUL_internal_op$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_internal_op \MUL_internal_op$32 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$33 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$34 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$35 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$36 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$37 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$38 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$39 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$40 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$41 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$42 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$43 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$44 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$45 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$46 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$47 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$48 + process $group_22 + assign \MUL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_in2_sel \MUL_in2_sel$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_in2_sel \MUL_in2_sel$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_in2_sel \MUL_in2_sel$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_in2_sel \MUL_in2_sel$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_in2_sel \MUL_in2_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_in2_sel \MUL_in2_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_in2_sel \MUL_dec_sub9_MUL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_in2_sel \MUL_dec_sub11_MUL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_in2_sel \MUL_in2_sel$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_in2_sel \MUL_in2_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_in2_sel \MUL_in2_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_in2_sel \MUL_in2_sel$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_in2_sel \MUL_in2_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_in2_sel \MUL_in2_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_in2_sel \MUL_in2_sel$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_in2_sel \MUL_in2_sel$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_in2_sel \MUL_in2_sel$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_in2_sel \MUL_in2_sel$48 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$49 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$50 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$51 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$52 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$53 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$54 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$55 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$56 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$57 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$58 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$59 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$60 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$61 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$62 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$63 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$64 + process $group_23 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_cr_in \MUL_cr_in$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_cr_in \MUL_cr_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_cr_in \MUL_cr_in$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_cr_in \MUL_cr_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_cr_in \MUL_cr_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_cr_in \MUL_cr_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_cr_in \MUL_dec_sub9_MUL_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_cr_in \MUL_dec_sub11_MUL_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_cr_in \MUL_cr_in$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_cr_in \MUL_cr_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_cr_in \MUL_cr_in$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_cr_in \MUL_cr_in$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_cr_in \MUL_cr_in$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_cr_in \MUL_cr_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_cr_in \MUL_cr_in$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_cr_in \MUL_cr_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_cr_in \MUL_cr_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_cr_in \MUL_cr_in$64 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$65 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$66 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$67 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$68 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$69 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$70 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$71 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$72 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$73 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$74 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$75 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$76 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$77 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$78 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$79 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$80 + process $group_24 + assign \MUL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_cr_out \MUL_cr_out$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_cr_out \MUL_cr_out$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_cr_out \MUL_cr_out$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_cr_out \MUL_cr_out$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_cr_out \MUL_cr_out$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_cr_out \MUL_cr_out$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_cr_out \MUL_dec_sub9_MUL_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_cr_out \MUL_dec_sub11_MUL_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_cr_out \MUL_cr_out$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_cr_out \MUL_cr_out$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_cr_out \MUL_cr_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_cr_out \MUL_cr_out$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_cr_out \MUL_cr_out$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_cr_out \MUL_cr_out$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_cr_out \MUL_cr_out$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_cr_out \MUL_cr_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_cr_out \MUL_cr_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_cr_out \MUL_cr_out$80 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$81 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$82 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$83 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$84 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$85 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$86 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$87 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$88 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$89 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$90 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$91 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$92 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$93 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$94 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$95 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$96 + process $group_25 + assign \MUL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_rc_sel \MUL_rc_sel$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_rc_sel \MUL_rc_sel$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_rc_sel \MUL_rc_sel$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_rc_sel \MUL_rc_sel$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_rc_sel \MUL_rc_sel$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_rc_sel \MUL_rc_sel$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_rc_sel \MUL_dec_sub9_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_rc_sel \MUL_dec_sub11_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_rc_sel \MUL_rc_sel$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_rc_sel \MUL_rc_sel$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_rc_sel \MUL_rc_sel$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_rc_sel \MUL_rc_sel$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_rc_sel \MUL_rc_sel$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_rc_sel \MUL_rc_sel$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_rc_sel \MUL_rc_sel$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_rc_sel \MUL_rc_sel$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_rc_sel \MUL_rc_sel$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_rc_sel \MUL_rc_sel$96 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$112 + process $group_26 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_is_32b \MUL_is_32b$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_is_32b \MUL_is_32b$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_is_32b \MUL_is_32b$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_is_32b \MUL_is_32b$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_is_32b \MUL_is_32b$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_is_32b \MUL_is_32b$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_is_32b \MUL_dec_sub9_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_is_32b \MUL_dec_sub11_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_is_32b \MUL_is_32b$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_is_32b \MUL_is_32b$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_is_32b \MUL_is_32b$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_is_32b \MUL_is_32b$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_is_32b \MUL_is_32b$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_is_32b \MUL_is_32b$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_is_32b \MUL_is_32b$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_is_32b \MUL_is_32b$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_is_32b \MUL_is_32b$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_is_32b \MUL_is_32b$112 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$128 + process $group_27 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \MUL_sgn \MUL_sgn$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \MUL_sgn \MUL_sgn$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \MUL_sgn \MUL_sgn$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \MUL_sgn \MUL_sgn$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \MUL_sgn \MUL_sgn$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \MUL_sgn \MUL_sgn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \MUL_sgn \MUL_dec_sub9_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \MUL_sgn \MUL_dec_sub11_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \MUL_sgn \MUL_sgn$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \MUL_sgn \MUL_sgn$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \MUL_sgn \MUL_sgn$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \MUL_sgn \MUL_sgn$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \MUL_sgn \MUL_sgn$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \MUL_sgn \MUL_sgn$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \MUL_sgn \MUL_sgn$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \MUL_sgn \MUL_sgn$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \MUL_sgn \MUL_sgn$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \MUL_sgn \MUL_sgn$128 + end + sync init + end + connect \MUL_function_unit$1 11'00000000000 + connect \MUL_function_unit$2 11'00000000000 + connect \MUL_function_unit$3 11'00000000000 + connect \MUL_function_unit$4 11'00000000000 + connect \MUL_function_unit$5 11'00000000000 + connect \MUL_function_unit$6 11'00000000000 + connect \MUL_function_unit$7 11'00000000000 + connect \MUL_function_unit$8 11'00000000000 + connect \MUL_function_unit$9 11'00000000000 + connect \MUL_function_unit$10 11'00000000000 + connect \MUL_function_unit$11 11'00000000000 + connect \MUL_function_unit$12 11'00000000000 + connect \MUL_function_unit$13 11'00000000000 + connect \MUL_function_unit$14 11'00000000000 + connect \MUL_function_unit$15 11'00000000000 + connect \MUL_function_unit$16 11'00000000000 + connect \MUL_internal_op$17 7'0000000 + connect \MUL_internal_op$18 7'0000000 + connect \MUL_internal_op$19 7'0000000 + connect \MUL_internal_op$20 7'0000000 + connect \MUL_internal_op$21 7'0000000 + connect \MUL_internal_op$22 7'0000000 + connect \MUL_internal_op$23 7'0000000 + connect \MUL_internal_op$24 7'0000000 + connect \MUL_internal_op$25 7'0000000 + connect \MUL_internal_op$26 7'0000000 + connect \MUL_internal_op$27 7'0000000 + connect \MUL_internal_op$28 7'0000000 + connect \MUL_internal_op$29 7'0000000 + connect \MUL_internal_op$30 7'0000000 + connect \MUL_internal_op$31 7'0000000 + connect \MUL_internal_op$32 7'0000000 + connect \MUL_in2_sel$33 4'0000 + connect \MUL_in2_sel$34 4'0000 + connect \MUL_in2_sel$35 4'0000 + connect \MUL_in2_sel$36 4'0000 + connect \MUL_in2_sel$37 4'0000 + connect \MUL_in2_sel$38 4'0000 + connect \MUL_in2_sel$39 4'0000 + connect \MUL_in2_sel$40 4'0000 + connect \MUL_in2_sel$41 4'0000 + connect \MUL_in2_sel$42 4'0000 + connect \MUL_in2_sel$43 4'0000 + connect \MUL_in2_sel$44 4'0000 + connect \MUL_in2_sel$45 4'0000 + connect \MUL_in2_sel$46 4'0000 + connect \MUL_in2_sel$47 4'0000 + connect \MUL_in2_sel$48 4'0000 + connect \MUL_cr_in$49 3'000 + connect \MUL_cr_in$50 3'000 + connect \MUL_cr_in$51 3'000 + connect \MUL_cr_in$52 3'000 + connect \MUL_cr_in$53 3'000 + connect \MUL_cr_in$54 3'000 + connect \MUL_cr_in$55 3'000 + connect \MUL_cr_in$56 3'000 + connect \MUL_cr_in$57 3'000 + connect \MUL_cr_in$58 3'000 + connect \MUL_cr_in$59 3'000 + connect \MUL_cr_in$60 3'000 + connect \MUL_cr_in$61 3'000 + connect \MUL_cr_in$62 3'000 + connect \MUL_cr_in$63 3'000 + connect \MUL_cr_in$64 3'000 + connect \MUL_cr_out$65 3'000 + connect \MUL_cr_out$66 3'000 + connect \MUL_cr_out$67 3'000 + connect \MUL_cr_out$68 3'000 + connect \MUL_cr_out$69 3'000 + connect \MUL_cr_out$70 3'000 + connect \MUL_cr_out$71 3'000 + connect \MUL_cr_out$72 3'000 + connect \MUL_cr_out$73 3'000 + connect \MUL_cr_out$74 3'000 + connect \MUL_cr_out$75 3'000 + connect \MUL_cr_out$76 3'000 + connect \MUL_cr_out$77 3'000 + connect \MUL_cr_out$78 3'000 + connect \MUL_cr_out$79 3'000 + connect \MUL_cr_out$80 3'000 + connect \MUL_rc_sel$81 2'00 + connect \MUL_rc_sel$82 2'00 + connect \MUL_rc_sel$83 2'00 + connect \MUL_rc_sel$84 2'00 + connect \MUL_rc_sel$85 2'00 + connect \MUL_rc_sel$86 2'00 + connect \MUL_rc_sel$87 2'00 + connect \MUL_rc_sel$88 2'00 + connect \MUL_rc_sel$89 2'00 + connect \MUL_rc_sel$90 2'00 + connect \MUL_rc_sel$91 2'00 + connect \MUL_rc_sel$92 2'00 + connect \MUL_rc_sel$93 2'00 + connect \MUL_rc_sel$94 2'00 + connect \MUL_rc_sel$95 2'00 + connect \MUL_rc_sel$96 2'00 + connect \MUL_is_32b$97 1'0 + connect \MUL_is_32b$98 1'0 + connect \MUL_is_32b$99 1'0 + connect \MUL_is_32b$100 1'0 + connect \MUL_is_32b$101 1'0 + connect \MUL_is_32b$102 1'0 + connect \MUL_is_32b$103 1'0 + connect \MUL_is_32b$104 1'0 + connect \MUL_is_32b$105 1'0 + connect \MUL_is_32b$106 1'0 + connect \MUL_is_32b$107 1'0 + connect \MUL_is_32b$108 1'0 + connect \MUL_is_32b$109 1'0 + connect \MUL_is_32b$110 1'0 + connect \MUL_is_32b$111 1'0 + connect \MUL_is_32b$112 1'0 + connect \MUL_sgn$113 1'0 + connect \MUL_sgn$114 1'0 + connect \MUL_sgn$115 1'0 + connect \MUL_sgn$116 1'0 + connect \MUL_sgn$117 1'0 + connect \MUL_sgn$118 1'0 + connect \MUL_sgn$119 1'0 + connect \MUL_sgn$120 1'0 + connect \MUL_sgn$121 1'0 + connect \MUL_sgn$122 1'0 + connect \MUL_sgn$123 1'0 + connect \MUL_sgn$124 1'0 + connect \MUL_sgn$125 1'0 + connect \MUL_sgn$126 1'0 + connect \MUL_sgn$127 1'0 + connect \MUL_sgn$128 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec58" +module \MUL_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec62" +module \MUL_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec" +module \dec$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \MUL_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \MUL_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 8 \MUL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 11 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 12 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 13 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 14 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 15 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 16 \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 17 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 18 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 19 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 20 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 21 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 22 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 23 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 24 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 25 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 26 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 27 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 28 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec19_opcode_in + cell \MUL_dec19 \MUL_dec19 + connect \opcode_in \MUL_dec19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec30_opcode_in + cell \MUL_dec30 \MUL_dec30 + connect \opcode_in \MUL_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_dec31_MUL_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_dec31_MUL_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_dec31_MUL_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_dec31_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_dec31_MUL_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_dec31_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_dec31_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_dec31_MUL_sgn + cell \MUL_dec31 \MUL_dec31 + connect \opcode_in \MUL_dec31_opcode_in + connect \MUL_function_unit \MUL_dec31_MUL_function_unit + connect \MUL_internal_op \MUL_dec31_MUL_internal_op + connect \MUL_in2_sel \MUL_dec31_MUL_in2_sel + connect \MUL_cr_in \MUL_dec31_MUL_cr_in + connect \MUL_cr_out \MUL_dec31_MUL_cr_out + connect \MUL_rc_sel \MUL_dec31_MUL_rc_sel + connect \MUL_is_32b \MUL_dec31_MUL_is_32b + connect \MUL_sgn \MUL_dec31_MUL_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec58_opcode_in + cell \MUL_dec58 \MUL_dec58 + connect \opcode_in \MUL_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \MUL_dec62_opcode_in + cell \MUL_dec62 \MUL_dec62 + connect \opcode_in \MUL_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \MUL_dec19_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \MUL_dec30_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \MUL_dec31_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \MUL_dec58_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \MUL_dec62_opcode_in 32'00000000000000000000000000000000 + assign \MUL_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \MUL_function_unit$4 + process $group_6 + assign \MUL_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_function_unit \MUL_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_function_unit \MUL_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_function_unit \MUL_dec31_MUL_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_function_unit \MUL_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_function_unit \MUL_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_function_unit 11'00100000000 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \MUL_internal_op$8 + process $group_7 + assign \MUL_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_internal_op \MUL_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_internal_op \MUL_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_internal_op \MUL_dec31_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_internal_op \MUL_internal_op$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_internal_op \MUL_internal_op$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_internal_op 7'0110010 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$9 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$10 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$11 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \MUL_in2_sel$12 + process $group_8 + assign \MUL_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_in2_sel \MUL_in2_sel$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_in2_sel \MUL_in2_sel$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_in2_sel \MUL_dec31_MUL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_in2_sel \MUL_in2_sel$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_in2_sel \MUL_in2_sel$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_in2_sel 4'0011 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$13 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$14 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$15 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_in$16 + process $group_9 + assign \MUL_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_cr_in \MUL_cr_in$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_cr_in \MUL_cr_in$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_cr_in \MUL_dec31_MUL_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_cr_in \MUL_cr_in$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_cr_in \MUL_cr_in$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_cr_in 3'000 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$17 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$18 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$19 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \MUL_cr_out$20 + process $group_10 + assign \MUL_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_cr_out \MUL_cr_out$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_cr_out \MUL_cr_out$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_cr_out \MUL_dec31_MUL_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_cr_out \MUL_cr_out$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_cr_out \MUL_cr_out$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_cr_out 3'001 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$21 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$22 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$23 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \MUL_rc_sel$24 + process $group_11 + assign \MUL_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_rc_sel \MUL_rc_sel$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_rc_sel \MUL_rc_sel$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_rc_sel \MUL_dec31_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_rc_sel \MUL_rc_sel$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_rc_sel \MUL_rc_sel$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_rc_sel 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_is_32b$28 + process $group_12 + assign \MUL_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_is_32b \MUL_is_32b$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_is_32b \MUL_is_32b$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_is_32b \MUL_dec31_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_is_32b \MUL_is_32b$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_is_32b \MUL_is_32b$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_is_32b 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \MUL_sgn$32 + process $group_13 + assign \MUL_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \MUL_sgn \MUL_sgn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \MUL_sgn \MUL_sgn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \MUL_sgn \MUL_dec31_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \MUL_sgn \MUL_sgn$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \MUL_sgn \MUL_sgn$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \MUL_sgn 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$33 + process $group_14 + assign \opcode_switch$33 32'00000000000000000000000000000000 + assign \opcode_switch$33 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $35 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $34 + end + process $group_15 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $34 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_RS + process $group_16 + assign \MUL_RS 5'00000 + assign \MUL_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_RT + process $group_17 + assign \MUL_RT 5'00000 + assign \MUL_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_RA + process $group_18 + assign \MUL_RA 5'00000 + assign \MUL_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_RB + process $group_19 + assign \MUL_RB 5'00000 + assign \MUL_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_20 + assign \MUL_SI 16'0000000000000000 + assign \MUL_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_21 + assign \MUL_UI 16'0000000000000000 + assign \MUL_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \MUL_L + process $group_22 + assign \MUL_L 1'0 + assign \MUL_L { \opcode_in [21] } + sync init + end + process $group_23 + assign \MUL_SH32 5'00000 + assign \MUL_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_24 + assign \MUL_sh 6'000000 + assign \MUL_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_MB32 + process $group_25 + assign \MUL_MB32 5'00000 + assign \MUL_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_ME32 + process $group_26 + assign \MUL_ME32 5'00000 + assign \MUL_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_27 + assign \MUL_LI 24'000000000000000000000000 + assign \MUL_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \MUL_LK + process $group_28 + assign \MUL_LK 1'0 + assign \MUL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \MUL_AA + process $group_29 + assign \MUL_AA 1'0 + assign \MUL_AA { \opcode_in [1] } + sync init + end + process $group_30 + assign \MUL_Rc 1'0 + assign \MUL_Rc { \opcode_in [0] } + sync init + end + process $group_31 + assign \MUL_OE 1'0 + assign \MUL_OE { \opcode_in [10] } + sync init + end + process $group_32 + assign \MUL_BD 14'00000000000000 + assign \MUL_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \MUL_BF + process $group_33 + assign \MUL_BF 3'000 + assign \MUL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \MUL_CR + process $group_34 + assign \MUL_CR 10'0000000000 + assign \MUL_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_35 + assign \MUL_BB 5'00000 + assign \MUL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_36 + assign \MUL_BA 5'00000 + assign \MUL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_37 + assign \MUL_BT 5'00000 + assign \MUL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_38 + assign \MUL_FXM 8'00000000 + assign \MUL_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_BO + process $group_39 + assign \MUL_BO 5'00000 + assign \MUL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_40 + assign \MUL_BI 5'00000 + assign \MUL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \MUL_BH + process $group_41 + assign \MUL_BH 2'00 + assign \MUL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \MUL_D + process $group_42 + assign \MUL_D 16'0000000000000000 + assign \MUL_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_43 + assign \MUL_DS 14'00000000000000 + assign \MUL_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_TO + process $group_44 + assign \MUL_TO 5'00000 + assign \MUL_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_45 + assign \MUL_BC 5'00000 + assign \MUL_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_SH + process $group_46 + assign \MUL_SH 5'00000 + assign \MUL_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_ME + process $group_47 + assign \MUL_ME 5'00000 + assign \MUL_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \MUL_MB + process $group_48 + assign \MUL_MB 5'00000 + assign \MUL_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \MUL_SPR + process $group_49 + assign \MUL_SPR 10'0000000000 + assign \MUL_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_50 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_51 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_52 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_53 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_54 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_55 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_56 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_57 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_58 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_59 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_60 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_61 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_62 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_63 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_64 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_65 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_66 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_67 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_68 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_69 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_70 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_71 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_72 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_73 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_74 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_75 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_76 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_77 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_78 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_79 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_80 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_81 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_82 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_83 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_84 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_85 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_86 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_87 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_88 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_89 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_90 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_91 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_92 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_93 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_94 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_95 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_96 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_97 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_98 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_99 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_100 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_101 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_102 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_103 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_104 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_105 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_106 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_107 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_108 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_109 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_110 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_111 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_112 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_113 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_114 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_115 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_116 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_117 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_118 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_119 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_120 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_121 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_122 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_123 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_124 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_125 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_126 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_127 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_128 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_129 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_130 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_131 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_132 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_133 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_134 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_135 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_136 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_137 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_138 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_139 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_140 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_141 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_142 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_143 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_144 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_145 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_146 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_147 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_148 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_149 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_150 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_151 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_152 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_153 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_154 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_155 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_156 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_157 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_158 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_159 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_160 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_161 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_162 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_163 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_164 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_165 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_166 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_167 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_168 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_169 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_170 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_171 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_172 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_173 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_174 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_175 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_176 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_177 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_178 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_179 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_180 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_181 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_182 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_183 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_184 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_185 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_186 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_187 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_188 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_189 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_190 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_191 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_192 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_193 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_194 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_195 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_196 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_197 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_198 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_199 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_200 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_201 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_202 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_203 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_204 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_205 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_206 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_207 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_208 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_209 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_210 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_211 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_212 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_213 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_214 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_215 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_216 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_217 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_218 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_219 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_220 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_221 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_222 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_223 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_224 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_225 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_226 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_227 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_228 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_229 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_230 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_231 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_232 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_233 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_234 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_235 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_236 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_237 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_238 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_239 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_240 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_241 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_242 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_243 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_244 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_245 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_246 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_247 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_248 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_249 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_250 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_251 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_252 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_253 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_254 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_255 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_256 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_257 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_258 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_259 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_260 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_261 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_262 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_263 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_264 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_265 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_266 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_267 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_268 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_269 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_270 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_271 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_272 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_273 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_274 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_275 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_276 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_277 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_278 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_279 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_280 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_281 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_282 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_283 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_284 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_285 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_286 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_287 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_288 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_289 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_290 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_291 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_292 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_293 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_294 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_295 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_296 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_297 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_298 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_299 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_300 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_301 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_302 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_303 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_304 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_305 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_306 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_307 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_308 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_309 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_310 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_311 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_312 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_313 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_314 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_315 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_316 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_317 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_318 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_319 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_320 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_321 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_322 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_323 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_324 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_325 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_326 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_327 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_328 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_329 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_330 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_331 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_332 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_333 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_334 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_335 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_336 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_337 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_338 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_339 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_340 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_341 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \MUL_function_unit$1 11'00000000000 + connect \MUL_function_unit$2 11'00000000000 + connect \MUL_function_unit$3 11'00000000000 + connect \MUL_function_unit$4 11'00000000000 + connect \MUL_internal_op$5 7'0000000 + connect \MUL_internal_op$6 7'0000000 + connect \MUL_internal_op$7 7'0000000 + connect \MUL_internal_op$8 7'0000000 + connect \MUL_in2_sel$9 4'0000 + connect \MUL_in2_sel$10 4'0000 + connect \MUL_in2_sel$11 4'0000 + connect \MUL_in2_sel$12 4'0000 + connect \MUL_cr_in$13 3'000 + connect \MUL_cr_in$14 3'000 + connect \MUL_cr_in$15 3'000 + connect \MUL_cr_in$16 3'000 + connect \MUL_cr_out$17 3'000 + connect \MUL_cr_out$18 3'000 + connect \MUL_cr_out$19 3'000 + connect \MUL_cr_out$20 3'000 + connect \MUL_rc_sel$21 2'00 + connect \MUL_rc_sel$22 2'00 + connect \MUL_rc_sel$23 2'00 + connect \MUL_rc_sel$24 2'00 + connect \MUL_is_32b$25 1'0 + connect \MUL_is_32b$26 1'0 + connect \MUL_is_32b$27 1'0 + connect \MUL_is_32b$28 1'0 + connect \MUL_sgn$29 1'0 + connect \MUL_sgn$30 1'0 + connect \MUL_sgn$31 1'0 + connect \MUL_sgn$32 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_rc" +module \dec_rc$178 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \MUL_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_oe" +module \dec_oe$179 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \MUL_OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \MUL_OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in.ppick" +module \ppick$181 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in" +module \dec_cr_in$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$181 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \MUL_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \MUL_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \MUL_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \MUL_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \MUL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out.ppick" +module \ppick$183 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out" +module \dec_cr_out$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 5 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$183 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \MUL_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_bi" +module \dec_bi$184 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL" +module \dec_MUL + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \MUL_MUL__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 6 \MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 7 \MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \MUL_MUL__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_MUL_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_MUL_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_MUL_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_MUL_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_MUL_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$177 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_cr_in \dec_MUL_cr_in + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_sh \dec_MUL_sh + connect \MUL_LI \dec_MUL_LI + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_OE \dec_MUL_OE + connect \MUL_BD \dec_MUL_BD + connect \MUL_BB \dec_MUL_BB + connect \MUL_BA \dec_MUL_BA + connect \MUL_BT \dec_MUL_BT + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_BI \dec_MUL_BI + connect \MUL_DS \dec_MUL_DS + connect \MUL_BC \dec_MUL_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc$178 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \MUL_Rc \dec_MUL_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe$179 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \MUL_OE \dec_MUL_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$180 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_BB \dec_MUL_BB + connect \MUL_BA \dec_MUL_BA + connect \MUL_BT \dec_MUL_BT + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_BI \dec_MUL_BI + connect \MUL_BC \dec_MUL_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + cell \dec_cr_out$182 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \MUL_internal_op \dec_MUL_internal_op + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \MUL_FXM \dec_MUL_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi$184 \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_sh \dec_MUL_sh + connect \MUL_LI \dec_MUL_LI + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + end + process $group_0 + assign \MUL_MUL__insn 32'00000000000000000000000000000000 + assign \MUL_MUL__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_MUL_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_MUL_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_MUL_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_MUL_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \MUL_MUL__insn_type 7'0000000 + assign \MUL_MUL__insn_type \dec_MUL_internal_op + sync init + end + process $group_11 + assign \MUL_MUL__fn_unit 11'00000000000 + assign \MUL_MUL__fn_unit \dec_MUL_function_unit + sync init + end + process $group_12 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_MUL_in2_sel + sync init + end + process $group_13 + assign \MUL_MUL__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \MUL_MUL__imm_data__ok 1'0 + assign { \MUL_MUL__imm_data__ok \MUL_MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_15 + assign \MUL_MUL__rc__rc 1'0 + assign \MUL_MUL__rc__ok 1'0 + assign { \MUL_MUL__rc__ok \MUL_MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + sync init + end + process $group_17 + assign \MUL_MUL__oe__oe 1'0 + assign \MUL_MUL__oe__ok 1'0 + assign { \MUL_MUL__oe__ok \MUL_MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + sync init + end + process $group_19 + assign \MUL_MUL__write_cr0 1'0 + assign \MUL_MUL__write_cr0 \dec_cr_out_cr_bitfield_ok + sync init + end + process $group_20 + assign \MUL_MUL__is_32bit 1'0 + assign \MUL_MUL__is_32bit \dec_MUL_is_32b + sync init + end + process $group_21 + assign \MUL_MUL__is_signed 1'0 + assign \MUL_MUL__is_signed \dec_MUL_sgn + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec19" +module \SHIFT_ROT_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_1 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +module \SHIFT_ROT_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end + process $group_1 + assign \SHIFT_ROT_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_function_unit 11'00000001000 + end + sync init + end + process $group_2 + assign \SHIFT_ROT_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_internal_op 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_internal_op 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_internal_op 7'0111010 + end + sync init + end + process $group_3 + assign \SHIFT_ROT_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_in2_sel 4'0001 + end + sync init + end + process $group_4 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_cr_in 3'000 + end + sync init + end + process $group_5 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_cr_out 3'001 + end + sync init + end + process $group_6 + assign \SHIFT_ROT_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_rc_sel 2'10 + end + sync init + end + process $group_7 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_cry_in 2'00 + end + sync init + end + process $group_8 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_cry_out 1'0 + end + sync init + end + process $group_9 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_is_32b 1'0 + end + sync init + end + process $group_10 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0100 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0101 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0001 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0011 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0111 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1000 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \SHIFT_ROT_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub10" +module \SHIFT_ROT_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub28" +module \SHIFT_ROT_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub0" +module \SHIFT_ROT_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub26" +module \SHIFT_ROT_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \SHIFT_ROT_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_function_unit 11'00000001000 + end + sync init + end + process $group_2 + assign \SHIFT_ROT_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_internal_op 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_internal_op 7'0111101 + end + sync init + end + process $group_3 + assign \SHIFT_ROT_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_in2_sel 4'1010 + end + sync init + end + process $group_4 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cr_in 3'000 + end + sync init + end + process $group_5 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cr_out 3'001 + end + sync init + end + process $group_6 + assign \SHIFT_ROT_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_rc_sel 2'10 + end + sync init + end + process $group_7 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cry_in 2'00 + end + sync init + end + process $group_8 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cry_out 1'1 + end + sync init + end + process $group_9 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_is_32b 1'0 + end + sync init + end + process $group_10 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_sgn 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub19" +module \SHIFT_ROT_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub22" +module \SHIFT_ROT_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub9" +module \SHIFT_ROT_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub11" +module \SHIFT_ROT_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub27" +module \SHIFT_ROT_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \SHIFT_ROT_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_function_unit 11'00000001000 + end + sync init + end + process $group_2 + assign \SHIFT_ROT_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_internal_op 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_internal_op 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_internal_op 7'0111101 + end + sync init + end + process $group_3 + assign \SHIFT_ROT_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_in2_sel 4'0001 + end + sync init + end + process $group_4 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cr_in 3'000 + end + sync init + end + process $group_5 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cr_out 3'001 + end + sync init + end + process $group_6 + assign \SHIFT_ROT_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_rc_sel 2'10 + end + sync init + end + process $group_7 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cry_in 2'00 + end + sync init + end + process $group_8 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cry_out 1'0 + end + sync init + end + process $group_9 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_is_32b 1'0 + end + sync init + end + process $group_10 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub15" +module \SHIFT_ROT_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub20" +module \SHIFT_ROT_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub21" +module \SHIFT_ROT_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub23" +module \SHIFT_ROT_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub16" +module \SHIFT_ROT_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub18" +module \SHIFT_ROT_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub8" +module \SHIFT_ROT_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub24" +module \SHIFT_ROT_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \SHIFT_ROT_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_function_unit 11'00000001000 + end + sync init + end + process $group_2 + assign \SHIFT_ROT_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_internal_op 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_internal_op 7'0111101 + end + sync init + end + process $group_3 + assign \SHIFT_ROT_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_in2_sel 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_in2_sel 4'0001 + end + sync init + end + process $group_4 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cr_in 3'000 + end + sync init + end + process $group_5 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cr_out 3'001 + end + sync init + end + process $group_6 + assign \SHIFT_ROT_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_rc_sel 2'10 + end + sync init + end + process $group_7 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cry_in 2'00 + end + sync init + end + process $group_8 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_cry_out 1'0 + end + sync init + end + process $group_9 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_is_32b 1'1 + end + sync init + end + process $group_10 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \SHIFT_ROT_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \SHIFT_ROT_sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \SHIFT_ROT_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub4" +module \SHIFT_ROT_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +module \SHIFT_ROT_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 3 \SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 6 \SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 8 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub10_opcode_in + cell \SHIFT_ROT_dec_sub10 \SHIFT_ROT_dec_sub10 + connect \opcode_in \SHIFT_ROT_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub28_opcode_in + cell \SHIFT_ROT_dec_sub28 \SHIFT_ROT_dec_sub28 + connect \opcode_in \SHIFT_ROT_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub0_opcode_in + cell \SHIFT_ROT_dec_sub0 \SHIFT_ROT_dec_sub0 + connect \opcode_in \SHIFT_ROT_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub26_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_dec_sub26_SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_dec_sub26_SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_dec_sub26_SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec_sub26_SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub26_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub26_SHIFT_ROT_sgn + cell \SHIFT_ROT_dec_sub26 \SHIFT_ROT_dec_sub26 + connect \opcode_in \SHIFT_ROT_dec_sub26_opcode_in + connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub26_SHIFT_ROT_function_unit + connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub26_SHIFT_ROT_internal_op + connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_out + connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_out + connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub26_SHIFT_ROT_is_32b + connect \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub26_SHIFT_ROT_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub19_opcode_in + cell \SHIFT_ROT_dec_sub19 \SHIFT_ROT_dec_sub19 + connect \opcode_in \SHIFT_ROT_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub22_opcode_in + cell \SHIFT_ROT_dec_sub22 \SHIFT_ROT_dec_sub22 + connect \opcode_in \SHIFT_ROT_dec_sub22_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub9_opcode_in + cell \SHIFT_ROT_dec_sub9 \SHIFT_ROT_dec_sub9 + connect \opcode_in \SHIFT_ROT_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub11_opcode_in + cell \SHIFT_ROT_dec_sub11 \SHIFT_ROT_dec_sub11 + connect \opcode_in \SHIFT_ROT_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_dec_sub27_SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_dec_sub27_SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_dec_sub27_SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec_sub27_SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub27_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub27_SHIFT_ROT_sgn + cell \SHIFT_ROT_dec_sub27 \SHIFT_ROT_dec_sub27 + connect \opcode_in \SHIFT_ROT_dec_sub27_opcode_in + connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub27_SHIFT_ROT_function_unit + connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub27_SHIFT_ROT_internal_op + connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_out + connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_out + connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub27_SHIFT_ROT_is_32b + connect \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub27_SHIFT_ROT_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub15_opcode_in + cell \SHIFT_ROT_dec_sub15 \SHIFT_ROT_dec_sub15 + connect \opcode_in \SHIFT_ROT_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub20_opcode_in + cell \SHIFT_ROT_dec_sub20 \SHIFT_ROT_dec_sub20 + connect \opcode_in \SHIFT_ROT_dec_sub20_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub21_opcode_in + cell \SHIFT_ROT_dec_sub21 \SHIFT_ROT_dec_sub21 + connect \opcode_in \SHIFT_ROT_dec_sub21_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub23_opcode_in + cell \SHIFT_ROT_dec_sub23 \SHIFT_ROT_dec_sub23 + connect \opcode_in \SHIFT_ROT_dec_sub23_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub16_opcode_in + cell \SHIFT_ROT_dec_sub16 \SHIFT_ROT_dec_sub16 + connect \opcode_in \SHIFT_ROT_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub18_opcode_in + cell \SHIFT_ROT_dec_sub18 \SHIFT_ROT_dec_sub18 + connect \opcode_in \SHIFT_ROT_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub8_opcode_in + cell \SHIFT_ROT_dec_sub8 \SHIFT_ROT_dec_sub8 + connect \opcode_in \SHIFT_ROT_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub24_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_dec_sub24_SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_dec_sub24_SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_dec_sub24_SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec_sub24_SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub24_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec_sub24_SHIFT_ROT_sgn + cell \SHIFT_ROT_dec_sub24 \SHIFT_ROT_dec_sub24 + connect \opcode_in \SHIFT_ROT_dec_sub24_opcode_in + connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub24_SHIFT_ROT_function_unit + connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub24_SHIFT_ROT_internal_op + connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_out + connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_out + connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub24_SHIFT_ROT_is_32b + connect \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub24_SHIFT_ROT_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec_sub4_opcode_in + cell \SHIFT_ROT_dec_sub4 \SHIFT_ROT_dec_sub4 + connect \opcode_in \SHIFT_ROT_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \SHIFT_ROT_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \SHIFT_ROT_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \SHIFT_ROT_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \SHIFT_ROT_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \SHIFT_ROT_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \SHIFT_ROT_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \SHIFT_ROT_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \SHIFT_ROT_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \SHIFT_ROT_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \SHIFT_ROT_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \SHIFT_ROT_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \SHIFT_ROT_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \SHIFT_ROT_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \SHIFT_ROT_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \SHIFT_ROT_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \SHIFT_ROT_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \SHIFT_ROT_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \SHIFT_ROT_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$14 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$15 + process $group_20 + assign \SHIFT_ROT_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub26_SHIFT_ROT_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub27_SHIFT_ROT_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub24_SHIFT_ROT_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$15 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$30 + process $group_21 + assign \SHIFT_ROT_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub26_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub27_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub24_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$30 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$31 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$32 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$33 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$34 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$35 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$36 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$37 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$38 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$39 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$40 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$41 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$42 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$43 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$44 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$45 + process $group_22 + assign \SHIFT_ROT_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$45 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$46 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$47 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$48 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$49 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$50 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$51 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$52 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$53 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$54 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$55 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$56 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$57 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$58 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$59 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$60 + process $group_23 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$60 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$61 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$62 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$63 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$64 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$65 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$66 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$67 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$68 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$69 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$70 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$71 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$72 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$73 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$74 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$75 + process $group_24 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$75 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$76 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$77 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$78 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$79 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$80 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$81 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$82 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$83 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$84 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$85 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$86 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$87 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$88 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$89 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$90 + process $group_25 + assign \SHIFT_ROT_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$90 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$91 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$92 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$93 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$94 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$95 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$96 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$97 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$98 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$99 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$100 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$101 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$102 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$103 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$104 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$105 + process $group_26 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$105 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$120 + process $group_27 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$120 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$135 + process $group_28 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub26_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub27_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub24_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$135 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$150 + process $group_29 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub26_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub27_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub24_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$150 + end + sync init + end + connect \SHIFT_ROT_function_unit$1 11'00000000000 + connect \SHIFT_ROT_function_unit$2 11'00000000000 + connect \SHIFT_ROT_function_unit$3 11'00000000000 + connect \SHIFT_ROT_function_unit$4 11'00000000000 + connect \SHIFT_ROT_function_unit$5 11'00000000000 + connect \SHIFT_ROT_function_unit$6 11'00000000000 + connect \SHIFT_ROT_function_unit$7 11'00000000000 + connect \SHIFT_ROT_function_unit$8 11'00000000000 + connect \SHIFT_ROT_function_unit$9 11'00000000000 + connect \SHIFT_ROT_function_unit$10 11'00000000000 + connect \SHIFT_ROT_function_unit$11 11'00000000000 + connect \SHIFT_ROT_function_unit$12 11'00000000000 + connect \SHIFT_ROT_function_unit$13 11'00000000000 + connect \SHIFT_ROT_function_unit$14 11'00000000000 + connect \SHIFT_ROT_function_unit$15 11'00000000000 + connect \SHIFT_ROT_internal_op$16 7'0000000 + connect \SHIFT_ROT_internal_op$17 7'0000000 + connect \SHIFT_ROT_internal_op$18 7'0000000 + connect \SHIFT_ROT_internal_op$19 7'0000000 + connect \SHIFT_ROT_internal_op$20 7'0000000 + connect \SHIFT_ROT_internal_op$21 7'0000000 + connect \SHIFT_ROT_internal_op$22 7'0000000 + connect \SHIFT_ROT_internal_op$23 7'0000000 + connect \SHIFT_ROT_internal_op$24 7'0000000 + connect \SHIFT_ROT_internal_op$25 7'0000000 + connect \SHIFT_ROT_internal_op$26 7'0000000 + connect \SHIFT_ROT_internal_op$27 7'0000000 + connect \SHIFT_ROT_internal_op$28 7'0000000 + connect \SHIFT_ROT_internal_op$29 7'0000000 + connect \SHIFT_ROT_internal_op$30 7'0000000 + connect \SHIFT_ROT_in2_sel$31 4'0000 + connect \SHIFT_ROT_in2_sel$32 4'0000 + connect \SHIFT_ROT_in2_sel$33 4'0000 + connect \SHIFT_ROT_in2_sel$34 4'0000 + connect \SHIFT_ROT_in2_sel$35 4'0000 + connect \SHIFT_ROT_in2_sel$36 4'0000 + connect \SHIFT_ROT_in2_sel$37 4'0000 + connect \SHIFT_ROT_in2_sel$38 4'0000 + connect \SHIFT_ROT_in2_sel$39 4'0000 + connect \SHIFT_ROT_in2_sel$40 4'0000 + connect \SHIFT_ROT_in2_sel$41 4'0000 + connect \SHIFT_ROT_in2_sel$42 4'0000 + connect \SHIFT_ROT_in2_sel$43 4'0000 + connect \SHIFT_ROT_in2_sel$44 4'0000 + connect \SHIFT_ROT_in2_sel$45 4'0000 + connect \SHIFT_ROT_cr_in$46 3'000 + connect \SHIFT_ROT_cr_in$47 3'000 + connect \SHIFT_ROT_cr_in$48 3'000 + connect \SHIFT_ROT_cr_in$49 3'000 + connect \SHIFT_ROT_cr_in$50 3'000 + connect \SHIFT_ROT_cr_in$51 3'000 + connect \SHIFT_ROT_cr_in$52 3'000 + connect \SHIFT_ROT_cr_in$53 3'000 + connect \SHIFT_ROT_cr_in$54 3'000 + connect \SHIFT_ROT_cr_in$55 3'000 + connect \SHIFT_ROT_cr_in$56 3'000 + connect \SHIFT_ROT_cr_in$57 3'000 + connect \SHIFT_ROT_cr_in$58 3'000 + connect \SHIFT_ROT_cr_in$59 3'000 + connect \SHIFT_ROT_cr_in$60 3'000 + connect \SHIFT_ROT_cr_out$61 3'000 + connect \SHIFT_ROT_cr_out$62 3'000 + connect \SHIFT_ROT_cr_out$63 3'000 + connect \SHIFT_ROT_cr_out$64 3'000 + connect \SHIFT_ROT_cr_out$65 3'000 + connect \SHIFT_ROT_cr_out$66 3'000 + connect \SHIFT_ROT_cr_out$67 3'000 + connect \SHIFT_ROT_cr_out$68 3'000 + connect \SHIFT_ROT_cr_out$69 3'000 + connect \SHIFT_ROT_cr_out$70 3'000 + connect \SHIFT_ROT_cr_out$71 3'000 + connect \SHIFT_ROT_cr_out$72 3'000 + connect \SHIFT_ROT_cr_out$73 3'000 + connect \SHIFT_ROT_cr_out$74 3'000 + connect \SHIFT_ROT_cr_out$75 3'000 + connect \SHIFT_ROT_rc_sel$76 2'00 + connect \SHIFT_ROT_rc_sel$77 2'00 + connect \SHIFT_ROT_rc_sel$78 2'00 + connect \SHIFT_ROT_rc_sel$79 2'00 + connect \SHIFT_ROT_rc_sel$80 2'00 + connect \SHIFT_ROT_rc_sel$81 2'00 + connect \SHIFT_ROT_rc_sel$82 2'00 + connect \SHIFT_ROT_rc_sel$83 2'00 + connect \SHIFT_ROT_rc_sel$84 2'00 + connect \SHIFT_ROT_rc_sel$85 2'00 + connect \SHIFT_ROT_rc_sel$86 2'00 + connect \SHIFT_ROT_rc_sel$87 2'00 + connect \SHIFT_ROT_rc_sel$88 2'00 + connect \SHIFT_ROT_rc_sel$89 2'00 + connect \SHIFT_ROT_rc_sel$90 2'00 + connect \SHIFT_ROT_cry_in$91 2'00 + connect \SHIFT_ROT_cry_in$92 2'00 + connect \SHIFT_ROT_cry_in$93 2'00 + connect \SHIFT_ROT_cry_in$94 2'00 + connect \SHIFT_ROT_cry_in$95 2'00 + connect \SHIFT_ROT_cry_in$96 2'00 + connect \SHIFT_ROT_cry_in$97 2'00 + connect \SHIFT_ROT_cry_in$98 2'00 + connect \SHIFT_ROT_cry_in$99 2'00 + connect \SHIFT_ROT_cry_in$100 2'00 + connect \SHIFT_ROT_cry_in$101 2'00 + connect \SHIFT_ROT_cry_in$102 2'00 + connect \SHIFT_ROT_cry_in$103 2'00 + connect \SHIFT_ROT_cry_in$104 2'00 + connect \SHIFT_ROT_cry_in$105 2'00 + connect \SHIFT_ROT_cry_out$106 1'0 + connect \SHIFT_ROT_cry_out$107 1'0 + connect \SHIFT_ROT_cry_out$108 1'0 + connect \SHIFT_ROT_cry_out$109 1'0 + connect \SHIFT_ROT_cry_out$110 1'0 + connect \SHIFT_ROT_cry_out$111 1'0 + connect \SHIFT_ROT_cry_out$112 1'0 + connect \SHIFT_ROT_cry_out$113 1'0 + connect \SHIFT_ROT_cry_out$114 1'0 + connect \SHIFT_ROT_cry_out$115 1'0 + connect \SHIFT_ROT_cry_out$116 1'0 + connect \SHIFT_ROT_cry_out$117 1'0 + connect \SHIFT_ROT_cry_out$118 1'0 + connect \SHIFT_ROT_cry_out$119 1'0 + connect \SHIFT_ROT_cry_out$120 1'0 + connect \SHIFT_ROT_is_32b$121 1'0 + connect \SHIFT_ROT_is_32b$122 1'0 + connect \SHIFT_ROT_is_32b$123 1'0 + connect \SHIFT_ROT_is_32b$124 1'0 + connect \SHIFT_ROT_is_32b$125 1'0 + connect \SHIFT_ROT_is_32b$126 1'0 + connect \SHIFT_ROT_is_32b$127 1'0 + connect \SHIFT_ROT_is_32b$128 1'0 + connect \SHIFT_ROT_is_32b$129 1'0 + connect \SHIFT_ROT_is_32b$130 1'0 + connect \SHIFT_ROT_is_32b$131 1'0 + connect \SHIFT_ROT_is_32b$132 1'0 + connect \SHIFT_ROT_is_32b$133 1'0 + connect \SHIFT_ROT_is_32b$134 1'0 + connect \SHIFT_ROT_is_32b$135 1'0 + connect \SHIFT_ROT_sgn$136 1'0 + connect \SHIFT_ROT_sgn$137 1'0 + connect \SHIFT_ROT_sgn$138 1'0 + connect \SHIFT_ROT_sgn$139 1'0 + connect \SHIFT_ROT_sgn$140 1'0 + connect \SHIFT_ROT_sgn$141 1'0 + connect \SHIFT_ROT_sgn$142 1'0 + connect \SHIFT_ROT_sgn$143 1'0 + connect \SHIFT_ROT_sgn$144 1'0 + connect \SHIFT_ROT_sgn$145 1'0 + connect \SHIFT_ROT_sgn$146 1'0 + connect \SHIFT_ROT_sgn$147 1'0 + connect \SHIFT_ROT_sgn$148 1'0 + connect \SHIFT_ROT_sgn$149 1'0 + connect \SHIFT_ROT_sgn$150 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec58" +module \SHIFT_ROT_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec62" +module \SHIFT_ROT_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec" +module \dec$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \SHIFT_ROT_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \SHIFT_ROT_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 8 \SHIFT_ROT_in2_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 13 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 14 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 15 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 16 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 17 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 18 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 19 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 20 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 21 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 22 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 23 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 24 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 25 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 26 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 27 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 28 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 29 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 30 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec19_opcode_in + cell \SHIFT_ROT_dec19 \SHIFT_ROT_dec19 + connect \opcode_in \SHIFT_ROT_dec19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec30_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_dec30_SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec30_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec30_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec30_SHIFT_ROT_sgn + cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 + connect \opcode_in \SHIFT_ROT_dec30_opcode_in + connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_function_unit + connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_internal_op + connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_cr_out + connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_cry_out + connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_is_32b + connect \SHIFT_ROT_sgn \SHIFT_ROT_dec30_SHIFT_ROT_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_dec31_SHIFT_ROT_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_rc_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec31_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec31_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_dec31_SHIFT_ROT_sgn + cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 + connect \opcode_in \SHIFT_ROT_dec31_opcode_in + connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_function_unit + connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_internal_op + connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_cr_out + connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_cry_out + connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_is_32b + connect \SHIFT_ROT_sgn \SHIFT_ROT_dec31_SHIFT_ROT_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec58_opcode_in + cell \SHIFT_ROT_dec58 \SHIFT_ROT_dec58 + connect \opcode_in \SHIFT_ROT_dec58_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \SHIFT_ROT_dec62_opcode_in + cell \SHIFT_ROT_dec62 \SHIFT_ROT_dec62 + connect \opcode_in \SHIFT_ROT_dec62_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \SHIFT_ROT_dec19_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \SHIFT_ROT_dec30_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \SHIFT_ROT_dec31_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \SHIFT_ROT_dec58_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \SHIFT_ROT_dec62_opcode_in 32'00000000000000000000000000000000 + assign \SHIFT_ROT_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \SHIFT_ROT_function_unit$3 + process $group_6 + assign \SHIFT_ROT_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_function_unit 11'00000001000 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \SHIFT_ROT_internal_op$6 + process $group_7 + assign \SHIFT_ROT_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_internal_op 7'0111000 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$7 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$8 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \SHIFT_ROT_in2_sel$9 + process $group_8 + assign \SHIFT_ROT_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_in2_sel 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_in2_sel 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_in2_sel 4'0001 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$10 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$11 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_in$12 + process $group_9 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_cr_in 3'000 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$13 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$14 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \SHIFT_ROT_cr_out$15 + process $group_10 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_cr_out 3'000 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$16 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$17 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_rc_sel$18 + process $group_11 + assign \SHIFT_ROT_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_rc_sel 2'10 + end + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$19 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$20 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \SHIFT_ROT_cry_in$21 + process $group_12 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_cry_in 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_cry_out$24 + process $group_13 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_cry_out 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_is_32b$27 + process $group_14 + assign \SHIFT_ROT_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_is_32b 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \SHIFT_ROT_sgn$30 + process $group_15 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \SHIFT_ROT_sgn \SHIFT_ROT_dec30_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \SHIFT_ROT_sgn \SHIFT_ROT_dec31_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \SHIFT_ROT_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \SHIFT_ROT_sgn 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$31 + process $group_16 + assign \opcode_switch$31 32'00000000000000000000000000000000 + assign \opcode_switch$31 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $33 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $32 + end + process $group_17 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_RS + process $group_18 + assign \SHIFT_ROT_RS 5'00000 + assign \SHIFT_ROT_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_RT + process $group_19 + assign \SHIFT_ROT_RT 5'00000 + assign \SHIFT_ROT_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_RA + process $group_20 + assign \SHIFT_ROT_RA 5'00000 + assign \SHIFT_ROT_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_RB + process $group_21 + assign \SHIFT_ROT_RB 5'00000 + assign \SHIFT_ROT_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_22 + assign \SHIFT_ROT_SI 16'0000000000000000 + assign \SHIFT_ROT_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_23 + assign \SHIFT_ROT_UI 16'0000000000000000 + assign \SHIFT_ROT_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \SHIFT_ROT_L + process $group_24 + assign \SHIFT_ROT_L 1'0 + assign \SHIFT_ROT_L { \opcode_in [21] } + sync init + end + process $group_25 + assign \SHIFT_ROT_SH32 5'00000 + assign \SHIFT_ROT_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_26 + assign \SHIFT_ROT_sh 6'000000 + assign \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_MB32 + process $group_27 + assign \SHIFT_ROT_MB32 5'00000 + assign \SHIFT_ROT_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_ME32 + process $group_28 + assign \SHIFT_ROT_ME32 5'00000 + assign \SHIFT_ROT_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_29 + assign \SHIFT_ROT_LI 24'000000000000000000000000 + assign \SHIFT_ROT_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \SHIFT_ROT_LK + process $group_30 + assign \SHIFT_ROT_LK 1'0 + assign \SHIFT_ROT_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \SHIFT_ROT_AA + process $group_31 + assign \SHIFT_ROT_AA 1'0 + assign \SHIFT_ROT_AA { \opcode_in [1] } + sync init + end + process $group_32 + assign \SHIFT_ROT_Rc 1'0 + assign \SHIFT_ROT_Rc { \opcode_in [0] } + sync init + end + process $group_33 + assign \SHIFT_ROT_OE 1'0 + assign \SHIFT_ROT_OE { \opcode_in [10] } + sync init + end + process $group_34 + assign \SHIFT_ROT_BD 14'00000000000000 + assign \SHIFT_ROT_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \SHIFT_ROT_BF + process $group_35 + assign \SHIFT_ROT_BF 3'000 + assign \SHIFT_ROT_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \SHIFT_ROT_CR + process $group_36 + assign \SHIFT_ROT_CR 10'0000000000 + assign \SHIFT_ROT_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_37 + assign \SHIFT_ROT_BB 5'00000 + assign \SHIFT_ROT_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_38 + assign \SHIFT_ROT_BA 5'00000 + assign \SHIFT_ROT_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_39 + assign \SHIFT_ROT_BT 5'00000 + assign \SHIFT_ROT_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_40 + assign \SHIFT_ROT_FXM 8'00000000 + assign \SHIFT_ROT_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_BO + process $group_41 + assign \SHIFT_ROT_BO 5'00000 + assign \SHIFT_ROT_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_42 + assign \SHIFT_ROT_BI 5'00000 + assign \SHIFT_ROT_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \SHIFT_ROT_BH + process $group_43 + assign \SHIFT_ROT_BH 2'00 + assign \SHIFT_ROT_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \SHIFT_ROT_D + process $group_44 + assign \SHIFT_ROT_D 16'0000000000000000 + assign \SHIFT_ROT_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_45 + assign \SHIFT_ROT_DS 14'00000000000000 + assign \SHIFT_ROT_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_TO + process $group_46 + assign \SHIFT_ROT_TO 5'00000 + assign \SHIFT_ROT_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_47 + assign \SHIFT_ROT_BC 5'00000 + assign \SHIFT_ROT_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_SH + process $group_48 + assign \SHIFT_ROT_SH 5'00000 + assign \SHIFT_ROT_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_ME + process $group_49 + assign \SHIFT_ROT_ME 5'00000 + assign \SHIFT_ROT_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SHIFT_ROT_MB + process $group_50 + assign \SHIFT_ROT_MB 5'00000 + assign \SHIFT_ROT_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \SHIFT_ROT_SPR + process $group_51 + assign \SHIFT_ROT_SPR 10'0000000000 + assign \SHIFT_ROT_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_52 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_53 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_54 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_55 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_56 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_57 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_58 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_59 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_60 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_61 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_62 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_63 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_64 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_65 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_66 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_67 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_68 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_69 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_70 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_71 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_72 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_73 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_74 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_75 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_76 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_77 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_78 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_79 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_80 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_81 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_82 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_83 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_84 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_85 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_86 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_87 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_88 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_89 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_90 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_91 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_92 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_93 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_94 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_95 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_96 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_97 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_98 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_99 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_100 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_101 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_102 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_103 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_104 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_105 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_106 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_107 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_108 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_109 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_110 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_111 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_112 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_113 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_114 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_115 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_116 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_117 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_118 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_119 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_120 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_121 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_122 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_123 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_124 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_125 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_126 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_127 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_128 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_129 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_130 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_131 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_132 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_133 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_134 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_135 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_136 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_137 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_138 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_139 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_140 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_141 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_142 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_143 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_144 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_145 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_146 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_147 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_148 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_149 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_150 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_151 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_152 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_153 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_154 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_155 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_156 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_157 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_158 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_159 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_160 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_161 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_162 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_163 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_164 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_165 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_166 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_167 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_168 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_169 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_170 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_171 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_172 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_173 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_174 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_175 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_176 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_177 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_178 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_179 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_180 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_181 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_182 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_183 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_184 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_185 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_186 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_187 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_188 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_189 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_190 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_191 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_192 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_193 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_194 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_195 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_196 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_197 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_198 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_199 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_200 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_201 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_202 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_203 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_204 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_205 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_206 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_207 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_208 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_209 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_210 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_211 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_212 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_213 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_214 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_215 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_216 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_217 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_218 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_219 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_220 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_221 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_222 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_223 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_224 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_225 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_226 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_227 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_228 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_229 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_230 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_231 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_232 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_233 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_234 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_235 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_236 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_237 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_238 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_239 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_240 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_241 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_242 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_243 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_244 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_245 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_246 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_247 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_248 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_249 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_250 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_251 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_252 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_253 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_254 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_255 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_256 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_257 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_258 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_259 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_260 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_261 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_262 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_263 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_264 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_265 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_266 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_267 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_268 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_269 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_270 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_271 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_272 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_273 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_274 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_275 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_276 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_277 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_278 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_279 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_280 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_281 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_282 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_283 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_284 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_285 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_286 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_287 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_288 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_289 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_290 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_291 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_292 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_293 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_294 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_295 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_296 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_297 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_298 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_299 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_300 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_301 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_302 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_303 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_304 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_305 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_306 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_307 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_308 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_309 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_310 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_311 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_312 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_313 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_314 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_315 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_316 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_317 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_318 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_319 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_320 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_321 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_322 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_323 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_324 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_325 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_326 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_327 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_328 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_329 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_330 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_331 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_332 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_333 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_334 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_335 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_336 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_337 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_338 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_339 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_340 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_341 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_342 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_343 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \SHIFT_ROT_function_unit$1 11'00000000000 + connect \SHIFT_ROT_function_unit$2 11'00000000000 + connect \SHIFT_ROT_function_unit$3 11'00000000000 + connect \SHIFT_ROT_internal_op$4 7'0000000 + connect \SHIFT_ROT_internal_op$5 7'0000000 + connect \SHIFT_ROT_internal_op$6 7'0000000 + connect \SHIFT_ROT_in2_sel$7 4'0000 + connect \SHIFT_ROT_in2_sel$8 4'0000 + connect \SHIFT_ROT_in2_sel$9 4'0000 + connect \SHIFT_ROT_cr_in$10 3'000 + connect \SHIFT_ROT_cr_in$11 3'000 + connect \SHIFT_ROT_cr_in$12 3'000 + connect \SHIFT_ROT_cr_out$13 3'000 + connect \SHIFT_ROT_cr_out$14 3'000 + connect \SHIFT_ROT_cr_out$15 3'000 + connect \SHIFT_ROT_rc_sel$16 2'00 + connect \SHIFT_ROT_rc_sel$17 2'00 + connect \SHIFT_ROT_rc_sel$18 2'00 + connect \SHIFT_ROT_cry_in$19 2'00 + connect \SHIFT_ROT_cry_in$20 2'00 + connect \SHIFT_ROT_cry_in$21 2'00 + connect \SHIFT_ROT_cry_out$22 1'0 + connect \SHIFT_ROT_cry_out$23 1'0 + connect \SHIFT_ROT_cry_out$24 1'0 + connect \SHIFT_ROT_is_32b$25 1'0 + connect \SHIFT_ROT_is_32b$26 1'0 + connect \SHIFT_ROT_is_32b$27 1'0 + connect \SHIFT_ROT_sgn$28 1'0 + connect \SHIFT_ROT_sgn$29 1'0 + connect \SHIFT_ROT_sgn$30 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_rc" +module \dec_rc$186 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \SHIFT_ROT_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_oe" +module \dec_oe$187 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \SHIFT_ROT_OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \SHIFT_ROT_OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in.ppick" +module \ppick$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in" +module \dec_cr_in$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$189 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \SHIFT_ROT_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \SHIFT_ROT_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \SHIFT_ROT_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \SHIFT_ROT_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \SHIFT_ROT_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out.ppick" +module \ppick$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out" +module \dec_cr_out$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 5 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$191 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \SHIFT_ROT_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_bi" +module \dec_bi$192 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT" +module \dec_SHIFT_ROT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT_SHIFT_ROT__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 6 \SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 7 \SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 11 \SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \SHIFT_ROT_SHIFT_ROT__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_SHIFT_ROT_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_SHIFT_ROT_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_SHIFT_ROT_in2_sel + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$185 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc$186 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe$187 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$188 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + cell \dec_cr_out$190 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi$192 \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + end + process $group_0 + assign \SHIFT_ROT_SHIFT_ROT__insn 32'00000000000000000000000000000000 + assign \SHIFT_ROT_SHIFT_ROT__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \SHIFT_ROT_SHIFT_ROT__insn_type 7'0000000 + assign \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op + sync init + end + process $group_11 + assign \SHIFT_ROT_SHIFT_ROT__fn_unit 11'00000000000 + assign \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit + sync init + end + process $group_12 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + sync init + end + process $group_13 + assign \SHIFT_ROT_SHIFT_ROT__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \SHIFT_ROT_SHIFT_ROT__imm_data__ok 1'0 + assign { \SHIFT_ROT_SHIFT_ROT__imm_data__ok \SHIFT_ROT_SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_15 + assign \SHIFT_ROT_SHIFT_ROT__rc__rc 1'0 + assign \SHIFT_ROT_SHIFT_ROT__rc__ok 1'0 + assign { \SHIFT_ROT_SHIFT_ROT__rc__ok \SHIFT_ROT_SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + sync init + end + process $group_17 + assign \SHIFT_ROT_SHIFT_ROT__oe__oe 1'0 + assign \SHIFT_ROT_SHIFT_ROT__oe__ok 1'0 + assign { \SHIFT_ROT_SHIFT_ROT__oe__ok \SHIFT_ROT_SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + sync init + end + process $group_19 + assign \SHIFT_ROT_SHIFT_ROT__write_cr0 1'0 + assign \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok + sync init + end + process $group_20 + assign \SHIFT_ROT_SHIFT_ROT__input_cr 1'0 + assign \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + sync init + end + process $group_21 + assign \SHIFT_ROT_SHIFT_ROT__output_cr 1'0 + assign \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + sync init + end + process $group_22 + assign \SHIFT_ROT_SHIFT_ROT__input_carry 2'00 + assign \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + sync init + end + process $group_23 + assign \SHIFT_ROT_SHIFT_ROT__output_carry 1'0 + assign \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + sync init + end + process $group_24 + assign \SHIFT_ROT_SHIFT_ROT__is_32bit 1'0 + assign \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + sync init + end + process $group_25 + assign \SHIFT_ROT_SHIFT_ROT__is_signed 1'0 + assign \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec19" +module \LDST_dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch$1 + process $group_1 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec30" +module \LDST_dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub10" +module \LDST_dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub28" +module \LDST_dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub0" +module \LDST_dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub26" +module \LDST_dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub19" +module \LDST_dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub22" +module \LDST_dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + process $group_2 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_internal_op 7'0100110 + end + sync init + end + process $group_3 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_in1_sel 3'010 + end + sync init + end + process $group_4 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_ldst_len 4'0100 + end + sync init + end + process $group_8 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_upd 2'00 + end + sync init + end + process $group_9 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_rc_sel 2'00 + end + sync init + end + process $group_10 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_br 1'0 + end + sync init + end + process $group_11 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_sgn_ext 1'0 + end + sync init + end + process $group_12 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_is_32b 1'0 + end + sync init + end + process $group_13 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10101 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10110 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub9" +module \LDST_dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub11" +module \LDST_dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub27" +module \LDST_dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub15" +module \LDST_dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub20" +module \LDST_dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + process $group_2 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_internal_op 7'0100110 + end + sync init + end + process $group_3 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_in1_sel 3'010 + end + sync init + end + process $group_4 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_ldst_len 4'1000 + end + sync init + end + process $group_8 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_upd 2'00 + end + sync init + end + process $group_9 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_rc_sel 2'00 + end + sync init + end + process $group_10 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_br 1'1 + end + sync init + end + process $group_11 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_sgn_ext 1'0 + end + sync init + end + process $group_12 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_is_32b 1'0 + end + sync init + end + process $group_13 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10100 + assign \LDST_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub21" +module \LDST_dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + process $group_2 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_internal_op 7'0100110 + end + sync init + end + process $group_3 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_in1_sel 3'010 + end + sync init + end + process $group_4 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_ldst_len 4'0100 + end + sync init + end + process $group_8 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_upd 2'10 + end + sync init + end + process $group_9 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_rc_sel 2'00 + end + sync init + end + process $group_10 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_br 1'0 + end + sync init + end + process $group_11 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_sgn_ext 1'0 + end + sync init + end + process $group_12 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_is_32b 1'0 + end + sync init + end + process $group_13 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11110 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11111 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11101 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11100 + assign \LDST_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub23" +module \LDST_dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + process $group_2 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_internal_op 7'0100110 + end + sync init + end + process $group_3 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_in1_sel 3'010 + end + sync init + end + process $group_4 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_in2_sel 4'0001 + end + sync init + end + process $group_5 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_ldst_len 4'0100 + end + sync init + end + process $group_8 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_upd 2'00 + end + sync init + end + process $group_9 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_rc_sel 2'00 + end + sync init + end + process $group_10 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_br 1'0 + end + sync init + end + process $group_11 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_sgn_ext 1'0 + end + sync init + end + process $group_12 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_is_32b 1'0 + end + sync init + end + process $group_13 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \LDST_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub16" +module \LDST_dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub18" +module \LDST_dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub8" +module \LDST_dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub24" +module \LDST_dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub4" +module \LDST_dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31" +module \LDST_dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub10_opcode_in + cell \LDST_dec_sub10 \LDST_dec_sub10 + connect \opcode_in \LDST_dec_sub10_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub28_opcode_in + cell \LDST_dec_sub28 \LDST_dec_sub28 + connect \opcode_in \LDST_dec_sub28_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub0_opcode_in + cell \LDST_dec_sub0 \LDST_dec_sub0 + connect \opcode_in \LDST_dec_sub0_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub26_opcode_in + cell \LDST_dec_sub26 \LDST_dec_sub26 + connect \opcode_in \LDST_dec_sub26_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub19_opcode_in + cell \LDST_dec_sub19 \LDST_dec_sub19 + connect \opcode_in \LDST_dec_sub19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub22_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec_sub22_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec_sub22_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub22_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub22_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub22_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub22_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub22_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub22_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub22_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub22_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub22_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub22_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub22_LDST_sgn + cell \LDST_dec_sub22 \LDST_dec_sub22 + connect \opcode_in \LDST_dec_sub22_opcode_in + connect \LDST_function_unit \LDST_dec_sub22_LDST_function_unit + connect \LDST_internal_op \LDST_dec_sub22_LDST_internal_op + connect \LDST_in1_sel \LDST_dec_sub22_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec_sub22_LDST_in2_sel + connect \LDST_cr_in \LDST_dec_sub22_LDST_cr_in + connect \LDST_cr_out \LDST_dec_sub22_LDST_cr_out + connect \LDST_ldst_len \LDST_dec_sub22_LDST_ldst_len + connect \LDST_upd \LDST_dec_sub22_LDST_upd + connect \LDST_rc_sel \LDST_dec_sub22_LDST_rc_sel + connect \LDST_br \LDST_dec_sub22_LDST_br + connect \LDST_sgn_ext \LDST_dec_sub22_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec_sub22_LDST_is_32b + connect \LDST_sgn \LDST_dec_sub22_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub9_opcode_in + cell \LDST_dec_sub9 \LDST_dec_sub9 + connect \opcode_in \LDST_dec_sub9_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub11_opcode_in + cell \LDST_dec_sub11 \LDST_dec_sub11 + connect \opcode_in \LDST_dec_sub11_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub27_opcode_in + cell \LDST_dec_sub27 \LDST_dec_sub27 + connect \opcode_in \LDST_dec_sub27_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub15_opcode_in + cell \LDST_dec_sub15 \LDST_dec_sub15 + connect \opcode_in \LDST_dec_sub15_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub20_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec_sub20_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec_sub20_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub20_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub20_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub20_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub20_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub20_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub20_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub20_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub20_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub20_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub20_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub20_LDST_sgn + cell \LDST_dec_sub20 \LDST_dec_sub20 + connect \opcode_in \LDST_dec_sub20_opcode_in + connect \LDST_function_unit \LDST_dec_sub20_LDST_function_unit + connect \LDST_internal_op \LDST_dec_sub20_LDST_internal_op + connect \LDST_in1_sel \LDST_dec_sub20_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec_sub20_LDST_in2_sel + connect \LDST_cr_in \LDST_dec_sub20_LDST_cr_in + connect \LDST_cr_out \LDST_dec_sub20_LDST_cr_out + connect \LDST_ldst_len \LDST_dec_sub20_LDST_ldst_len + connect \LDST_upd \LDST_dec_sub20_LDST_upd + connect \LDST_rc_sel \LDST_dec_sub20_LDST_rc_sel + connect \LDST_br \LDST_dec_sub20_LDST_br + connect \LDST_sgn_ext \LDST_dec_sub20_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec_sub20_LDST_is_32b + connect \LDST_sgn \LDST_dec_sub20_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub21_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec_sub21_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec_sub21_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub21_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub21_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub21_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub21_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub21_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub21_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub21_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub21_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub21_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub21_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub21_LDST_sgn + cell \LDST_dec_sub21 \LDST_dec_sub21 + connect \opcode_in \LDST_dec_sub21_opcode_in + connect \LDST_function_unit \LDST_dec_sub21_LDST_function_unit + connect \LDST_internal_op \LDST_dec_sub21_LDST_internal_op + connect \LDST_in1_sel \LDST_dec_sub21_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec_sub21_LDST_in2_sel + connect \LDST_cr_in \LDST_dec_sub21_LDST_cr_in + connect \LDST_cr_out \LDST_dec_sub21_LDST_cr_out + connect \LDST_ldst_len \LDST_dec_sub21_LDST_ldst_len + connect \LDST_upd \LDST_dec_sub21_LDST_upd + connect \LDST_rc_sel \LDST_dec_sub21_LDST_rc_sel + connect \LDST_br \LDST_dec_sub21_LDST_br + connect \LDST_sgn_ext \LDST_dec_sub21_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec_sub21_LDST_is_32b + connect \LDST_sgn \LDST_dec_sub21_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub23_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec_sub23_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec_sub23_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub23_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub23_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub23_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec_sub23_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec_sub23_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub23_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec_sub23_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub23_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub23_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub23_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec_sub23_LDST_sgn + cell \LDST_dec_sub23 \LDST_dec_sub23 + connect \opcode_in \LDST_dec_sub23_opcode_in + connect \LDST_function_unit \LDST_dec_sub23_LDST_function_unit + connect \LDST_internal_op \LDST_dec_sub23_LDST_internal_op + connect \LDST_in1_sel \LDST_dec_sub23_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec_sub23_LDST_in2_sel + connect \LDST_cr_in \LDST_dec_sub23_LDST_cr_in + connect \LDST_cr_out \LDST_dec_sub23_LDST_cr_out + connect \LDST_ldst_len \LDST_dec_sub23_LDST_ldst_len + connect \LDST_upd \LDST_dec_sub23_LDST_upd + connect \LDST_rc_sel \LDST_dec_sub23_LDST_rc_sel + connect \LDST_br \LDST_dec_sub23_LDST_br + connect \LDST_sgn_ext \LDST_dec_sub23_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec_sub23_LDST_is_32b + connect \LDST_sgn \LDST_dec_sub23_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub16_opcode_in + cell \LDST_dec_sub16 \LDST_dec_sub16 + connect \opcode_in \LDST_dec_sub16_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub18_opcode_in + cell \LDST_dec_sub18 \LDST_dec_sub18 + connect \opcode_in \LDST_dec_sub18_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub8_opcode_in + cell \LDST_dec_sub8 \LDST_dec_sub8 + connect \opcode_in \LDST_dec_sub8_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub24_opcode_in + cell \LDST_dec_sub24 \LDST_dec_sub24 + connect \opcode_in \LDST_dec_sub24_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec_sub4_opcode_in + cell \LDST_dec_sub4 \LDST_dec_sub4 + connect \opcode_in \LDST_dec_sub4_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] + sync init + end + process $group_2 + assign \LDST_dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub10_opcode_in \opcode_in + sync init + end + process $group_3 + assign \LDST_dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub28_opcode_in \opcode_in + sync init + end + process $group_4 + assign \LDST_dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub0_opcode_in \opcode_in + sync init + end + process $group_5 + assign \LDST_dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub26_opcode_in \opcode_in + sync init + end + process $group_6 + assign \LDST_dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub19_opcode_in \opcode_in + sync init + end + process $group_7 + assign \LDST_dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub22_opcode_in \opcode_in + sync init + end + process $group_8 + assign \LDST_dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub9_opcode_in \opcode_in + sync init + end + process $group_9 + assign \LDST_dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub11_opcode_in \opcode_in + sync init + end + process $group_10 + assign \LDST_dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub27_opcode_in \opcode_in + sync init + end + process $group_11 + assign \LDST_dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub15_opcode_in \opcode_in + sync init + end + process $group_12 + assign \LDST_dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub20_opcode_in \opcode_in + sync init + end + process $group_13 + assign \LDST_dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub21_opcode_in \opcode_in + sync init + end + process $group_14 + assign \LDST_dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub23_opcode_in \opcode_in + sync init + end + process $group_15 + assign \LDST_dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub16_opcode_in \opcode_in + sync init + end + process $group_16 + assign \LDST_dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub18_opcode_in \opcode_in + sync init + end + process $group_17 + assign \LDST_dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub8_opcode_in \opcode_in + sync init + end + process $group_18 + assign \LDST_dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub24_opcode_in \opcode_in + sync init + end + process $group_19 + assign \LDST_dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec_sub4_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$5 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$6 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$8 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$9 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$11 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$14 + process $group_20 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_function_unit \LDST_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_function_unit \LDST_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_function_unit \LDST_function_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_function_unit \LDST_function_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_function_unit \LDST_function_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_function_unit \LDST_dec_sub22_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_function_unit \LDST_function_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_function_unit \LDST_function_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_function_unit \LDST_function_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_function_unit \LDST_function_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_function_unit \LDST_dec_sub20_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_function_unit \LDST_dec_sub21_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_function_unit \LDST_dec_sub23_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_function_unit \LDST_function_unit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_function_unit \LDST_function_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_function_unit \LDST_function_unit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_function_unit \LDST_function_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_function_unit \LDST_function_unit$14 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$15 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$22 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$25 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$26 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$28 + process $group_21 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_internal_op \LDST_internal_op$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_internal_op \LDST_internal_op$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_internal_op \LDST_internal_op$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_internal_op \LDST_internal_op$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_internal_op \LDST_internal_op$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_internal_op \LDST_dec_sub22_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_internal_op \LDST_internal_op$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_internal_op \LDST_internal_op$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_internal_op \LDST_internal_op$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_internal_op \LDST_internal_op$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_internal_op \LDST_dec_sub20_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_internal_op \LDST_dec_sub21_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_internal_op \LDST_dec_sub23_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_internal_op \LDST_internal_op$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_internal_op \LDST_internal_op$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_internal_op \LDST_internal_op$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_internal_op \LDST_internal_op$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_internal_op \LDST_internal_op$28 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$29 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$30 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$31 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$32 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$33 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$34 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$35 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$36 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$37 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$38 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$39 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$40 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$41 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$42 + process $group_22 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_in1_sel \LDST_in1_sel$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_in1_sel \LDST_in1_sel$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_in1_sel \LDST_in1_sel$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_in1_sel \LDST_in1_sel$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_in1_sel \LDST_in1_sel$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_in1_sel \LDST_dec_sub22_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_in1_sel \LDST_in1_sel$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_in1_sel \LDST_in1_sel$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_in1_sel \LDST_in1_sel$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_in1_sel \LDST_in1_sel$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_in1_sel \LDST_dec_sub20_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_in1_sel \LDST_dec_sub21_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_in1_sel \LDST_dec_sub23_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_in1_sel \LDST_in1_sel$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_in1_sel \LDST_in1_sel$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_in1_sel \LDST_in1_sel$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_in1_sel \LDST_in1_sel$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_in1_sel \LDST_in1_sel$42 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$43 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$44 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$45 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$46 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$47 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$48 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$49 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$50 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$51 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$52 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$53 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$54 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$55 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$56 + process $group_23 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_in2_sel \LDST_in2_sel$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_in2_sel \LDST_in2_sel$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_in2_sel \LDST_in2_sel$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_in2_sel \LDST_in2_sel$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_in2_sel \LDST_in2_sel$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_in2_sel \LDST_dec_sub22_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_in2_sel \LDST_in2_sel$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_in2_sel \LDST_in2_sel$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_in2_sel \LDST_in2_sel$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_in2_sel \LDST_in2_sel$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_in2_sel \LDST_dec_sub20_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_in2_sel \LDST_dec_sub21_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_in2_sel \LDST_dec_sub23_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_in2_sel \LDST_in2_sel$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_in2_sel \LDST_in2_sel$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_in2_sel \LDST_in2_sel$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_in2_sel \LDST_in2_sel$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_in2_sel \LDST_in2_sel$56 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$57 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$58 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$59 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$60 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$61 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$62 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$63 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$64 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$65 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$66 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$67 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$68 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$69 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$70 + process $group_24 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_cr_in \LDST_cr_in$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_cr_in \LDST_cr_in$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_cr_in \LDST_cr_in$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_cr_in \LDST_cr_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_cr_in \LDST_cr_in$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_cr_in \LDST_dec_sub22_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_cr_in \LDST_cr_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_cr_in \LDST_cr_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_cr_in \LDST_cr_in$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_cr_in \LDST_cr_in$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_cr_in \LDST_dec_sub20_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_cr_in \LDST_dec_sub21_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_cr_in \LDST_dec_sub23_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_cr_in \LDST_cr_in$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_cr_in \LDST_cr_in$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_cr_in \LDST_cr_in$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_cr_in \LDST_cr_in$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_cr_in \LDST_cr_in$70 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$71 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$72 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$73 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$74 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$75 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$76 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$77 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$78 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$79 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$80 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$81 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$82 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$83 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$84 + process $group_25 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_cr_out \LDST_cr_out$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_cr_out \LDST_cr_out$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_cr_out \LDST_cr_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_cr_out \LDST_cr_out$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_cr_out \LDST_cr_out$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_cr_out \LDST_dec_sub22_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_cr_out \LDST_cr_out$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_cr_out \LDST_cr_out$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_cr_out \LDST_cr_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_cr_out \LDST_cr_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_cr_out \LDST_dec_sub20_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_cr_out \LDST_dec_sub21_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_cr_out \LDST_dec_sub23_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_cr_out \LDST_cr_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_cr_out \LDST_cr_out$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_cr_out \LDST_cr_out$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_cr_out \LDST_cr_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_cr_out \LDST_cr_out$84 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$85 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$86 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$87 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$88 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$89 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$90 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$91 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$92 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$93 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$94 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$95 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$96 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$97 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$98 + process $group_26 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_ldst_len \LDST_ldst_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_ldst_len \LDST_ldst_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_ldst_len \LDST_ldst_len$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_ldst_len \LDST_ldst_len$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_ldst_len \LDST_ldst_len$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_ldst_len \LDST_dec_sub22_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_ldst_len \LDST_ldst_len$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_ldst_len \LDST_ldst_len$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_ldst_len \LDST_ldst_len$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_ldst_len \LDST_ldst_len$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_ldst_len \LDST_dec_sub20_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_ldst_len \LDST_dec_sub21_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_ldst_len \LDST_dec_sub23_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_ldst_len \LDST_ldst_len$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_ldst_len \LDST_ldst_len$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_ldst_len \LDST_ldst_len$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_ldst_len \LDST_ldst_len$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_ldst_len \LDST_ldst_len$98 + end + sync init + end + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$99 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$100 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$101 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$102 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$103 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$104 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$105 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$106 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$107 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$108 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$109 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$110 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$111 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$112 + process $group_27 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_upd \LDST_upd$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_upd \LDST_upd$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_upd \LDST_upd$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_upd \LDST_upd$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_upd \LDST_upd$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_upd \LDST_dec_sub22_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_upd \LDST_upd$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_upd \LDST_upd$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_upd \LDST_upd$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_upd \LDST_upd$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_upd \LDST_dec_sub20_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_upd \LDST_dec_sub21_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_upd \LDST_dec_sub23_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_upd \LDST_upd$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_upd \LDST_upd$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_upd \LDST_upd$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_upd \LDST_upd$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_upd \LDST_upd$112 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$113 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$114 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$115 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$116 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$117 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$118 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$119 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$120 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$121 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$122 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$123 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$124 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$125 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$126 + process $group_28 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_rc_sel \LDST_rc_sel$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_rc_sel \LDST_rc_sel$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_rc_sel \LDST_rc_sel$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_rc_sel \LDST_rc_sel$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_rc_sel \LDST_rc_sel$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_rc_sel \LDST_dec_sub22_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_rc_sel \LDST_rc_sel$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_rc_sel \LDST_rc_sel$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_rc_sel \LDST_rc_sel$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_rc_sel \LDST_rc_sel$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_rc_sel \LDST_dec_sub20_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_rc_sel \LDST_dec_sub21_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_rc_sel \LDST_dec_sub23_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_rc_sel \LDST_rc_sel$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_rc_sel \LDST_rc_sel$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_rc_sel \LDST_rc_sel$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_rc_sel \LDST_rc_sel$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_rc_sel \LDST_rc_sel$126 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$140 + process $group_29 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_br \LDST_br$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_br \LDST_br$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_br \LDST_br$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_br \LDST_br$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_br \LDST_br$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_br \LDST_dec_sub22_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_br \LDST_br$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_br \LDST_br$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_br \LDST_br$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_br \LDST_br$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_br \LDST_dec_sub20_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_br \LDST_dec_sub21_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_br \LDST_dec_sub23_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_br \LDST_br$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_br \LDST_br$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_br \LDST_br$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_br \LDST_br$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_br \LDST_br$140 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$154 + process $group_30 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_sgn_ext \LDST_sgn_ext$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_sgn_ext \LDST_sgn_ext$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_sgn_ext \LDST_sgn_ext$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_sgn_ext \LDST_sgn_ext$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_sgn_ext \LDST_sgn_ext$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_sgn_ext \LDST_dec_sub22_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_sgn_ext \LDST_sgn_ext$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_sgn_ext \LDST_sgn_ext$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_sgn_ext \LDST_sgn_ext$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_sgn_ext \LDST_sgn_ext$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_sgn_ext \LDST_dec_sub20_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_sgn_ext \LDST_dec_sub21_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_sgn_ext \LDST_dec_sub23_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_sgn_ext \LDST_sgn_ext$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_sgn_ext \LDST_sgn_ext$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_sgn_ext \LDST_sgn_ext$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_sgn_ext \LDST_sgn_ext$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_sgn_ext \LDST_sgn_ext$154 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$168 + process $group_31 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_is_32b \LDST_is_32b$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_is_32b \LDST_is_32b$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_is_32b \LDST_is_32b$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_is_32b \LDST_is_32b$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_is_32b \LDST_is_32b$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_is_32b \LDST_dec_sub22_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_is_32b \LDST_is_32b$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_is_32b \LDST_is_32b$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_is_32b \LDST_is_32b$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_is_32b \LDST_is_32b$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_is_32b \LDST_dec_sub20_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_is_32b \LDST_dec_sub21_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_is_32b \LDST_dec_sub23_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_is_32b \LDST_is_32b$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_is_32b \LDST_is_32b$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_is_32b \LDST_is_32b$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_is_32b \LDST_is_32b$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_is_32b \LDST_is_32b$168 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$182 + process $group_32 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \LDST_sgn \LDST_sgn$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \LDST_sgn \LDST_sgn$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \LDST_sgn \LDST_sgn$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \LDST_sgn \LDST_sgn$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \LDST_sgn \LDST_sgn$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \LDST_sgn \LDST_dec_sub22_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \LDST_sgn \LDST_sgn$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \LDST_sgn \LDST_sgn$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \LDST_sgn \LDST_sgn$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \LDST_sgn \LDST_sgn$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \LDST_sgn \LDST_dec_sub20_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \LDST_sgn \LDST_dec_sub21_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \LDST_sgn \LDST_dec_sub23_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \LDST_sgn \LDST_sgn$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \LDST_sgn \LDST_sgn$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \LDST_sgn \LDST_sgn$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \LDST_sgn \LDST_sgn$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \LDST_sgn \LDST_sgn$182 + end + sync init + end + connect \LDST_function_unit$1 11'00000000000 + connect \LDST_function_unit$2 11'00000000000 + connect \LDST_function_unit$3 11'00000000000 + connect \LDST_function_unit$4 11'00000000000 + connect \LDST_function_unit$5 11'00000000000 + connect \LDST_function_unit$6 11'00000000000 + connect \LDST_function_unit$7 11'00000000000 + connect \LDST_function_unit$8 11'00000000000 + connect \LDST_function_unit$9 11'00000000000 + connect \LDST_function_unit$10 11'00000000000 + connect \LDST_function_unit$11 11'00000000000 + connect \LDST_function_unit$12 11'00000000000 + connect \LDST_function_unit$13 11'00000000000 + connect \LDST_function_unit$14 11'00000000000 + connect \LDST_internal_op$15 7'0000000 + connect \LDST_internal_op$16 7'0000000 + connect \LDST_internal_op$17 7'0000000 + connect \LDST_internal_op$18 7'0000000 + connect \LDST_internal_op$19 7'0000000 + connect \LDST_internal_op$20 7'0000000 + connect \LDST_internal_op$21 7'0000000 + connect \LDST_internal_op$22 7'0000000 + connect \LDST_internal_op$23 7'0000000 + connect \LDST_internal_op$24 7'0000000 + connect \LDST_internal_op$25 7'0000000 + connect \LDST_internal_op$26 7'0000000 + connect \LDST_internal_op$27 7'0000000 + connect \LDST_internal_op$28 7'0000000 + connect \LDST_in1_sel$29 3'000 + connect \LDST_in1_sel$30 3'000 + connect \LDST_in1_sel$31 3'000 + connect \LDST_in1_sel$32 3'000 + connect \LDST_in1_sel$33 3'000 + connect \LDST_in1_sel$34 3'000 + connect \LDST_in1_sel$35 3'000 + connect \LDST_in1_sel$36 3'000 + connect \LDST_in1_sel$37 3'000 + connect \LDST_in1_sel$38 3'000 + connect \LDST_in1_sel$39 3'000 + connect \LDST_in1_sel$40 3'000 + connect \LDST_in1_sel$41 3'000 + connect \LDST_in1_sel$42 3'000 + connect \LDST_in2_sel$43 4'0000 + connect \LDST_in2_sel$44 4'0000 + connect \LDST_in2_sel$45 4'0000 + connect \LDST_in2_sel$46 4'0000 + connect \LDST_in2_sel$47 4'0000 + connect \LDST_in2_sel$48 4'0000 + connect \LDST_in2_sel$49 4'0000 + connect \LDST_in2_sel$50 4'0000 + connect \LDST_in2_sel$51 4'0000 + connect \LDST_in2_sel$52 4'0000 + connect \LDST_in2_sel$53 4'0000 + connect \LDST_in2_sel$54 4'0000 + connect \LDST_in2_sel$55 4'0000 + connect \LDST_in2_sel$56 4'0000 + connect \LDST_cr_in$57 3'000 + connect \LDST_cr_in$58 3'000 + connect \LDST_cr_in$59 3'000 + connect \LDST_cr_in$60 3'000 + connect \LDST_cr_in$61 3'000 + connect \LDST_cr_in$62 3'000 + connect \LDST_cr_in$63 3'000 + connect \LDST_cr_in$64 3'000 + connect \LDST_cr_in$65 3'000 + connect \LDST_cr_in$66 3'000 + connect \LDST_cr_in$67 3'000 + connect \LDST_cr_in$68 3'000 + connect \LDST_cr_in$69 3'000 + connect \LDST_cr_in$70 3'000 + connect \LDST_cr_out$71 3'000 + connect \LDST_cr_out$72 3'000 + connect \LDST_cr_out$73 3'000 + connect \LDST_cr_out$74 3'000 + connect \LDST_cr_out$75 3'000 + connect \LDST_cr_out$76 3'000 + connect \LDST_cr_out$77 3'000 + connect \LDST_cr_out$78 3'000 + connect \LDST_cr_out$79 3'000 + connect \LDST_cr_out$80 3'000 + connect \LDST_cr_out$81 3'000 + connect \LDST_cr_out$82 3'000 + connect \LDST_cr_out$83 3'000 + connect \LDST_cr_out$84 3'000 + connect \LDST_ldst_len$85 4'0000 + connect \LDST_ldst_len$86 4'0000 + connect \LDST_ldst_len$87 4'0000 + connect \LDST_ldst_len$88 4'0000 + connect \LDST_ldst_len$89 4'0000 + connect \LDST_ldst_len$90 4'0000 + connect \LDST_ldst_len$91 4'0000 + connect \LDST_ldst_len$92 4'0000 + connect \LDST_ldst_len$93 4'0000 + connect \LDST_ldst_len$94 4'0000 + connect \LDST_ldst_len$95 4'0000 + connect \LDST_ldst_len$96 4'0000 + connect \LDST_ldst_len$97 4'0000 + connect \LDST_ldst_len$98 4'0000 + connect \LDST_upd$99 2'00 + connect \LDST_upd$100 2'00 + connect \LDST_upd$101 2'00 + connect \LDST_upd$102 2'00 + connect \LDST_upd$103 2'00 + connect \LDST_upd$104 2'00 + connect \LDST_upd$105 2'00 + connect \LDST_upd$106 2'00 + connect \LDST_upd$107 2'00 + connect \LDST_upd$108 2'00 + connect \LDST_upd$109 2'00 + connect \LDST_upd$110 2'00 + connect \LDST_upd$111 2'00 + connect \LDST_upd$112 2'00 + connect \LDST_rc_sel$113 2'00 + connect \LDST_rc_sel$114 2'00 + connect \LDST_rc_sel$115 2'00 + connect \LDST_rc_sel$116 2'00 + connect \LDST_rc_sel$117 2'00 + connect \LDST_rc_sel$118 2'00 + connect \LDST_rc_sel$119 2'00 + connect \LDST_rc_sel$120 2'00 + connect \LDST_rc_sel$121 2'00 + connect \LDST_rc_sel$122 2'00 + connect \LDST_rc_sel$123 2'00 + connect \LDST_rc_sel$124 2'00 + connect \LDST_rc_sel$125 2'00 + connect \LDST_rc_sel$126 2'00 + connect \LDST_br$127 1'0 + connect \LDST_br$128 1'0 + connect \LDST_br$129 1'0 + connect \LDST_br$130 1'0 + connect \LDST_br$131 1'0 + connect \LDST_br$132 1'0 + connect \LDST_br$133 1'0 + connect \LDST_br$134 1'0 + connect \LDST_br$135 1'0 + connect \LDST_br$136 1'0 + connect \LDST_br$137 1'0 + connect \LDST_br$138 1'0 + connect \LDST_br$139 1'0 + connect \LDST_br$140 1'0 + connect \LDST_sgn_ext$141 1'0 + connect \LDST_sgn_ext$142 1'0 + connect \LDST_sgn_ext$143 1'0 + connect \LDST_sgn_ext$144 1'0 + connect \LDST_sgn_ext$145 1'0 + connect \LDST_sgn_ext$146 1'0 + connect \LDST_sgn_ext$147 1'0 + connect \LDST_sgn_ext$148 1'0 + connect \LDST_sgn_ext$149 1'0 + connect \LDST_sgn_ext$150 1'0 + connect \LDST_sgn_ext$151 1'0 + connect \LDST_sgn_ext$152 1'0 + connect \LDST_sgn_ext$153 1'0 + connect \LDST_sgn_ext$154 1'0 + connect \LDST_is_32b$155 1'0 + connect \LDST_is_32b$156 1'0 + connect \LDST_is_32b$157 1'0 + connect \LDST_is_32b$158 1'0 + connect \LDST_is_32b$159 1'0 + connect \LDST_is_32b$160 1'0 + connect \LDST_is_32b$161 1'0 + connect \LDST_is_32b$162 1'0 + connect \LDST_is_32b$163 1'0 + connect \LDST_is_32b$164 1'0 + connect \LDST_is_32b$165 1'0 + connect \LDST_is_32b$166 1'0 + connect \LDST_is_32b$167 1'0 + connect \LDST_is_32b$168 1'0 + connect \LDST_sgn$169 1'0 + connect \LDST_sgn$170 1'0 + connect \LDST_sgn$171 1'0 + connect \LDST_sgn$172 1'0 + connect \LDST_sgn$173 1'0 + connect \LDST_sgn$174 1'0 + connect \LDST_sgn$175 1'0 + connect \LDST_sgn$176 1'0 + connect \LDST_sgn$177 1'0 + connect \LDST_sgn$178 1'0 + connect \LDST_sgn$179 1'0 + connect \LDST_sgn$180 1'0 + connect \LDST_sgn$181 1'0 + connect \LDST_sgn$182 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec58" +module \LDST_dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end + process $group_1 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + process $group_2 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_internal_op 7'0100101 + end + sync init + end + process $group_3 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_in1_sel 3'010 + end + sync init + end + process $group_4 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_in2_sel 4'1000 + end + sync init + end + process $group_5 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_ldst_len 4'0100 + end + sync init + end + process $group_8 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_upd 2'00 + end + sync init + end + process $group_9 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_rc_sel 2'00 + end + sync init + end + process $group_10 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_br 1'0 + end + sync init + end + process $group_11 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_sgn_ext 1'1 + end + sync init + end + process $group_12 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_is_32b 1'0 + end + sync init + end + process $group_13 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'10 + assign \LDST_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec62" +module \LDST_dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 1 \LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 3 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 4 \LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 6 \LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 7 \LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 9 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] + sync init + end + process $group_1 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + process $group_2 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_internal_op 7'0100110 + end + sync init + end + process $group_3 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_in1_sel 3'010 + end + sync init + end + process $group_4 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_in2_sel 4'1000 + end + sync init + end + process $group_5 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_cr_in 3'000 + end + sync init + end + process $group_6 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_cr_out 3'000 + end + sync init + end + process $group_7 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_ldst_len 4'1000 + end + sync init + end + process $group_8 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_upd 2'01 + end + sync init + end + process $group_9 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_rc_sel 2'00 + end + sync init + end + process $group_10 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_br 1'0 + end + sync init + end + process $group_11 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_sgn_ext 1'0 + end + sync init + end + process $group_12 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_is_32b 1'0 + end + sync init + end + process $group_13 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'00 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 2'01 + assign \LDST_sgn 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec" +module \dec$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \LDST_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \LDST_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \LDST_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 8 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 9 \LDST_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 10 \LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 11 \LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 12 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 13 \LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 14 \LDST_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 15 \LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 16 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 17 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 output 18 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 19 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 output 20 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 output 21 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 22 \LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 23 \LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 24 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 25 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 26 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 27 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 28 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 29 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 output 30 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 31 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec19_opcode_in + cell \LDST_dec19 \LDST_dec19 + connect \opcode_in \LDST_dec19_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec30_opcode_in + cell \LDST_dec30 \LDST_dec30 + connect \opcode_in \LDST_dec30_opcode_in + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec31_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec31_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec31_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec31_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec31_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec31_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec31_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec31_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec31_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec31_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec31_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec31_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec31_LDST_sgn + cell \LDST_dec31 \LDST_dec31 + connect \opcode_in \LDST_dec31_opcode_in + connect \LDST_function_unit \LDST_dec31_LDST_function_unit + connect \LDST_internal_op \LDST_dec31_LDST_internal_op + connect \LDST_in1_sel \LDST_dec31_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec31_LDST_in2_sel + connect \LDST_cr_in \LDST_dec31_LDST_cr_in + connect \LDST_cr_out \LDST_dec31_LDST_cr_out + connect \LDST_ldst_len \LDST_dec31_LDST_ldst_len + connect \LDST_upd \LDST_dec31_LDST_upd + connect \LDST_rc_sel \LDST_dec31_LDST_rc_sel + connect \LDST_br \LDST_dec31_LDST_br + connect \LDST_sgn_ext \LDST_dec31_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec31_LDST_is_32b + connect \LDST_sgn \LDST_dec31_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec58_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec58_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec58_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec58_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec58_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec58_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec58_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec58_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec58_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec58_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec58_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec58_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec58_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec58_LDST_sgn + cell \LDST_dec58 \LDST_dec58 + connect \opcode_in \LDST_dec58_opcode_in + connect \LDST_function_unit \LDST_dec58_LDST_function_unit + connect \LDST_internal_op \LDST_dec58_LDST_internal_op + connect \LDST_in1_sel \LDST_dec58_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec58_LDST_in2_sel + connect \LDST_cr_in \LDST_dec58_LDST_cr_in + connect \LDST_cr_out \LDST_dec58_LDST_cr_out + connect \LDST_ldst_len \LDST_dec58_LDST_ldst_len + connect \LDST_upd \LDST_dec58_LDST_upd + connect \LDST_rc_sel \LDST_dec58_LDST_rc_sel + connect \LDST_br \LDST_dec58_LDST_br + connect \LDST_sgn_ext \LDST_dec58_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec58_LDST_is_32b + connect \LDST_sgn \LDST_dec58_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \LDST_dec62_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_dec62_LDST_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_dec62_LDST_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec62_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec62_LDST_in2_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec62_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_dec62_LDST_cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_dec62_LDST_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec62_LDST_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_dec62_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec62_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec62_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec62_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_dec62_LDST_sgn + cell \LDST_dec62 \LDST_dec62 + connect \opcode_in \LDST_dec62_opcode_in + connect \LDST_function_unit \LDST_dec62_LDST_function_unit + connect \LDST_internal_op \LDST_dec62_LDST_internal_op + connect \LDST_in1_sel \LDST_dec62_LDST_in1_sel + connect \LDST_in2_sel \LDST_dec62_LDST_in2_sel + connect \LDST_cr_in \LDST_dec62_LDST_cr_in + connect \LDST_cr_out \LDST_dec62_LDST_cr_out + connect \LDST_ldst_len \LDST_dec62_LDST_ldst_len + connect \LDST_upd \LDST_dec62_LDST_upd + connect \LDST_rc_sel \LDST_dec62_LDST_rc_sel + connect \LDST_br \LDST_dec62_LDST_br + connect \LDST_sgn_ext \LDST_dec62_LDST_sgn_ext + connect \LDST_is_32b \LDST_dec62_LDST_is_32b + connect \LDST_sgn \LDST_dec62_LDST_sgn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] + sync init + end + process $group_1 + assign \LDST_dec19_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec19_opcode_in \opcode_in + sync init + end + process $group_2 + assign \LDST_dec30_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec30_opcode_in \opcode_in + sync init + end + process $group_3 + assign \LDST_dec31_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec31_opcode_in \opcode_in + sync init + end + process $group_4 + assign \LDST_dec58_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec58_opcode_in \opcode_in + sync init + end + process $group_5 + assign \LDST_dec62_opcode_in 32'00000000000000000000000000000000 + assign \LDST_dec62_opcode_in \opcode_in + sync init + end + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \LDST_function_unit$2 + process $group_6 + assign \LDST_function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_function_unit \LDST_function_unit$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_function_unit \LDST_function_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_function_unit \LDST_dec31_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_function_unit \LDST_dec58_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_function_unit \LDST_dec62_LDST_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_function_unit 11'00000000100 + end + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$3 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \LDST_internal_op$4 + process $group_7 + assign \LDST_internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_internal_op \LDST_internal_op$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_internal_op \LDST_internal_op$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_internal_op \LDST_dec31_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_internal_op \LDST_dec58_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_internal_op \LDST_dec62_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_internal_op 7'0100110 + end + sync init + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$5 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_in1_sel$6 + process $group_8 + assign \LDST_in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_in1_sel \LDST_in1_sel$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_in1_sel \LDST_in1_sel$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_in1_sel \LDST_dec31_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_in1_sel \LDST_dec58_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_in1_sel \LDST_dec62_LDST_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_in1_sel 3'010 + end + sync init + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$7 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_in2_sel$8 + process $group_9 + assign \LDST_in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_in2_sel \LDST_in2_sel$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_in2_sel \LDST_in2_sel$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_in2_sel \LDST_dec31_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_in2_sel \LDST_dec58_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_in2_sel \LDST_dec62_LDST_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_in2_sel 4'0011 + end + sync init + end + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$9 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_in$10 + process $group_10 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_cr_in \LDST_cr_in$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_cr_in \LDST_cr_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_cr_in \LDST_dec31_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_cr_in \LDST_dec58_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_cr_in \LDST_dec62_LDST_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_cr_in 3'000 + end + sync init + end + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$11 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \LDST_cr_out$12 + process $group_11 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_cr_out \LDST_cr_out$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_cr_out \LDST_cr_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_cr_out \LDST_dec31_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_cr_out \LDST_dec58_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_cr_out \LDST_dec62_LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_cr_out 3'000 + end + sync init + end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$13 + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \LDST_ldst_len$14 + process $group_12 + assign \LDST_ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_ldst_len \LDST_ldst_len$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_ldst_len \LDST_ldst_len$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_ldst_len \LDST_dec31_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_ldst_len \LDST_dec58_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_ldst_len \LDST_dec62_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_ldst_len 4'0100 + end + sync init + end + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$15 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_upd$16 + process $group_13 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_upd \LDST_upd$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_upd \LDST_upd$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_upd \LDST_dec31_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_upd \LDST_dec58_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_upd \LDST_dec62_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_upd 2'01 + end + sync init + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$17 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \LDST_rc_sel$18 + process $group_14 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_rc_sel \LDST_rc_sel$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_rc_sel \LDST_rc_sel$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_rc_sel \LDST_dec31_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_rc_sel \LDST_dec58_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_rc_sel \LDST_dec62_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_rc_sel 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_br$20 + process $group_15 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_br \LDST_br$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_br \LDST_br$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_br \LDST_dec31_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_br \LDST_dec58_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_br \LDST_dec62_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_br 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn_ext$22 + process $group_16 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_sgn_ext \LDST_sgn_ext$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_sgn_ext \LDST_sgn_ext$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_sgn_ext \LDST_dec31_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_sgn_ext \LDST_dec58_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_sgn_ext \LDST_dec62_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_sgn_ext 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_is_32b$24 + process $group_17 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_is_32b \LDST_is_32b$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_is_32b \LDST_is_32b$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_is_32b \LDST_dec31_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_is_32b \LDST_dec58_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_is_32b \LDST_dec62_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_is_32b 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \LDST_sgn$26 + process $group_18 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \LDST_sgn \LDST_sgn$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \LDST_sgn \LDST_sgn$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \LDST_sgn \LDST_dec31_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \LDST_sgn \LDST_dec58_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \LDST_sgn \LDST_dec62_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \LDST_sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \LDST_sgn 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" + wire width 32 \opcode_switch$27 + process $group_19 + assign \opcode_switch$27 32'00000000000000000000000000000000 + assign \opcode_switch$27 \opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + wire width 32 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" + cell $mux $29 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $28 + end + process $group_20 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_RS + process $group_21 + assign \LDST_RS 5'00000 + assign \LDST_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_RT + process $group_22 + assign \LDST_RT 5'00000 + assign \LDST_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_23 + assign \LDST_RA 5'00000 + assign \LDST_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_RB + process $group_24 + assign \LDST_RB 5'00000 + assign \LDST_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_25 + assign \LDST_SI 16'0000000000000000 + assign \LDST_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_26 + assign \LDST_UI 16'0000000000000000 + assign \LDST_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \LDST_L + process $group_27 + assign \LDST_L 1'0 + assign \LDST_L { \opcode_in [21] } + sync init + end + process $group_28 + assign \LDST_SH32 5'00000 + assign \LDST_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_29 + assign \LDST_sh 6'000000 + assign \LDST_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_MB32 + process $group_30 + assign \LDST_MB32 5'00000 + assign \LDST_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_ME32 + process $group_31 + assign \LDST_ME32 5'00000 + assign \LDST_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_32 + assign \LDST_LI 24'000000000000000000000000 + assign \LDST_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \LDST_LK + process $group_33 + assign \LDST_LK 1'0 + assign \LDST_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \LDST_AA + process $group_34 + assign \LDST_AA 1'0 + assign \LDST_AA { \opcode_in [1] } + sync init + end + process $group_35 + assign \LDST_Rc 1'0 + assign \LDST_Rc { \opcode_in [0] } + sync init + end + process $group_36 + assign \LDST_OE 1'0 + assign \LDST_OE { \opcode_in [10] } + sync init + end + process $group_37 + assign \LDST_BD 14'00000000000000 + assign \LDST_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 3 \LDST_BF + process $group_38 + assign \LDST_BF 3'000 + assign \LDST_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \LDST_CR + process $group_39 + assign \LDST_CR 10'0000000000 + assign \LDST_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + process $group_40 + assign \LDST_BB 5'00000 + assign \LDST_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + process $group_41 + assign \LDST_BA 5'00000 + assign \LDST_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + process $group_42 + assign \LDST_BT 5'00000 + assign \LDST_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_43 + assign \LDST_FXM 8'00000000 + assign \LDST_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_BO + process $group_44 + assign \LDST_BO 5'00000 + assign \LDST_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_45 + assign \LDST_BI 5'00000 + assign \LDST_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 2 \LDST_BH + process $group_46 + assign \LDST_BH 2'00 + assign \LDST_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \LDST_D + process $group_47 + assign \LDST_D 16'0000000000000000 + assign \LDST_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + process $group_48 + assign \LDST_DS 14'00000000000000 + assign \LDST_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_TO + process $group_49 + assign \LDST_TO 5'00000 + assign \LDST_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_50 + assign \LDST_BC 5'00000 + assign \LDST_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_SH + process $group_51 + assign \LDST_SH 5'00000 + assign \LDST_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_ME + process $group_52 + assign \LDST_ME 5'00000 + assign \LDST_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \LDST_MB + process $group_53 + assign \LDST_MB 5'00000 + assign \LDST_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 \LDST_SPR + process $group_54 + assign \LDST_SPR 10'0000000000 + assign \LDST_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_A + process $group_55 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init + end + process $group_56 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + process $group_57 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_BO + process $group_58 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_CT + process $group_59 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \X_DCMX + process $group_60 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_DRM + process $group_61 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_E + process $group_62 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_E_1 + process $group_63 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_EO + process $group_64 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_EO_1 + process $group_65 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_EX + process $group_66 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FC + process $group_67 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRA + process $group_68 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRAp + process $group_69 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRB + process $group_70 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRBp + process $group_71 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRS + process $group_72 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRSp + process $group_73 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRT + process $group_74 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_FRTp + process $group_75 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \X_IH + process $group_76 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_IMM8 + process $group_77 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 + process $group_78 + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L + process $group_79 + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 + process $group_80 + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 + process $group_81 + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_MO + process $group_82 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_NB + process $group_83 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_PRS + process $group_84 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R + process $group_85 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_R_1 + process $group_86 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RA + process $group_87 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RB + process $group_88 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_Rc + process $group_89 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RIC + process $group_90 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_RM + process $group_91 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_RO + process $group_92 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RS + process $group_93 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RSp + process $group_94 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RT + process $group_95 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_RTp + process $group_96 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_S + process $group_97 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SH + process $group_98 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_SI + process $group_99 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_SP + process $group_100 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_SR + process $group_101 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_SX + process $group_102 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_SX_S + process $group_103 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_T + process $group_104 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_TBR + process $group_105 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TH + process $group_106 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_TO + process $group_107 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_TX + process $group_108 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \X_TX_T + process $group_109 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \X_U + process $group_110 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_UIM + process $group_111 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRS + process $group_112 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \X_VRT + process $group_113 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_W + process $group_114 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_WC + process $group_115 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \X_XO + process $group_116 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \X_XO_1 + process $group_117 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_AA + process $group_118 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \B_BD + process $group_119 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BI + process $group_120 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \B_BO + process $group_121 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \B_LK + process $group_122 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_AA + process $group_123 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 24 \I_LI + process $group_124 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \I_LK + process $group_125 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_AX + process $group_126 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_A + process $group_127 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_AX_A + process $group_128 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX3_BF + process $group_129 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_BX + process $group_130 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_B + process $group_131 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_BX_B + process $group_132 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_DM + process $group_133 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_Rc + process $group_134 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX3_SHW + process $group_135 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX3_TX + process $group_136 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX3_T + process $group_137 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX3_TX_T + process $group_138 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX3_XO + process $group_139 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XX3_XO_1 + process $group_140 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX3_XO_2 + process $group_141 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_AX + process $group_142 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_A + process $group_143 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_AX_A + process $group_144 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_BX + process $group_145 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_B + process $group_146 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_BX_B + process $group_147 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_CX + process $group_148 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_C + process $group_149 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_CX_C + process $group_150 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX4_TX + process $group_151 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX4_T + process $group_152 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX4_TX_T + process $group_153 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX4_XO + process $group_154 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BA + process $group_155 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BB + process $group_156 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BF + process $group_157 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XL_BFA + process $group_158 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XL_BH + process $group_159 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BI + process $group_160 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO + process $group_161 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XL_BO_1 + process $group_162 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + process $group_163 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_LK + process $group_164 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 15 \XL_OC + process $group_165 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XL_S + process $group_166 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XL_XO + process $group_167 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_BC + process $group_168 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRA + process $group_169 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRB + process $group_170 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRC + process $group_171 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_FRT + process $group_172 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RA + process $group_173 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RB + process $group_174 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \A_Rc + process $group_175 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_RT + process $group_176 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \A_XO + process $group_177 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \D_BF + process $group_178 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_D + process $group_179 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRS + process $group_180 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_FRT + process $group_181 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \D_L + process $group_182 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RA + process $group_183 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RS + process $group_184 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_RT + process $group_185 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_SI + process $group_186 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \D_TO + process $group_187 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \D_UI + process $group_188 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \XX2_BF + process $group_189 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_BX + process $group_190 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_B + process $group_191 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_BX_B + process $group_192 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dc + process $group_193 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_dm + process $group_194 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_dx + process $group_195 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_dc_dm_dx + process $group_196 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_DCMX + process $group_197 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_EO + process $group_198 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_RT + process $group_199 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XX2_TX + process $group_200 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XX2_T + process $group_201 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XX2_TX_T + process $group_202 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \XX2_UIM + process $group_203 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \XX2_UIM_1 + process $group_204 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \XX2_XO + process $group_205 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XX2_XO_1 + process $group_206 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \Z22_BF + process $group_207 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DCM + process $group_208 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_DGM + process $group_209 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRA + process $group_210 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRAp + process $group_211 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRT + process $group_212 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z22_FRTp + process $group_213 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z22_Rc + process $group_214 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \Z22_SH + process $group_215 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \Z22_XO + process $group_216 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \EVS_BFA + process $group_217 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_BHRBE + process $group_218 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_DUI + process $group_219 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_DUIS + process $group_220 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFX_FXM + process $group_221 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RS + process $group_222 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFX_RT + process $group_223 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_SPR + process $group_224 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFX_XO + process $group_225 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \DX_d0 + process $group_226 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_d1 + process $group_227 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DX_d2 + process $group_228 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 16 \DX_d0_d1_d2 + process $group_229 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_RT + process $group_230 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DX_XO + process $group_231 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 12 \DQ_DQ + process $group_232 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \DQ_PT + process $group_233 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RA + process $group_234 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_RTp + process $group_235 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_SX + process $group_236 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_S + process $group_237 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_SX_S + process $group_238 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \DQ_TX + process $group_239 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQ_T + process $group_240 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \DQ_TX_T + process $group_241 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \DQ_XO + process $group_242 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 14 \DS_DS + process $group_243 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRSp + process $group_244 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_FRTp + process $group_245 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RA + process $group_246 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RS + process $group_247 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RSp + process $group_248 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_RT + process $group_249 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRS + process $group_250 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DS_VRT + process $group_251 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DS_XO + process $group_252 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_EO + process $group_253 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VX_PS + process $group_254 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RA + process $group_255 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_RT + process $group_256 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_SIM + process $group_257 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_UIM + process $group_258 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VX_UIM_1 + process $group_259 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \VX_UIM_2 + process $group_260 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \VX_UIM_3 + process $group_261 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRA + process $group_262 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRB + process $group_263 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VX_VRT + process $group_264 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VX_XO + process $group_265 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 11 \VX_XO_1 + process $group_266 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \XFL_FLM + process $group_267 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XFL_FRB + process $group_268 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_L + process $group_269 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_Rc + process $group_270 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XFL_W + process $group_271 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \XFL_XO + process $group_272 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRA + process $group_273 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRAp + process $group_274 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRB + process $group_275 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRBp + process $group_276 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRT + process $group_277 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_FRTp + process $group_278 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_R + process $group_279 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \Z23_Rc + process $group_280 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \Z23_RMC + process $group_281 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \Z23_TE + process $group_282 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 8 \Z23_XO + process $group_283 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IB + process $group_284 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_IS + process $group_285 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_mb + process $group_286 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MDS_me + process $group_287 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RA + process $group_288 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RB + process $group_289 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MDS_Rc + process $group_290 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MDS_RS + process $group_291 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI + process $group_292 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XBI_1 + process $group_293 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \MDS_XO + process $group_294 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 7 \SC_LEV + process $group_295 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \SC_XO + process $group_296 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \SC_XO_1 + process $group_297 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_MB + process $group_298 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_ME + process $group_299 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RA + process $group_300 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RB + process $group_301 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \M_Rc + process $group_302 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_RS + process $group_303 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \M_SH + process $group_304 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_mb + process $group_305 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_me + process $group_306 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RA + process $group_307 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \MD_Rc + process $group_308 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_309 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_310 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_311 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_312 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_313 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_314 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_315 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_316 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_317 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_318 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_319 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_320 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_321 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_322 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_323 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_324 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_325 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_326 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_327 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_328 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_329 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_330 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_331 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_332 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_333 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_334 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_335 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_336 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_337 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_338 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_339 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_340 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_341 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_342 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_343 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_344 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_345 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_346 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + connect \LDST_function_unit$1 11'00000000000 + connect \LDST_function_unit$2 11'00000000000 + connect \LDST_internal_op$3 7'0000000 + connect \LDST_internal_op$4 7'0000000 + connect \LDST_in1_sel$5 3'000 + connect \LDST_in1_sel$6 3'000 + connect \LDST_in2_sel$7 4'0000 + connect \LDST_in2_sel$8 4'0000 + connect \LDST_cr_in$9 3'000 + connect \LDST_cr_in$10 3'000 + connect \LDST_cr_out$11 3'000 + connect \LDST_cr_out$12 3'000 + connect \LDST_ldst_len$13 4'0000 + connect \LDST_ldst_len$14 4'0000 + connect \LDST_upd$15 2'00 + connect \LDST_upd$16 2'00 + connect \LDST_rc_sel$17 2'00 + connect \LDST_rc_sel$18 2'00 + connect \LDST_br$19 1'0 + connect \LDST_br$20 1'0 + connect \LDST_sgn_ext$21 1'0 + connect \LDST_sgn_ext$22 1'0 + connect \LDST_is_32b$23 1'0 + connect \LDST_is_32b$24 1'0 + connect \LDST_sgn$25 1'0 + connect \LDST_sgn$26 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_rc" +module \dec_rc$194 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \LDST_Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_oe" +module \dec_oe$195 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \LDST_OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \LDST_OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in.ppick" +module \ppick$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in" +module \dec_cr_in$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 3 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 4 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 6 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$197 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_b_ok + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \LDST_BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \LDST_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \LDST_BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \LDST_BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \LDST_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_o_ok + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 + end + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out.ppick" +module \ppick$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out" +module \dec_cr_out$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 4 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$199 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_bitfield_ok + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_fxm_ok + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $1 + end + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \LDST_FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_ai" +module \dec_ai$200 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 output 1 \immz_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 2 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + process $group_0 + assign \ra 5'00000 + assign \ra \LDST_RA + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B $3 + connect \Y $5 + end + process $group_1 + assign \immz_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + case 1'1 + assign \immz_out 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_bi" +module \dec_bi$201 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 3 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 5 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 input 7 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 8 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 input 9 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $11 + end + process $group_0 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end + sync init + end + process $group_1 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init + end + process $group_2 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $14 + end + connect $13 $14 + process $group_3 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_4 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_5 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $23 + end + connect $22 $23 + process $group_7 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST" +module \dec_LDST + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 0 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 input 1 \bigendian + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LDST_LDST__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 3 \LDST_LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LDST_LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 5 \LDST_LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 6 \LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 7 \LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \LDST_LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \LDST_LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \LDST_LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \LDST_LDST__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 13 \LDST_LDST__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \LDST_LDST__sign_extend + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 16 \LDST_LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \LDST_LDST__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" + wire width 32 \dec_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_LDST_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_LDST_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_LDST_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 \dec_LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_LDST_in2_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_LDST_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LDST_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LDST_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \dec_LDST_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \dec_LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \dec_LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \dec_LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \dec_XL_BT + cell \dec$193 \dec + connect \raw_opcode_in \raw_opcode_in + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_cr_in \dec_LDST_cr_in + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_br \dec_LDST_br + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_upd \dec_LDST_upd + connect \LDST_RA \dec_LDST_RA + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_sh \dec_LDST_sh + connect \LDST_LI \dec_LDST_LI + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_OE \dec_LDST_OE + connect \LDST_BD \dec_LDST_BD + connect \LDST_BB \dec_LDST_BB + connect \LDST_BA \dec_LDST_BA + connect \LDST_BT \dec_LDST_BT + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_BI \dec_LDST_BI + connect \LDST_DS \dec_LDST_DS + connect \LDST_BC \dec_LDST_BC + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc$194 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \LDST_Rc \dec_LDST_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe$195 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \LDST_internal_op \dec_LDST_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \LDST_OE \dec_LDST_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + cell \dec_cr_in$196 \dec_cr_in + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_BB \dec_LDST_BB + connect \LDST_BA \dec_LDST_BA + connect \LDST_BT \dec_LDST_BT + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_BI \dec_LDST_BI + connect \LDST_BC \dec_LDST_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + cell \dec_cr_out$198 \dec_cr_out + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_FXM \dec_LDST_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire width 1 \dec_ai_immz_out + cell \dec_ai$200 \dec_ai + connect \sel_in \dec_ai_sel_in + connect \immz_out \dec_ai_immz_out + connect \LDST_RA \dec_LDST_RA + end + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_bi_imm_b_ok + cell \dec_bi$201 \dec_bi + connect \sel_in \dec_bi_sel_in + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_sh \dec_LDST_sh + connect \LDST_LI \dec_LDST_LI + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + end + process $group_0 + assign \LDST_LDST__insn 32'00000000000000000000000000000000 + assign \LDST_LDST__insn \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + process $group_2 + assign \insn_in$1 32'00000000000000000000000000000000 + assign \insn_in$1 \dec_opcode_in + sync init + end + process $group_3 + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in + sync init + end + process $group_4 + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in + sync init + end + process $group_5 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_LDST_rc_sel + sync init + end + process $group_6 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_LDST_rc_sel + sync init + end + process $group_7 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_LDST_cr_in + sync init + end + process $group_8 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_LDST_cr_out + sync init + end + process $group_9 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init + end + process $group_10 + assign \LDST_LDST__insn_type 7'0000000 + assign \LDST_LDST__insn_type \dec_LDST_internal_op + sync init + end + process $group_11 + assign \LDST_LDST__fn_unit 11'00000000000 + assign \LDST_LDST__fn_unit \dec_LDST_function_unit + sync init + end + process $group_12 + assign \dec_ai_sel_in 3'000 + assign \dec_ai_sel_in \dec_LDST_in1_sel + sync init + end + process $group_13 + assign \LDST_LDST__zero_a 1'0 + assign \LDST_LDST__zero_a \dec_ai_immz_out + sync init + end + process $group_14 + assign \dec_bi_sel_in 4'0000 + assign \dec_bi_sel_in \dec_LDST_in2_sel + sync init + end + process $group_15 + assign \LDST_LDST__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \LDST_LDST__imm_data__ok 1'0 + assign { \LDST_LDST__imm_data__ok \LDST_LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + sync init + end + process $group_17 + assign \LDST_LDST__rc__rc 1'0 + assign \LDST_LDST__rc__ok 1'0 + assign { \LDST_LDST__rc__ok \LDST_LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + sync init + end + process $group_19 + assign \LDST_LDST__oe__oe 1'0 + assign \LDST_LDST__oe__ok 1'0 + assign { \LDST_LDST__oe__ok \LDST_LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + sync init + end + process $group_21 + assign \LDST_LDST__data_len 4'0000 + assign \LDST_LDST__data_len \dec_LDST_ldst_len + sync init + end + process $group_22 + assign \LDST_LDST__is_32bit 1'0 + assign \LDST_LDST__is_32bit \dec_LDST_is_32b + sync init + end + process $group_23 + assign \LDST_LDST__is_signed 1'0 + assign \LDST_LDST__is_signed \dec_LDST_sgn + sync init + end + process $group_24 + assign \LDST_LDST__byte_reverse 1'0 + assign \LDST_LDST__byte_reverse \dec_LDST_br + sync init + end + process $group_25 + assign \LDST_LDST__sign_extend 1'0 + assign \LDST_LDST__sign_extend \dec_LDST_sgn_ext + sync init + end + process $group_26 + assign \LDST_LDST__ldst_mode 2'00 + assign \LDST_LDST__ldst_mode \dec_LDST_upd + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" +module \rdpick_INT_ra + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 9 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 9 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A { \i [8] \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } + connect \Y $1 + end + process $group_0 + assign \ni 9'000000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [1] \i [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [8] } + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \Y $31 + end + process $group_9 + assign \t8 1'0 + assign \t8 $31 + sync init + end + process $group_10 + assign \o 9'000000000 + assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $35 + end + process $group_11 + assign \en_o 1'0 + assign \en_o $35 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" +module \rdpick_INT_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [1] \i [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" +module \rdpick_INT_rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A { \i [1] \i [0] } + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97340,9 +203880,9 @@ module \rdpick_INT_rc assign \o { \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -97359,43 +203899,43 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" module \rdpick_XER_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 - assign \ni 4'0000 + assign \ni 6'000000 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -97403,7 +203943,7 @@ module \rdpick_XER_xer_so connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97416,21 +203956,21 @@ module \rdpick_XER_xer_so assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97443,21 +203983,21 @@ module \rdpick_XER_xer_so assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $13 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \A { \i [2] \i [1] \i [0] \ni [3] } connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97470,46 +204010,100 @@ module \rdpick_XER_xer_so assign \t3 $11 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end process $group_5 - assign \o 4'0000 - assign \o { \t3 \t2 \t1 \t0 } + assign \t4 1'0 + assign \t4 $15 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \o - connect \Y $15 + connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 end process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + process $group_7 + assign \o 6'000000 + assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $23 + end + process $group_8 assign \en_o 1'0 - assign \en_o $15 + assign \en_o $23 sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" module \rdpick_XER_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 3 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \i + connect \A { \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -97517,20 +204111,20 @@ module \rdpick_XER_xer_ca assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -97538,7 +204132,7 @@ module \rdpick_XER_xer_ca connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97551,21 +204145,21 @@ module \rdpick_XER_xer_ca assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97583,9 +204177,9 @@ module \rdpick_XER_xer_ca assign \o { \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -97602,22 +204196,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" module \rdpick_XER_xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -97625,7 +204219,7 @@ module \rdpick_XER_xer_ov assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -97637,9 +204231,9 @@ module \rdpick_XER_xer_ov assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97656,22 +204250,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" module \rdpick_CR_full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -97679,7 +204273,7 @@ module \rdpick_CR_full_cr assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -97691,9 +204285,9 @@ module \rdpick_CR_full_cr assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97710,22 +204304,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" module \rdpick_CR_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \i + connect \A { \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -97733,20 +204327,20 @@ module \rdpick_CR_cr_a assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -97754,7 +204348,7 @@ module \rdpick_CR_cr_a connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97772,9 +204366,9 @@ module \rdpick_CR_cr_a assign \o { \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -97791,22 +204385,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" module \rdpick_CR_cr_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -97814,7 +204408,7 @@ module \rdpick_CR_cr_b assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -97826,9 +204420,9 @@ module \rdpick_CR_cr_b assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97845,22 +204439,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" module \rdpick_CR_cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -97868,7 +204462,7 @@ module \rdpick_CR_cr_c assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -97880,9 +204474,9 @@ module \rdpick_CR_cr_c assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97899,22 +204493,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" module \rdpick_FAST_fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 3 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \i + connect \A { \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -97922,20 +204516,20 @@ module \rdpick_FAST_fast1 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -97943,7 +204537,7 @@ module \rdpick_FAST_fast1 connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97956,21 +204550,21 @@ module \rdpick_FAST_fast1 assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -97988,9 +204582,9 @@ module \rdpick_FAST_fast1 assign \o { \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -98007,22 +204601,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" module \rdpick_FAST_fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \i + connect \A { \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -98030,20 +204624,20 @@ module \rdpick_FAST_fast2 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98051,7 +204645,7 @@ module \rdpick_FAST_fast2 connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98069,9 +204663,9 @@ module \rdpick_FAST_fast2 assign \o { \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98088,22 +204682,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" module \rdpick_SPR_spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -98111,7 +204705,7 @@ module \rdpick_SPR_spr1 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -98123,9 +204717,9 @@ module \rdpick_SPR_spr1 assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98142,22 +204736,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" module \wrpick_INT_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 10 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 10 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 10 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 10 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 - connect \A \i + connect \A { \i [9] \i [8] \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -98165,20 +204759,20 @@ module \wrpick_INT_o assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98186,7 +204780,7 @@ module \wrpick_INT_o connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98199,21 +204793,21 @@ module \wrpick_INT_o assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98226,21 +204820,21 @@ module \wrpick_INT_o assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $13 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \A { \i [2] \i [1] \i [0] \ni [3] } connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98253,21 +204847,21 @@ module \wrpick_INT_o assign \t3 $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $17 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } connect \Y $16 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98280,21 +204874,21 @@ module \wrpick_INT_o assign \t4 $15 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $21 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } + connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] \ni [5] } connect \Y $20 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98307,21 +204901,21 @@ module \wrpick_INT_o assign \t5 $19 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $25 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 - connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [6] } connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98334,21 +204928,21 @@ module \wrpick_INT_o assign \t6 $23 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $29 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 - connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } + connect \A { \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [7] } connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98361,21 +204955,21 @@ module \wrpick_INT_o assign \t7 $27 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $33 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 - connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] } + connect \A { \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [8] } connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98388,21 +204982,21 @@ module \wrpick_INT_o assign \t8 $31 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $37 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A { \i [8:0] [8] \i [8:0] [7] \i [8:0] [6] \i [8:0] [5] \i [8:0] [4] \i [8:0] [3] \i [8:0] [2] \i [8:0] [1] \i [8:0] [0] \ni [9] } + connect \A { \i [8] \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [9] } connect \Y $36 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98420,9 +205014,9 @@ module \wrpick_INT_o assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $40 parameter \A_SIGNED 0 parameter \A_WIDTH 10 @@ -98439,22 +205033,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" module \wrpick_CR_full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -98462,7 +205056,7 @@ module \wrpick_CR_full_cr assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -98474,9 +205068,9 @@ module \wrpick_CR_full_cr assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98493,22 +205087,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" module \wrpick_CR_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 6 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 - connect \A \i + connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -98516,20 +205110,20 @@ module \wrpick_CR_cr_a assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98537,7 +205131,7 @@ module \wrpick_CR_cr_a connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98550,21 +205144,21 @@ module \wrpick_CR_cr_a assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98577,21 +205171,21 @@ module \wrpick_CR_cr_a assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $13 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \A { \i [2] \i [1] \i [0] \ni [3] } connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98604,21 +205198,21 @@ module \wrpick_CR_cr_a assign \t3 $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $17 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } connect \Y $16 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98631,21 +205225,21 @@ module \wrpick_CR_cr_a assign \t4 $15 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $21 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } + connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] \ni [5] } connect \Y $20 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98663,9 +205257,9 @@ module \wrpick_CR_cr_a assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $24 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -98682,43 +205276,43 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" module \wrpick_XER_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 - assign \ni 4'0000 + assign \ni 3'000 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98726,7 +205320,7 @@ module \wrpick_XER_xer_ca connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98739,21 +205333,21 @@ module \wrpick_XER_xer_ca assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98766,73 +205360,46 @@ module \wrpick_XER_xer_ca assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - process $group_5 - assign \o 4'0000 - assign \o { \t3 \t2 \t1 \t0 } + assign \o 3'000 + assign \o { \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $15 + connect \Y $11 end - process $group_6 + process $group_5 assign \en_o 1'0 - assign \en_o $15 + assign \en_o $11 sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" module \wrpick_XER_xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \i + connect \A { \i [3] \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -98840,20 +205407,20 @@ module \wrpick_XER_xer_ov assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98861,7 +205428,7 @@ module \wrpick_XER_xer_ov connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98874,21 +205441,21 @@ module \wrpick_XER_xer_ov assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98901,21 +205468,21 @@ module \wrpick_XER_xer_ov assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $13 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \A { \i [2] \i [1] \i [0] \ni [3] } connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -98933,9 +205500,9 @@ module \wrpick_XER_xer_ov assign \o { \t3 \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $16 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -98952,22 +205519,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" module \wrpick_XER_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \i + connect \A { \i [3] \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -98975,20 +205542,20 @@ module \wrpick_XER_xer_so assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -98996,7 +205563,7 @@ module \wrpick_XER_xer_so connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99009,21 +205576,21 @@ module \wrpick_XER_xer_so assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99036,21 +205603,21 @@ module \wrpick_XER_xer_so assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $13 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \A { \i [2] \i [1] \i [0] \ni [3] } connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99068,9 +205635,9 @@ module \wrpick_XER_xer_so assign \o { \t3 \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $16 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -99087,22 +205654,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" module \wrpick_FAST_fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 5 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 5 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 5 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \i + connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -99110,20 +205677,20 @@ module \wrpick_FAST_fast1 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -99131,7 +205698,7 @@ module \wrpick_FAST_fast1 connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99144,21 +205711,21 @@ module \wrpick_FAST_fast1 assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $9 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \A { \i [1] \i [0] \ni [2] } connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99171,21 +205738,21 @@ module \wrpick_FAST_fast1 assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $13 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \A { \i [2] \i [1] \i [0] \ni [3] } connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99198,21 +205765,21 @@ module \wrpick_FAST_fast1 assign \t3 $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $17 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } connect \Y $16 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99230,9 +205797,9 @@ module \wrpick_FAST_fast1 assign \o { \t4 \t3 \t2 \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $20 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -99249,22 +205816,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" module \wrpick_STATE_nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \i + connect \A { \i [1] \i [0] } connect \Y $1 end process $group_0 @@ -99272,20 +205839,20 @@ module \wrpick_STATE_nia assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $reduce_bool $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -99293,7 +205860,7 @@ module \wrpick_STATE_nia connect \A { \i [0] \ni [1] } connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99311,9 +205878,9 @@ module \wrpick_STATE_nia assign \o { \t1 \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -99330,22 +205897,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" module \wrpick_STATE_msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -99353,7 +205920,7 @@ module \wrpick_STATE_msr assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -99365,9 +205932,9 @@ module \wrpick_STATE_msr assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99384,22 +205951,22 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" module \wrpick_SPR_spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A { \i } connect \Y $1 end process $group_0 @@ -99407,7 +205974,7 @@ module \wrpick_SPR_spr1 assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 1 \t0 process $group_1 assign \t0 1'0 @@ -99419,9 +205986,9 @@ module \wrpick_SPR_spr1 assign \o { \t0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" cell $reduce_bool $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -99438,11 +206005,11 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core" module \core - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire width 1 input 1 \core_reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:84" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 1 output 2 \corebusy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 1 output 3 \cu_st__rel_o @@ -99453,35 +206020,35 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 1 input 6 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 7 \cia__ren + wire width 4 input 7 \cia__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 8 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \wen + wire width 4 input 9 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 10 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire width 4 input 11 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" wire width 1 output 12 \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" wire width 1 \core_terminate_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 input 13 \rego + wire width 5 input 13 \core_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 input 14 \ea + wire width 5 input 14 \core_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 input 15 \reg1 + wire width 5 input 15 \core_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 16 \reg1_ok + wire width 1 input 16 \core_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 input 17 \reg2 + wire width 5 input 17 \core_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 18 \reg2_ok + wire width 1 input 18 \core_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 input 19 \reg3 + wire width 5 input 19 \core_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \reg3_ok + wire width 1 input 20 \core_reg3_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -99594,7 +206161,7 @@ module \core attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 input 21 \spro + wire width 10 input 21 \core_spro attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -99707,43 +206274,890 @@ module \core attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 input 22 \spr1 + wire width 10 input 22 \core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 23 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 input 24 \xer_in + wire width 1 input 23 \core_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 input 24 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 25 \fast1 + wire width 3 input 25 \core_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 26 \fast1_ok + wire width 1 input 26 \core_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 27 \fast2 + wire width 3 input 27 \core_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 28 \fast2_ok + wire width 1 input 28 \core_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 29 \fasto1 + wire width 3 input 29 \core_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 30 \fasto2 + wire width 3 input 30 \core_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 31 \cr_in1 + wire width 3 input 31 \core_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 32 \cr_in1_ok + wire width 1 input 32 \core_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 33 \cr_in2 + wire width 3 input 33 \core_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 34 \cr_in2_ok + wire width 1 input 34 \core_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 35 \cr_in2$1 + wire width 3 input 35 \core_cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 36 \cr_in2_ok$2 + wire width 1 input 36 \core_cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 37 \cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 64 input 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" - wire width 64 input 39 \cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" - wire width 32 input 40 \insn + wire width 3 input 37 \core_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 input 38 \core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 input 39 \core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 input 40 \core_core_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 input 41 \core_core_insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 11 input 42 \core_core_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 43 \core_core_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 44 \core_core_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 45 \core_core_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 46 \core_core_oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 input 47 \core_core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 input 48 \core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 input 49 \core_core_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 input 50 \core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 51 \core_core_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 input 52 \core_core_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 input 53 \core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" + wire width 32 input 54 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + wire width 1 input 55 \bigendian_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 56 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 57 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" + wire width 1 input 58 \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" + wire width 1 input 59 \issue_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 60 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 61 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 62 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 63 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 64 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 output 65 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 66 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 output 67 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 68 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 69 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 70 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 71 \issue__addr$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 72 \issue__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 73 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 74 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 75 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 76 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 77 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 78 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 79 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 80 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 81 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 82 \dbus__dat_w + attribute \src "simple/issuer.py:141" + wire width 1 \coresync_rst + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_alu0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_alu0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_alu0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 \fus_cu_rdmaskn_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_cr0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_cr0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 \fus_cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_branch0__cia + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_branch0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_branch0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_branch0__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_trap0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_trap0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 \fus_cu_rdmaskn_i$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_logical0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_logical0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_logical0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$15 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_spr0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_spr0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 \fus_cu_rdmaskn_i$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -99817,8 +207231,8 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" - wire width 7 input 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_div0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -99831,101 +207245,1306 @@ module \core attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" - wire width 11 input 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 43 \imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 44 \imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 1 input 45 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 46 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 47 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 48 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 49 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 input 50 \invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 input 51 \zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 input 52 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 input 53 \output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 input 54 \input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 input 55 \output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 input 56 \invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 input 57 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 input 58 \is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 input 59 \data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 input 60 \byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 input 61 \sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_div0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_div0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_mul0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_mul0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_shift_rot0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 \fus_cu_rdmaskn_i$27 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_ldst_ldst0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \fus_oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_ldst_ldst0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \fus_oper_i_ldst_ldst0__sign_extend attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 input 62 \ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 input 63 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 13 input 64 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 input 65 \read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 input 66 \write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 input 67 \write_cr0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 68 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82" - wire width 1 input 69 \ivalid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:83" - wire width 1 input 70 \issue_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 71 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 72 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 73 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 74 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 75 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 76 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 77 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 78 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 79 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 80 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 81 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 82 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 83 \dbus__dat_w - attribute \src "simple/issuer.py:102" - wire width 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_ldst_ldst0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \fus_cu_issue_i$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 \fus_cu_busy_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 \fus_src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 \fus_src3_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 \fus_src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 \fus_src3_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 \fus_src3_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 \fus_src4_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src5_i$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 \fus_src3_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src4_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src3_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src5_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src6_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src4_i$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_o_ok$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__rel_o$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__go_i$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__rel_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__go_i$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 \fus_dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_cr_a_ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_cr_a_ok$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_cr_a_ok$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ca_ok$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ca_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ov_ok$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ov_ok$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_ov_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_so_ok$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_so_ok$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_xer_so_ok$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 \fus_dest5_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 \fus_dest4_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 \fus_dest4_o$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 \fus_dest4_o$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__rel_o$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__go_i$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_fast1_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_fast1_ok$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_fast2_ok$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_nia_ok$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest4_o$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest5_o$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 \fus_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 \fus_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 \fus_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \fus_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 \fus_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 \fus_ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 \fus_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_ldst_port0_st_data_i_ok + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_st__go_i \cu_st__go_i + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \cu_issue_i \fus_cu_issue_i + connect \cu_busy_o \fus_cu_busy_o + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \cu_issue_i$1 \fus_cu_issue_i$4 + connect \cu_busy_o$2 \fus_cu_busy_o$5 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$6 + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \cu_issue_i$4 \fus_cu_issue_i$7 + connect \cu_busy_o$5 \fus_cu_busy_o$8 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$9 + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \cu_issue_i$7 \fus_cu_issue_i$10 + connect \cu_busy_o$8 \fus_cu_busy_o$11 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$12 + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \cu_issue_i$10 \fus_cu_issue_i$13 + connect \cu_busy_o$11 \fus_cu_busy_o$14 + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$15 + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \cu_issue_i$13 \fus_cu_issue_i$16 + connect \cu_busy_o$14 \fus_cu_busy_o$17 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$18 + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len + connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn + connect \cu_issue_i$16 \fus_cu_issue_i$19 + connect \cu_busy_o$17 \fus_cu_busy_o$20 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$21 + connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn + connect \cu_issue_i$19 \fus_cu_issue_i$22 + connect \cu_busy_o$20 \fus_cu_busy_o$23 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$24 + connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 + connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn + connect \cu_issue_i$22 \fus_cu_issue_i$25 + connect \cu_busy_o$23 \fus_cu_busy_o$26 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$27 + connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a + connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn + connect \cu_issue_i$25 \fus_cu_issue_i$28 + connect \cu_busy_o$26 \fus_cu_busy_o$29 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$30 + connect \cu_rd__rel_o \fus_cu_rd__rel_o + connect \cu_rd__go_i \fus_cu_rd__go_i + connect \src1_i \fus_src1_i + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$31 + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$32 + connect \src1_i$30 \fus_src1_i$33 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$34 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$35 + connect \src1_i$33 \fus_src1_i$36 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$37 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$38 + connect \src1_i$36 \fus_src1_i$39 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$40 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$41 + connect \src1_i$39 \fus_src1_i$42 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$43 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$44 + connect \src1_i$42 \fus_src1_i$45 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$46 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$47 + connect \src1_i$45 \fus_src1_i$48 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$49 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$50 + connect \src1_i$48 \fus_src1_i$51 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$52 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$53 + connect \src1_i$51 \fus_src1_i$54 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$55 + connect \src2_i$53 \fus_src2_i$56 + connect \src2_i$54 \fus_src2_i$57 + connect \src2_i$55 \fus_src2_i$58 + connect \src2_i$56 \fus_src2_i$59 + connect \src2_i$57 \fus_src2_i$60 + connect \src2_i$58 \fus_src2_i$61 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$62 + connect \src3_i$60 \fus_src3_i$63 + connect \src3_i$61 \fus_src3_i$64 + connect \src4_i \fus_src4_i + connect \src3_i$62 \fus_src3_i$65 + connect \src3_i$63 \fus_src3_i$66 + connect \src4_i$64 \fus_src4_i$67 + connect \src4_i$65 \fus_src4_i$68 + connect \src6_i \fus_src6_i + connect \src5_i \fus_src5_i + connect \src5_i$66 \fus_src5_i$69 + connect \src3_i$67 \fus_src3_i$70 + connect \src4_i$68 \fus_src4_i$71 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$72 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$73 + connect \src3_i$71 \fus_src3_i$74 + connect \src5_i$72 \fus_src5_i$75 + connect \src6_i$73 \fus_src6_i$76 + connect \src1_i$74 \fus_src1_i$77 + connect \src3_i$75 \fus_src3_i$78 + connect \src3_i$76 \fus_src3_i$79 + connect \src2_i$77 \fus_src2_i$80 + connect \src4_i$78 \fus_src4_i$81 + connect \src2_i$79 \fus_src2_i$82 + connect \o_ok \fus_o_ok + connect \cu_wr__rel_o \fus_cu_wr__rel_o + connect \cu_wr__go_i \fus_cu_wr__go_i + connect \o_ok$80 \fus_o_ok$83 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$84 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$85 + connect \o_ok$83 \fus_o_ok$86 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$87 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$88 + connect \o_ok$86 \fus_o_ok$89 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$90 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$91 + connect \o_ok$89 \fus_o_ok$92 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$93 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$94 + connect \o_ok$92 \fus_o_ok$95 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$96 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$97 + connect \o_ok$95 \fus_o_ok$98 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$99 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$100 + connect \o_ok$98 \fus_o_ok$101 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$102 + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$103 + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$104 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$105 + connect \dest1_o \fus_dest1_o + connect \dest1_o$103 \fus_dest1_o$106 + connect \dest1_o$104 \fus_dest1_o$107 + connect \dest1_o$105 \fus_dest1_o$108 + connect \dest1_o$106 \fus_dest1_o$109 + connect \dest1_o$107 \fus_dest1_o$110 + connect \dest1_o$108 \fus_dest1_o$111 + connect \dest1_o$109 \fus_dest1_o$112 + connect \o \fus_o + connect \ea \fus_ea + connect \full_cr_ok \fus_full_cr_ok + connect \dest2_o \fus_dest2_o + connect \cr_a_ok \fus_cr_a_ok + connect \cr_a_ok$110 \fus_cr_a_ok$113 + connect \cr_a_ok$111 \fus_cr_a_ok$114 + connect \cr_a_ok$112 \fus_cr_a_ok$115 + connect \cr_a_ok$113 \fus_cr_a_ok$116 + connect \cr_a_ok$114 \fus_cr_a_ok$117 + connect \dest2_o$115 \fus_dest2_o$118 + connect \dest3_o \fus_dest3_o + connect \dest2_o$116 \fus_dest2_o$119 + connect \dest2_o$117 \fus_dest2_o$120 + connect \dest2_o$118 \fus_dest2_o$121 + connect \dest2_o$119 \fus_dest2_o$122 + connect \xer_ca_ok \fus_xer_ca_ok + connect \xer_ca_ok$120 \fus_xer_ca_ok$123 + connect \xer_ca_ok$121 \fus_xer_ca_ok$124 + connect \dest3_o$122 \fus_dest3_o$125 + connect \dest6_o \fus_dest6_o + connect \dest3_o$123 \fus_dest3_o$126 + connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$124 \fus_xer_ov_ok$127 + connect \xer_ov_ok$125 \fus_xer_ov_ok$128 + connect \xer_ov_ok$126 \fus_xer_ov_ok$129 + connect \dest4_o \fus_dest4_o + connect \dest5_o \fus_dest5_o + connect \dest3_o$127 \fus_dest3_o$130 + connect \dest3_o$128 \fus_dest3_o$131 + connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$129 \fus_xer_so_ok$132 + connect \xer_so_ok$130 \fus_xer_so_ok$133 + connect \xer_so_ok$131 \fus_xer_so_ok$134 + connect \dest5_o$132 \fus_dest5_o$135 + connect \dest4_o$133 \fus_dest4_o$136 + connect \dest4_o$134 \fus_dest4_o$137 + connect \dest4_o$135 \fus_dest4_o$138 + connect \fast1_ok \fus_fast1_ok + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$139 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$140 + connect \fast1_ok$138 \fus_fast1_ok$141 + connect \fast1_ok$139 \fus_fast1_ok$142 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$140 \fus_fast2_ok$143 + connect \dest1_o$141 \fus_dest1_o$144 + connect \dest2_o$142 \fus_dest2_o$145 + connect \dest3_o$143 \fus_dest3_o$146 + connect \dest2_o$144 \fus_dest2_o$147 + connect \dest3_o$145 \fus_dest3_o$148 + connect \nia_ok \fus_nia_ok + connect \nia_ok$146 \fus_nia_ok$149 + connect \dest3_o$147 \fus_dest3_o$150 + connect \dest4_o$148 \fus_dest4_o$151 + connect \msr_ok \fus_msr_ok + connect \dest5_o$149 \fus_dest5_o$152 + connect \spr1_ok \fus_spr1_ok + connect \dest2_o$150 \fus_dest2_o$153 + connect \coresync_rst \coresync_rst + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + end + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \dbus__cyc \dbus__cyc + connect \dbus__ack \dbus__ack + connect \dbus__err \dbus__err + connect \dbus__stb \dbus__stb + connect \dbus__sel \dbus__sel + connect \dbus__dat_r \dbus__dat_r + connect \dbus__adr \dbus__adr + connect \dbus__we \dbus__we + connect \dbus__dat_w \dbus__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_dest1__wen + cell \int \int + connect \coresync_clk \coresync_clk + connect \dmi__addr \dmi__addr + connect \dmi__ren \dmi__ren + connect \dmi__data_o \dmi__data_o + connect \src1__data_o \int_src1__data_o + connect \src1__addr \int_src1__addr + connect \src1__ren \int_src1__ren + connect \src2__data_o \int_src2__data_o + connect \src2__addr \int_src2__addr + connect \src2__ren \int_src2__ren + connect \src3__data_o \int_src3__data_o + connect \src3__addr \int_src3__addr + connect \src3__ren \int_src3__ren + connect \dest1__data_i \int_dest1__data_i + connect \dest1__addr \int_dest1__addr + connect \dest1__wen \int_dest1__wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_wen + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \full_rd2__ren \full_rd2__ren + connect \full_rd2__data_o \full_rd2__data_o + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \data_i \cr_data_i + connect \wen \cr_wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen$155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen$157 + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \full_rd__ren \full_rd__ren + connect \full_rd__data_o \full_rd__data_o + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \data_i \xer_data_i + connect \wen \xer_wen + connect \data_i$1 \xer_data_i$154 + connect \wen$2 \xer_wen$155 + connect \data_i$3 \xer_data_i$156 + connect \wen$4 \xer_wen$157 + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \fast_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \fast_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \fast_dest1__wen + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \issue__addr \issue__addr + connect \issue__ren \issue__ren + connect \issue__data_o \issue__data_o + connect \issue__addr$1 \issue__addr$3 + connect \issue__wen \issue__wen + connect \issue__data_i \issue__data_i + connect \src1__data_o \fast_src1__data_o + connect \src1__addr \fast_src1__addr + connect \src1__ren \fast_src1__ren + connect \src2__data_o \fast_src2__data_o + connect \src2__addr \fast_src2__addr + connect \src2__ren \fast_src2__ren + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__addr \fast_dest1__addr + connect \dest1__wen \fast_dest1__wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \state_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \state_data_i$158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \state_wen + cell \state \state + connect \coresync_clk \coresync_clk + connect \cia__ren \cia__ren + connect \cia__data_o \cia__data_o + connect \wen \wen + connect \data_i \data_i + connect \msr__ren \msr__ren + connect \msr__data_o \msr__data_o + connect \state_nia_wen \state_nia_wen + connect \data_i$1 \state_data_i + connect \data_i$2 \state_data_i$158 + connect \wen$3 \state_wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 \spr_spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 \spr_spr1__addr$159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_spr1__wen + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__addr \spr_spr1__addr + connect \spr1__ren \spr_spr1__ren + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__addr$1 \spr_spr1__addr$159 + connect \spr1__wen \spr_spr1__wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_ALU_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100000,7 +208619,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_alu0__insn_type + wire width 7 \dec_ALU_ALU_ALU__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100014,152 +208633,69 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_alu0__fn_unit + wire width 11 \dec_ALU_ALU_ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_alu0__imm_data__imm + wire width 64 \dec_ALU_ALU_ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__imm_data__imm_ok + wire width 1 \dec_ALU_ALU_ALU__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__rc__rc + wire width 1 \dec_ALU_ALU_ALU__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__rc__rc_ok + wire width 1 \dec_ALU_ALU_ALU__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__oe__oe + wire width 1 \dec_ALU_ALU_ALU__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__oe__oe_ok + wire width 1 \dec_ALU_ALU_ALU__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__invert_in + wire width 1 \dec_ALU_ALU_ALU__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__zero_a + wire width 1 \dec_ALU_ALU_ALU__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__invert_out + wire width 1 \dec_ALU_ALU_ALU__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__write_cr0 + wire width 1 \dec_ALU_ALU_ALU__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_alu0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_alu0__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_alu0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 \fus_cu_rdmaskn_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_cr0__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_cr0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_cr0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_cr0__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_cr0__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 \fus_cu_rdmaskn_i$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_branch0__cia + wire width 2 \dec_ALU_ALU_ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_ALU_ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_ALU_ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_ALU_ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_ALU_ALU_ALU__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_ALU_ALU_ALU__insn + cell \dec_ALU \dec_ALU + connect \raw_opcode_in \dec_ALU_raw_opcode_in + connect \bigendian \dec_ALU_bigendian + connect \ALU_ALU__insn_type \dec_ALU_ALU_ALU__insn_type + connect \ALU_ALU__fn_unit \dec_ALU_ALU_ALU__fn_unit + connect \ALU_ALU__imm_data__data \dec_ALU_ALU_ALU__imm_data__data + connect \ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__ok + connect \ALU_ALU__rc__rc \dec_ALU_ALU_ALU__rc__rc + connect \ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__ok + connect \ALU_ALU__oe__oe \dec_ALU_ALU_ALU__oe__oe + connect \ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__ok + connect \ALU_ALU__invert_in \dec_ALU_ALU_ALU__invert_in + connect \ALU_ALU__zero_a \dec_ALU_ALU_ALU__zero_a + connect \ALU_ALU__invert_out \dec_ALU_ALU_ALU__invert_out + connect \ALU_ALU__write_cr0 \dec_ALU_ALU_ALU__write_cr0 + connect \ALU_ALU__input_carry \dec_ALU_ALU_ALU__input_carry + connect \ALU_ALU__output_carry \dec_ALU_ALU_ALU__output_carry + connect \ALU_ALU__is_32bit \dec_ALU_ALU_ALU__is_32bit + connect \ALU_ALU__is_signed \dec_ALU_ALU_ALU__is_signed + connect \ALU_ALU__data_len \dec_ALU_ALU_ALU__data_len + connect \ALU_ALU__insn \dec_ALU_ALU_ALU__insn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_CR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_CR_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100234,7 +208770,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_branch0__insn_type + wire width 7 \dec_CR_CR_CR__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100248,23 +208784,22 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_branch0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_branch0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_branch0__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_branch0__imm_data__imm_ok + wire width 11 \dec_CR_CR_CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_branch0__lk + wire width 32 \dec_CR_CR_CR__insn + cell \dec_CR \dec_CR + connect \raw_opcode_in \dec_CR_raw_opcode_in + connect \bigendian \dec_CR_bigendian + connect \CR_CR__insn_type \dec_CR_CR_CR__insn_type + connect \CR_CR__fn_unit \dec_CR_CR_CR__fn_unit + connect \CR_CR__insn \dec_CR_CR_CR__insn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_BRANCH_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_BRANCH_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_branch0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$8 + wire width 64 \dec_BRANCH_BRANCH_BRANCH__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100339,7 +208874,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_trap0__insn_type + wire width 7 \dec_BRANCH_BRANCH_BRANCH__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100353,25 +208888,34 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_trap0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_trap0__insn + wire width 11 \dec_BRANCH_BRANCH_BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_trap0__msr + wire width 32 \dec_BRANCH_BRANCH_BRANCH__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_trap0__cia + wire width 64 \dec_BRANCH_BRANCH_BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_trap0__is_32bit + wire width 1 \dec_BRANCH_BRANCH_BRANCH__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \fus_oper_i_alu_trap0__traptype + wire width 1 \dec_BRANCH_BRANCH_BRANCH__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 \fus_cu_rdmaskn_i$11 + wire width 1 \dec_BRANCH_BRANCH_BRANCH__is_32bit + cell \dec_BRANCH \dec_BRANCH + connect \core_pc \core_pc + connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + connect \bigendian \dec_BRANCH_bigendian + connect \BRANCH_BRANCH__cia \dec_BRANCH_BRANCH_BRANCH__cia + connect \BRANCH_BRANCH__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type + connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit + connect \BRANCH_BRANCH__insn \dec_BRANCH_BRANCH_BRANCH__insn + connect \BRANCH_BRANCH__imm_data__data \dec_BRANCH_BRANCH_BRANCH__imm_data__data + connect \BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__ok + connect \BRANCH_BRANCH__lk \dec_BRANCH_BRANCH_BRANCH__lk + connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_LOGICAL_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100446,7 +208990,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_logical0__insn_type + wire width 7 \dec_LOGICAL_LOGICAL_LOGICAL__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100460,49 +209004,69 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_logical0__fn_unit + wire width 11 \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_logical0__imm_data__imm + wire width 64 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__imm_data__imm_ok + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__rc__rc + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__rc__rc_ok + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__oe__oe + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__oe__oe_ok + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__invert_in + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__zero_a + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_logical0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_logical0__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_logical0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 2 \fus_cu_rdmaskn_i$14 + wire width 2 \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LOGICAL_LOGICAL_LOGICAL__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LOGICAL_LOGICAL_LOGICAL__insn + cell \dec_LOGICAL \dec_LOGICAL + connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + connect \bigendian \dec_LOGICAL_bigendian + connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL_LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL_LOGICAL__rc__rc \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL_LOGICAL__oe__oe \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + connect \LOGICAL_LOGICAL__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + connect \LOGICAL_LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len + connect \LOGICAL_LOGICAL__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_SPR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_SPR_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100577,7 +209141,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_spr0__insn_type + wire width 7 \dec_SPR_SPR_SPR__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100591,17 +209155,23 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_spr0__fn_unit + wire width 11 \dec_SPR_SPR_SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_spr0__insn + wire width 32 \dec_SPR_SPR_SPR__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_spr0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 \fus_cu_rdmaskn_i$17 + wire width 1 \dec_SPR_SPR_SPR__is_32bit + cell \dec_SPR \dec_SPR + connect \raw_opcode_in \dec_SPR_raw_opcode_in + connect \bigendian \dec_SPR_bigendian + connect \SPR_SPR__insn_type \dec_SPR_SPR_SPR__insn_type + connect \SPR_SPR__fn_unit \dec_SPR_SPR_SPR__fn_unit + connect \SPR_SPR__insn \dec_SPR_SPR_SPR__insn + connect \SPR_SPR__is_32bit \dec_SPR_SPR_SPR__is_32bit + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_DIV_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100676,7 +209246,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_div0__insn_type + wire width 7 \dec_DIV_DIV_DIV__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100690,49 +209260,69 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_div0__fn_unit + wire width 11 \dec_DIV_DIV_DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_div0__imm_data__imm + wire width 64 \dec_DIV_DIV_DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__imm_data__imm_ok + wire width 1 \dec_DIV_DIV_DIV__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__rc__rc + wire width 1 \dec_DIV_DIV_DIV__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__rc__rc_ok + wire width 1 \dec_DIV_DIV_DIV__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__oe__oe + wire width 1 \dec_DIV_DIV_DIV__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__oe__oe_ok + wire width 1 \dec_DIV_DIV_DIV__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__invert_in + wire width 1 \dec_DIV_DIV_DIV__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__zero_a + wire width 1 \dec_DIV_DIV_DIV__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_div0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_div0__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_div0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$20 + wire width 2 \dec_DIV_DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_DIV_DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_DIV_DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_DIV_DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_DIV_DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_DIV_DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_DIV_DIV_DIV__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_DIV_DIV_DIV__insn + cell \dec_DIV \dec_DIV + connect \raw_opcode_in \dec_DIV_raw_opcode_in + connect \bigendian \dec_DIV_bigendian + connect \DIV_DIV__insn_type \dec_DIV_DIV_DIV__insn_type + connect \DIV_DIV__fn_unit \dec_DIV_DIV_DIV__fn_unit + connect \DIV_DIV__imm_data__data \dec_DIV_DIV_DIV__imm_data__data + connect \DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__ok + connect \DIV_DIV__rc__rc \dec_DIV_DIV_DIV__rc__rc + connect \DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__ok + connect \DIV_DIV__oe__oe \dec_DIV_DIV_DIV__oe__oe + connect \DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__ok + connect \DIV_DIV__invert_in \dec_DIV_DIV_DIV__invert_in + connect \DIV_DIV__zero_a \dec_DIV_DIV_DIV__zero_a + connect \DIV_DIV__input_carry \dec_DIV_DIV_DIV__input_carry + connect \DIV_DIV__invert_out \dec_DIV_DIV_DIV__invert_out + connect \DIV_DIV__write_cr0 \dec_DIV_DIV_DIV__write_cr0 + connect \DIV_DIV__output_carry \dec_DIV_DIV_DIV__output_carry + connect \DIV_DIV__is_32bit \dec_DIV_DIV_DIV__is_32bit + connect \DIV_DIV__is_signed \dec_DIV_DIV_DIV__is_signed + connect \DIV_DIV__data_len \dec_DIV_DIV_DIV__data_len + connect \DIV_DIV__insn \dec_DIV_DIV_DIV__insn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_MUL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_MUL_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100807,7 +209397,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_mul0__insn_type + wire width 7 \dec_MUL_MUL_MUL__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100821,33 +209411,47 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_mul0__fn_unit + wire width 11 \dec_MUL_MUL_MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_mul0__imm_data__imm + wire width 64 \dec_MUL_MUL_MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__imm_data__imm_ok + wire width 1 \dec_MUL_MUL_MUL__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__rc__rc + wire width 1 \dec_MUL_MUL_MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__rc__rc_ok + wire width 1 \dec_MUL_MUL_MUL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__oe__oe + wire width 1 \dec_MUL_MUL_MUL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__oe__oe_ok + wire width 1 \dec_MUL_MUL_MUL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__write_cr0 + wire width 1 \dec_MUL_MUL_MUL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__is_32bit + wire width 1 \dec_MUL_MUL_MUL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__is_signed + wire width 1 \dec_MUL_MUL_MUL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_mul0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$23 + wire width 32 \dec_MUL_MUL_MUL__insn + cell \dec_MUL \dec_MUL + connect \raw_opcode_in \dec_MUL_raw_opcode_in + connect \bigendian \dec_MUL_bigendian + connect \MUL_MUL__insn_type \dec_MUL_MUL_MUL__insn_type + connect \MUL_MUL__fn_unit \dec_MUL_MUL_MUL__fn_unit + connect \MUL_MUL__imm_data__data \dec_MUL_MUL_MUL__imm_data__data + connect \MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__ok + connect \MUL_MUL__rc__rc \dec_MUL_MUL_MUL__rc__rc + connect \MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__ok + connect \MUL_MUL__oe__oe \dec_MUL_MUL_MUL__oe__oe + connect \MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__ok + connect \MUL_MUL__write_cr0 \dec_MUL_MUL_MUL__write_cr0 + connect \MUL_MUL__is_32bit \dec_MUL_MUL_MUL__is_32bit + connect \MUL_MUL__is_signed \dec_MUL_MUL_MUL__is_signed + connect \MUL_MUL__insn \dec_MUL_MUL_MUL__insn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_SHIFT_ROT_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100922,7 +209526,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100936,43 +209540,63 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_shift_rot0__fn_unit + wire width 11 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__imm + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__imm_data__imm_ok + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc_ok + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe_ok + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_shift_rot0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_shift_rot0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 \fus_cu_rdmaskn_i$26 + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + cell \dec_SHIFT_ROT \dec_SHIFT_ROT + connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + connect \bigendian \dec_SHIFT_ROT_bigendian + connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT_SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT_SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT_SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT_SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" + wire width 1 \dec_LDST_bigendian attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -101047,1219 +209671,468 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_ldst_ldst0__insn_type + wire width 7 \dec_LDST_LDST_LDST__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_ldst_ldst0__imm_data__imm + wire width 11 \dec_LDST_LDST_LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__imm_data__imm_ok + wire width 64 \dec_LDST_LDST_LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__zero_a + wire width 1 \dec_LDST_LDST_LDST__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__rc__rc + wire width 1 \dec_LDST_LDST_LDST__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__rc__rc_ok + wire width 1 \dec_LDST_LDST_LDST__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__oe__oe + wire width 1 \dec_LDST_LDST_LDST__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__oe__oe_ok + wire width 1 \dec_LDST_LDST_LDST__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__is_32bit + wire width 1 \dec_LDST_LDST_LDST__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__is_signed + wire width 1 \dec_LDST_LDST_LDST__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_ldst_ldst0__data_len + wire width 1 \dec_LDST_LDST_LDST__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__byte_reverse + wire width 4 \dec_LDST_LDST_LDST__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__sign_extend + wire width 1 \dec_LDST_LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \dec_LDST_LDST_LDST__sign_extend attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 \fus_cu_issue_i$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \fus_cu_busy_o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__rel_o$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__go_i$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_rd__rel_o$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_rd__go_i$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__rel_o$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__go_i$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 \fus_src3_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 \fus_src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 \fus_src3_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 \fus_src3_i$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src4_i$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src4_i$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 \fus_src3_i$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src4_i$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src3_i$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src5_i$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src6_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src4_i$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__rel_o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__go_i$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_wr__rel_o$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_wr__go_i$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__rel_o$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__go_i$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__rel_o$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__go_i$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__rel_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__go_i$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 \fus_dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest5_o$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest4_o$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest4_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest4_o$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast2_ok$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_nia_ok$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest4_o$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest5_o$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 \fus_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 \fus_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 \fus_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 \fus_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 \fus_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 \fus_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 \fus_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_st_data_i_ok - cell \fus \fus - connect \coresync_clk \coresync_clk - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_st__go_i \cu_st__go_i - connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__imm \fus_oper_i_alu_alu0__imm_data__imm - connect \oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm_ok - connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc_ok - connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe_ok - connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a - connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn - connect \cu_issue_i \fus_cu_issue_i - connect \cu_busy_o \fus_cu_busy_o - connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type - connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__read_cr_whole \fus_oper_i_alu_cr0__read_cr_whole - connect \oper_i_alu_cr0__write_cr_whole \fus_oper_i_alu_cr0__write_cr_whole - connect \cu_issue_i$1 \fus_cu_issue_i$3 - connect \cu_busy_o$2 \fus_cu_busy_o$4 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$5 - connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__imm_data__imm \fus_oper_i_alu_branch0__imm_data__imm - connect \oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm_ok - connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk - connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit - connect \cu_issue_i$4 \fus_cu_issue_i$6 - connect \cu_busy_o$5 \fus_cu_busy_o$7 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$8 - connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype - connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr - connect \cu_issue_i$7 \fus_cu_issue_i$9 - connect \cu_busy_o$8 \fus_cu_busy_o$10 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$11 - connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__imm \fus_oper_i_alu_logical0__imm_data__imm - connect \oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm_ok - connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc_ok - connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe_ok - connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a - connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn - connect \cu_issue_i$10 \fus_cu_issue_i$12 - connect \cu_busy_o$11 \fus_cu_busy_o$13 - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$14 - connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit - connect \cu_issue_i$13 \fus_cu_issue_i$15 - connect \cu_busy_o$14 \fus_cu_busy_o$16 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$17 - connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__imm \fus_oper_i_alu_div0__imm_data__imm - connect \oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm_ok - connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc_ok - connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe_ok - connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a - connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len - connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn - connect \cu_issue_i$16 \fus_cu_issue_i$18 - connect \cu_busy_o$17 \fus_cu_busy_o$19 - connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$20 - connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__imm \fus_oper_i_alu_mul0__imm_data__imm - connect \oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm_ok - connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc_ok - connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe_ok - connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 - connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn - connect \cu_issue_i$19 \fus_cu_issue_i$21 - connect \cu_busy_o$20 \fus_cu_busy_o$22 - connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$23 - connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__imm \fus_oper_i_alu_shift_rot0__imm_data__imm - connect \oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm_ok - connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc_ok - connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe_ok - connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn - connect \cu_issue_i$22 \fus_cu_issue_i$24 - connect \cu_busy_o$23 \fus_cu_busy_o$25 - connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$26 - connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__imm_data__imm \fus_oper_i_ldst_ldst0__imm_data__imm - connect \oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm_ok - connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a - connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc_ok - connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe_ok - connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode - connect \cu_issue_i$25 \fus_cu_issue_i$27 - connect \cu_busy_o$26 \fus_cu_busy_o$28 - connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$29 - connect \cu_rd__rel_o \fus_cu_rd__rel_o - connect \cu_rd__go_i \fus_cu_rd__go_i - connect \src1_i \fus_src1_i - connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$30 - connect \cu_rd__go_i$29 \fus_cu_rd__go_i$31 - connect \src1_i$30 \fus_src1_i$32 - connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$33 - connect \cu_rd__go_i$32 \fus_cu_rd__go_i$34 - connect \src1_i$33 \fus_src1_i$35 - connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$36 - connect \cu_rd__go_i$35 \fus_cu_rd__go_i$37 - connect \src1_i$36 \fus_src1_i$38 - connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$39 - connect \cu_rd__go_i$38 \fus_cu_rd__go_i$40 - connect \src1_i$39 \fus_src1_i$41 - connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$42 - connect \cu_rd__go_i$41 \fus_cu_rd__go_i$43 - connect \src1_i$42 \fus_src1_i$44 - connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$45 - connect \cu_rd__go_i$44 \fus_cu_rd__go_i$46 - connect \src1_i$45 \fus_src1_i$47 - connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$48 - connect \cu_rd__go_i$47 \fus_cu_rd__go_i$49 - connect \src1_i$48 \fus_src1_i$50 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$51 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$52 - connect \src1_i$51 \fus_src1_i$53 - connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$54 - connect \src2_i$53 \fus_src2_i$55 - connect \src2_i$54 \fus_src2_i$56 - connect \src2_i$55 \fus_src2_i$57 - connect \src2_i$56 \fus_src2_i$58 - connect \src2_i$57 \fus_src2_i$59 - connect \src2_i$58 \fus_src2_i$60 - connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$61 - connect \src3_i$60 \fus_src3_i$62 - connect \src4_i \fus_src4_i - connect \src3_i$61 \fus_src3_i$63 - connect \src3_i$62 \fus_src3_i$64 - connect \src4_i$63 \fus_src4_i$65 - connect \src6_i \fus_src6_i - connect \src4_i$64 \fus_src4_i$66 - connect \src5_i \fus_src5_i - connect \src3_i$65 \fus_src3_i$67 - connect \src4_i$66 \fus_src4_i$68 - connect \cu_rd__rel_o$67 \fus_cu_rd__rel_o$69 - connect \cu_rd__go_i$68 \fus_cu_rd__go_i$70 - connect \src3_i$69 \fus_src3_i$71 - connect \src5_i$70 \fus_src5_i$72 - connect \src6_i$71 \fus_src6_i$73 - connect \src1_i$72 \fus_src1_i$74 - connect \src3_i$73 \fus_src3_i$75 - connect \src3_i$74 \fus_src3_i$76 - connect \src2_i$75 \fus_src2_i$77 - connect \src4_i$76 \fus_src4_i$78 - connect \src2_i$77 \fus_src2_i$79 - connect \o_ok \fus_o_ok - connect \cu_wr__rel_o \fus_cu_wr__rel_o - connect \cu_wr__go_i \fus_cu_wr__go_i - connect \o_ok$78 \fus_o_ok$80 - connect \cu_wr__rel_o$79 \fus_cu_wr__rel_o$81 - connect \cu_wr__go_i$80 \fus_cu_wr__go_i$82 - connect \o_ok$81 \fus_o_ok$83 - connect \cu_wr__rel_o$82 \fus_cu_wr__rel_o$84 - connect \cu_wr__go_i$83 \fus_cu_wr__go_i$85 - connect \o_ok$84 \fus_o_ok$86 - connect \cu_wr__rel_o$85 \fus_cu_wr__rel_o$87 - connect \cu_wr__go_i$86 \fus_cu_wr__go_i$88 - connect \o_ok$87 \fus_o_ok$89 - connect \cu_wr__rel_o$88 \fus_cu_wr__rel_o$90 - connect \cu_wr__go_i$89 \fus_cu_wr__go_i$91 - connect \o_ok$90 \fus_o_ok$92 - connect \cu_wr__rel_o$91 \fus_cu_wr__rel_o$93 - connect \cu_wr__go_i$92 \fus_cu_wr__go_i$94 - connect \o_ok$93 \fus_o_ok$95 - connect \cu_wr__rel_o$94 \fus_cu_wr__rel_o$96 - connect \cu_wr__go_i$95 \fus_cu_wr__go_i$97 - connect \o_ok$96 \fus_o_ok$98 - connect \cu_wr__rel_o$97 \fus_cu_wr__rel_o$99 - connect \cu_wr__go_i$98 \fus_cu_wr__go_i$100 - connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$101 - connect \cu_wr__go_i$100 \fus_cu_wr__go_i$102 - connect \dest1_o \fus_dest1_o - connect \dest1_o$101 \fus_dest1_o$103 - connect \dest1_o$102 \fus_dest1_o$104 - connect \dest1_o$103 \fus_dest1_o$105 - connect \dest1_o$104 \fus_dest1_o$106 - connect \dest1_o$105 \fus_dest1_o$107 - connect \dest1_o$106 \fus_dest1_o$108 - connect \dest1_o$107 \fus_dest1_o$109 - connect \o \fus_o - connect \ea \fus_ea - connect \full_cr_ok \fus_full_cr_ok - connect \dest2_o \fus_dest2_o - connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$108 \fus_cr_a_ok$110 - connect \cr_a_ok$109 \fus_cr_a_ok$111 - connect \cr_a_ok$110 \fus_cr_a_ok$112 - connect \cr_a_ok$111 \fus_cr_a_ok$113 - connect \cr_a_ok$112 \fus_cr_a_ok$114 - connect \dest2_o$113 \fus_dest2_o$115 - connect \dest3_o \fus_dest3_o - connect \dest2_o$114 \fus_dest2_o$116 - connect \dest2_o$115 \fus_dest2_o$117 - connect \dest2_o$116 \fus_dest2_o$118 - connect \dest2_o$117 \fus_dest2_o$119 - connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$118 \fus_xer_ca_ok$120 - connect \xer_ca_ok$119 \fus_xer_ca_ok$121 - connect \xer_ca_ok$120 \fus_xer_ca_ok$122 - connect \dest3_o$121 \fus_dest3_o$123 - connect \dest3_o$122 \fus_dest3_o$124 - connect \dest6_o \fus_dest6_o - connect \dest3_o$123 \fus_dest3_o$125 - connect \xer_ov_ok \fus_xer_ov_ok - connect \xer_ov_ok$124 \fus_xer_ov_ok$126 - connect \xer_ov_ok$125 \fus_xer_ov_ok$127 - connect \xer_ov_ok$126 \fus_xer_ov_ok$128 - connect \dest4_o \fus_dest4_o - connect \dest5_o \fus_dest5_o - connect \dest3_o$127 \fus_dest3_o$129 - connect \dest3_o$128 \fus_dest3_o$130 - connect \xer_so_ok \fus_xer_so_ok - connect \xer_so_ok$129 \fus_xer_so_ok$131 - connect \xer_so_ok$130 \fus_xer_so_ok$132 - connect \xer_so_ok$131 \fus_xer_so_ok$133 - connect \dest5_o$132 \fus_dest5_o$134 - connect \dest4_o$133 \fus_dest4_o$135 - connect \dest4_o$134 \fus_dest4_o$136 - connect \dest4_o$135 \fus_dest4_o$137 - connect \fast1_ok \fus_fast1_ok - connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$138 - connect \cu_wr__go_i$137 \fus_cu_wr__go_i$139 - connect \fast1_ok$138 \fus_fast1_ok$140 - connect \fast1_ok$139 \fus_fast1_ok$141 - connect \fast2_ok \fus_fast2_ok - connect \fast2_ok$140 \fus_fast2_ok$142 - connect \dest1_o$141 \fus_dest1_o$143 - connect \dest2_o$142 \fus_dest2_o$144 - connect \dest3_o$143 \fus_dest3_o$145 - connect \dest2_o$144 \fus_dest2_o$146 - connect \dest3_o$145 \fus_dest3_o$147 - connect \nia_ok \fus_nia_ok - connect \nia_ok$146 \fus_nia_ok$148 - connect \dest3_o$147 \fus_dest3_o$149 - connect \dest4_o$148 \fus_dest4_o$150 - connect \msr_ok \fus_msr_ok - connect \dest5_o$149 \fus_dest5_o$151 - connect \spr1_ok \fus_spr1_ok - connect \dest2_o$150 \fus_dest2_o$152 - connect \coresync_rst \coresync_rst - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - end - cell \l0 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_dest1__wen - cell \int \int - connect \coresync_clk \coresync_clk - connect \dmi__addr \dmi__addr - connect \dmi__ren \dmi__ren - connect \dmi__data_o \dmi__data_o - connect \src1__data_o \int_src1__data_o - connect \src1__addr \int_src1__addr - connect \src1__ren \int_src1__ren - connect \src2__data_o \int_src2__data_o - connect \src2__addr \int_src2__addr - connect \src2__ren \int_src2__ren - connect \src3__data_o \int_src3__data_o - connect \src3__addr \int_src3__addr - connect \src3__ren \int_src3__ren - connect \dest1__data_i \int_dest1__data_i - connect \dest1__addr \int_dest1__addr - connect \dest1__wen \int_dest1__wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \cr_full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \cr_full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_wr__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_wen - cell \cr \cr - connect \coresync_clk \coresync_clk - connect \full_rd__data_o \cr_full_rd__data_o - connect \full_rd__ren \cr_full_rd__ren - connect \src1__data_o \cr_src1__data_o - connect \src1__ren \cr_src1__ren - connect \src2__data_o \cr_src2__data_o - connect \src2__ren \cr_src2__ren - connect \src3__data_o \cr_src3__data_o - connect \src3__ren \cr_src3__ren - connect \full_wr__data_i \cr_full_wr__data_i - connect \full_wr__wen \cr_full_wr__wen - connect \data_i \cr_data_i - connect \wen \cr_wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$153 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$154 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$156 - cell \xer \xer - connect \coresync_clk \coresync_clk - connect \src1__data_o \xer_src1__data_o - connect \src1__ren \xer_src1__ren - connect \src2__data_o \xer_src2__data_o - connect \src2__ren \xer_src2__ren - connect \src3__data_o \xer_src3__data_o - connect \src3__ren \xer_src3__ren - connect \data_i \xer_data_i - connect \wen \xer_wen - connect \data_i$1 \xer_data_i$153 - connect \wen$2 \xer_wen$154 - connect \data_i$3 \xer_data_i$155 - connect \wen$4 \xer_wen$156 - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \fast_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \fast_dest1__wen - cell \fast \fast - connect \coresync_clk \coresync_clk - connect \src1__data_o \fast_src1__data_o - connect \src1__addr \fast_src1__addr - connect \src1__ren \fast_src1__ren - connect \src2__data_o \fast_src2__data_o - connect \src2__addr \fast_src2__addr - connect \src2__ren \fast_src2__ren - connect \dest1__data_i \fast_dest1__data_i - connect \dest1__addr \fast_dest1__addr - connect \dest1__wen \fast_dest1__wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$157 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \state_wen - cell \state \state - connect \coresync_clk \coresync_clk - connect \cia__ren \cia__ren - connect \cia__data_o \cia__data_o - connect \wen \wen - connect \data_i \data_i - connect \msr__ren \msr__ren - connect \msr__data_o \msr__data_o - connect \state_nia_wen \state_nia_wen - connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$157 - connect \wen$3 \state_wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \spr_spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$158 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \spr_spr1__wen - cell \spr \spr - connect \coresync_clk \coresync_clk - connect \spr1__data_o \spr_spr1__data_o - connect \spr1__addr \spr_spr1__addr - connect \spr1__ren \spr_spr1__ren - connect \spr1__data_i \spr_spr1__data_i - connect \spr1__addr$1 \spr_spr1__addr$158 - connect \spr1__wen \spr_spr1__wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 \dec_LDST_LDST_LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LDST_LDST_LDST__insn + cell \dec_LDST \dec_LDST + connect \raw_opcode_in \dec_LDST_raw_opcode_in + connect \bigendian \dec_LDST_bigendian + connect \LDST_LDST__insn_type \dec_LDST_LDST_LDST__insn_type + connect \LDST_LDST__fn_unit \dec_LDST_LDST_LDST__fn_unit + connect \LDST_LDST__imm_data__data \dec_LDST_LDST_LDST__imm_data__data + connect \LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__ok + connect \LDST_LDST__zero_a \dec_LDST_LDST_LDST__zero_a + connect \LDST_LDST__rc__rc \dec_LDST_LDST_LDST__rc__rc + connect \LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__ok + connect \LDST_LDST__oe__oe \dec_LDST_LDST_LDST__oe__oe + connect \LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__ok + connect \LDST_LDST__is_32bit \dec_LDST_LDST_LDST__is_32bit + connect \LDST_LDST__is_signed \dec_LDST_LDST_LDST__is_signed + connect \LDST_LDST__data_len \dec_LDST_LDST_LDST__data_len + connect \LDST_LDST__byte_reverse \dec_LDST_LDST_LDST__byte_reverse + connect \LDST_LDST__sign_extend \dec_LDST_LDST_LDST__sign_extend + connect \LDST_LDST__ldst_mode \dec_LDST_LDST_LDST__ldst_mode + connect \LDST_LDST__insn \dec_LDST_LDST_LDST__insn + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 9 \rdpick_INT_ra_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 9 \rdpick_INT_ra_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_INT_ra_en_o cell \rdpick_INT_ra \rdpick_INT_ra connect \i \rdpick_INT_ra_i connect \o \rdpick_INT_ra_o connect \en_o \rdpick_INT_ra_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \rdpick_INT_rb_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \rdpick_INT_rb_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_INT_rb_en_o cell \rdpick_INT_rb \rdpick_INT_rb connect \i \rdpick_INT_rb_i connect \o \rdpick_INT_rb_o connect \en_o \rdpick_INT_rb_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 \rdpick_INT_rc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 \rdpick_INT_rc_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_INT_rc_en_o cell \rdpick_INT_rc \rdpick_INT_rc connect \i \rdpick_INT_rc_i connect \o \rdpick_INT_rc_o connect \en_o \rdpick_INT_rc_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \rdpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 \rdpick_XER_xer_so_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 \rdpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_XER_xer_so_en_o cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o connect \en_o \rdpick_XER_xer_so_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 3 \rdpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 3 \rdpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_XER_xer_ca_en_o cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o connect \en_o \rdpick_XER_xer_ca_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \rdpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \rdpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_XER_xer_ov_en_o cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o connect \en_o \rdpick_XER_xer_ov_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \rdpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \rdpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_CR_full_cr_en_o cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o connect \en_o \rdpick_CR_full_cr_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 \rdpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 \rdpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_CR_cr_a_en_o cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o connect \en_o \rdpick_CR_cr_a_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \rdpick_CR_cr_b_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \rdpick_CR_cr_b_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_CR_cr_b_en_o cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o connect \en_o \rdpick_CR_cr_b_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \rdpick_CR_cr_c_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \rdpick_CR_cr_c_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_CR_cr_c_en_o cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o connect \en_o \rdpick_CR_cr_c_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 3 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 3 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_FAST_fast1_en_o cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o connect \en_o \rdpick_FAST_fast1_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 \rdpick_FAST_fast2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 \rdpick_FAST_fast2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_FAST_fast2_en_o cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 connect \i \rdpick_FAST_fast2_i connect \o \rdpick_FAST_fast2_o connect \en_o \rdpick_FAST_fast2_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \rdpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \rdpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \rdpick_SPR_spr1_en_o cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o connect \en_o \rdpick_SPR_spr1_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 10 \wrpick_INT_o_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 10 \wrpick_INT_o_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_INT_o_en_o cell \wrpick_INT_o \wrpick_INT_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o connect \en_o \wrpick_INT_o_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \wrpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \wrpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_CR_full_cr_en_o cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o connect \en_o \wrpick_CR_full_cr_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 6 \wrpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 6 \wrpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_CR_cr_a_en_o cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o connect \en_o \wrpick_CR_cr_a_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \wrpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \wrpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 \wrpick_XER_xer_ca_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 \wrpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_XER_xer_ca_en_o cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o connect \en_o \wrpick_XER_xer_ca_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 4 \wrpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 4 \wrpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_XER_xer_ov_en_o cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o connect \en_o \wrpick_XER_xer_ov_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 4 \wrpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 4 \wrpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_XER_xer_so_en_o cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o connect \en_o \wrpick_XER_xer_so_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 5 \wrpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 5 \wrpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_FAST_fast1_en_o cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o connect \en_o \wrpick_FAST_fast1_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 2 \wrpick_STATE_nia_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 2 \wrpick_STATE_nia_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_STATE_nia_en_o cell \wrpick_STATE_nia \wrpick_STATE_nia connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o connect \en_o \wrpick_STATE_nia_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \wrpick_STATE_msr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \wrpick_STATE_msr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_STATE_msr_en_o cell \wrpick_STATE_msr \wrpick_STATE_msr connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o connect \en_o \wrpick_STATE_msr_en_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 1 \wrpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 1 \wrpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire width 1 \wrpick_SPR_spr1_en_o cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o connect \en_o \wrpick_SPR_spr1_en_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + process $group_0 + assign \dec_ALU_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_ALU_raw_opcode_in \raw_insn_i + sync init + end + process $group_1 + assign \dec_ALU_bigendian 1'0 + assign \dec_ALU_bigendian \bigendian_i + sync init + end + process $group_2 + assign \dec_CR_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_CR_raw_opcode_in \raw_insn_i + sync init + end + process $group_3 + assign \dec_CR_bigendian 1'0 + assign \dec_CR_bigendian \bigendian_i + sync init + end + process $group_4 + assign \dec_BRANCH_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_BRANCH_raw_opcode_in \raw_insn_i + sync init + end + process $group_5 + assign \dec_BRANCH_bigendian 1'0 + assign \dec_BRANCH_bigendian \bigendian_i + sync init + end + process $group_6 + assign \dec_LOGICAL_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_LOGICAL_raw_opcode_in \raw_insn_i + sync init + end + process $group_7 + assign \dec_LOGICAL_bigendian 1'0 + assign \dec_LOGICAL_bigendian \bigendian_i + sync init + end + process $group_8 + assign \dec_SPR_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_SPR_raw_opcode_in \raw_insn_i + sync init + end + process $group_9 + assign \dec_SPR_bigendian 1'0 + assign \dec_SPR_bigendian \bigendian_i + sync init + end + process $group_10 + assign \dec_DIV_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_DIV_raw_opcode_in \raw_insn_i + sync init + end + process $group_11 + assign \dec_DIV_bigendian 1'0 + assign \dec_DIV_bigendian \bigendian_i + sync init + end + process $group_12 + assign \dec_MUL_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_MUL_raw_opcode_in \raw_insn_i + sync init + end + process $group_13 + assign \dec_MUL_bigendian 1'0 + assign \dec_MUL_bigendian \bigendian_i + sync init + end + process $group_14 + assign \dec_SHIFT_ROT_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + sync init + end + process $group_15 + assign \dec_SHIFT_ROT_bigendian 1'0 + assign \dec_SHIFT_ROT_bigendian \bigendian_i + sync init + end + process $group_16 + assign \dec_LDST_raw_opcode_in 32'00000000000000000000000000000000 + assign \dec_LDST_raw_opcode_in \raw_insn_i + sync init + end + process $group_17 + assign \dec_LDST_bigendian 1'0 + assign \dec_LDST_bigendian \bigendian_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $162 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 2'10 - connect \Y $160 + connect \Y $161 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $163 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $160 - connect \Y $159 + connect \A $161 + connect \Y $160 end - process $group_0 + process $group_18 assign \en_alu0 1'0 - assign \en_alu0 $159 + assign \en_alu0 $160 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161" wire width 10 \fu_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" wire width 1 \en_ldst0 - process $group_1 + process $group_19 assign \fu_enable 10'0000000000 assign \fu_enable [0] \en_alu0 assign \fu_enable [1] \en_cr0 @@ -102273,266 +210146,266 @@ module \core assign \fu_enable [9] \en_ldst0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $166 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 7'1000000 - connect \Y $164 + connect \Y $165 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $167 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $164 - connect \Y $163 + connect \A $165 + connect \Y $164 end - process $group_2 + process $group_20 assign \en_cr0 1'0 - assign \en_cr0 $163 + assign \en_cr0 $164 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $170 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $168 + connect \Y $169 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $171 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $168 - connect \Y $167 + connect \A $169 + connect \Y $168 end - process $group_3 + process $group_21 assign \en_branch0 1'0 - assign \en_branch0 $167 + assign \en_branch0 $168 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $174 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $172 + connect \Y $173 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $175 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $172 - connect \Y $171 + connect \A $173 + connect \Y $172 end - process $group_4 + process $group_22 assign \en_trap0 1'0 - assign \en_trap0 $171 + assign \en_trap0 $172 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $178 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $176 + connect \Y $177 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $179 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $176 - connect \Y $175 + connect \A $177 + connect \Y $176 end - process $group_5 + process $group_23 assign \en_logical0 1'0 - assign \en_logical0 $175 + assign \en_logical0 $176 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $182 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 11 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $180 + connect \Y $181 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $183 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $180 - connect \Y $179 + connect \A $181 + connect \Y $180 end - process $group_6 + process $group_24 assign \en_spr0 1'0 - assign \en_spr0 $179 + assign \en_spr0 $180 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $186 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $184 + connect \Y $185 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $187 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $184 - connect \Y $183 + connect \A $185 + connect \Y $184 end - process $group_7 + process $group_25 assign \en_div0 1'0 - assign \en_div0 $183 + assign \en_div0 $184 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $190 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 9 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $188 + connect \Y $189 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $191 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $188 - connect \Y $187 + connect \A $189 + connect \Y $188 end - process $group_8 + process $group_26 assign \en_mul0 1'0 - assign \en_mul0 $187 + assign \en_mul0 $188 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $194 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $192 + connect \Y $193 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $195 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $192 - connect \Y $191 + connect \A $193 + connect \Y $192 end - process $group_9 + process $group_27 assign \en_shiftrot0 1'0 - assign \en_shiftrot0 $191 + assign \en_shiftrot0 $192 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 1 $195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - wire width 11 $196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $and $197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 1 $196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + wire width 11 $197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $and $198 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 11 - connect \A \fn_unit + connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $196 + connect \Y $197 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" - cell $reduce_bool $198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" + cell $reduce_bool $199 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $196 - connect \Y $195 + connect \A $197 + connect \Y $196 end - process $group_10 + process $group_28 assign \en_ldst0 1'0 - assign \en_ldst0 $195 + assign \en_ldst0 $196 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:176" wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:176" wire width 2 \counter$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" - wire width 1 $199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" - cell $ne $200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + wire width 1 $200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + cell $ne $201 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -102540,14 +210413,14 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $199 + connect \Y $200 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144" - wire width 3 $201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire width 3 $202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144" - cell $sub $203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + wire width 3 $203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" + cell $sub $204 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -102555,31 +210428,31 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $202 + connect \Y $203 end - connect $201 $202 - process $group_11 + connect $202 $203 + process $group_29 assign \counter$next \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" - switch { $199 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + switch { $200 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" case 1'1 - assign \counter$next $201 [1:0] + assign \counter$next $202 [1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 assign \counter$next 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case end @@ -102594,10 +210467,10 @@ module \core sync posedge \coresync_clk update \counter \counter$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" - wire width 1 $204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" - cell $ne $205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + wire width 1 $205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + cell $ne $206 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -102605,112 +210478,112 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $204 + connect \Y $205 end - process $group_12 + process $group_30 assign \corebusy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" - switch { $204 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + switch { $205 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" case 1'1 assign \corebusy_o 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 assign \corebusy_o 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 assign \corebusy_o \fus_cu_busy_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$4 + assign \corebusy_o \fus_cu_busy_o$5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$7 + assign \corebusy_o \fus_cu_busy_o$8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$10 + assign \corebusy_o \fus_cu_busy_o$11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$13 + assign \corebusy_o \fus_cu_busy_o$14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$16 + assign \corebusy_o \fus_cu_busy_o$17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$19 + assign \corebusy_o \fus_cu_busy_o$20 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$22 + assign \corebusy_o \fus_cu_busy_o$23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$25 + assign \corebusy_o \fus_cu_busy_o$26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \corebusy_o \fus_cu_busy_o$28 + assign \corebusy_o \fus_cu_busy_o$29 end end end sync init end - process $group_13 + process $group_31 assign \core_terminate_o$next \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 assign \core_terminate_o$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case end @@ -102725,434 +210598,434 @@ module \core sync posedge \coresync_clk update \core_terminate_o \core_terminate_o$next end - process $group_14 + process $group_32 assign \fus_oper_i_alu_alu0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__insn_type \insn_type + assign \fus_oper_i_alu_alu0__insn_type \dec_ALU_ALU_ALU__insn_type end end end sync init end - process $group_15 + process $group_33 assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__fn_unit \fn_unit + assign \fus_oper_i_alu_alu0__fn_unit \dec_ALU_ALU_ALU__fn_unit end end end sync init end - process $group_16 - assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_34 + assign \fus_oper_i_alu_alu0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_alu0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \imm_ok \imm } + assign { \fus_oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__data } { \dec_ALU_ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__data } end end end sync init end - process $group_18 + process $group_36 assign \fus_oper_i_alu_alu0__rc__rc 1'0 - assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_alu0__rc__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \rc_ok \rc } + assign { \fus_oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__rc } { \dec_ALU_ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__rc } end end end sync init end - process $group_20 + process $group_38 assign \fus_oper_i_alu_alu0__oe__oe 1'0 - assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_alu0__oe__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \oe_ok \oe } + assign { \fus_oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__oe } { \dec_ALU_ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__oe } end end end sync init end - process $group_22 + process $group_40 assign \fus_oper_i_alu_alu0__invert_in 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__invert_in \invert_in + assign \fus_oper_i_alu_alu0__invert_in \dec_ALU_ALU_ALU__invert_in end end end sync init end - process $group_23 + process $group_41 assign \fus_oper_i_alu_alu0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__zero_a \zero_a + assign \fus_oper_i_alu_alu0__zero_a \dec_ALU_ALU_ALU__zero_a end end end sync init end - process $group_24 + process $group_42 assign \fus_oper_i_alu_alu0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__invert_out \invert_out + assign \fus_oper_i_alu_alu0__invert_out \dec_ALU_ALU_ALU__invert_out end end end sync init end - process $group_25 + process $group_43 assign \fus_oper_i_alu_alu0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__write_cr0 \write_cr0 + assign \fus_oper_i_alu_alu0__write_cr0 \dec_ALU_ALU_ALU__write_cr0 end end end sync init end - process $group_26 + process $group_44 assign \fus_oper_i_alu_alu0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__input_carry \input_carry + assign \fus_oper_i_alu_alu0__input_carry \dec_ALU_ALU_ALU__input_carry end end end sync init end - process $group_27 + process $group_45 assign \fus_oper_i_alu_alu0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__output_carry \output_carry + assign \fus_oper_i_alu_alu0__output_carry \dec_ALU_ALU_ALU__output_carry end end end sync init end - process $group_28 + process $group_46 assign \fus_oper_i_alu_alu0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__is_32bit \is_32bit + assign \fus_oper_i_alu_alu0__is_32bit \dec_ALU_ALU_ALU__is_32bit end end end sync init end - process $group_29 + process $group_47 assign \fus_oper_i_alu_alu0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__is_signed \is_signed + assign \fus_oper_i_alu_alu0__is_signed \dec_ALU_ALU_ALU__is_signed end end end sync init end - process $group_30 + process $group_48 assign \fus_oper_i_alu_alu0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__data_len \data_len + assign \fus_oper_i_alu_alu0__data_len \dec_ALU_ALU_ALU__data_len end end end sync init end - process $group_31 + process $group_49 assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_alu0__insn \insn + assign \fus_oper_i_alu_alu0__insn \dec_ALU_ALU_ALU__insn end end end sync init end - process $group_32 + process $group_50 assign \fus_cu_issue_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 assign \fus_cu_issue_i \issue_i end @@ -103160,3205 +211033,3673 @@ module \core end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 4 $206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 4 $207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $207 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $208 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $210 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $210 + connect \B 1'1 + connect \Y $212 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $207 - connect \B \xer_in - connect \Y $209 + connect \A $208 + connect \B $212 + connect \Y $214 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $216 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $214 + connect \B $216 + connect \Y $218 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire width 1 $220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $221 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \input_carry + connect \A \core_core_input_carry connect \B 2'10 - connect \Y $211 + connect \Y $220 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 $222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $222 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $222 + connect \B 3'100 + connect \Y $224 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $211 - connect \B \xer_in - connect \Y $213 + connect \A $220 + connect \B $224 + connect \Y $226 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $228 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A { $213 $209 \reg2_ok \reg1_ok } - connect \Y $206 + connect \A { $226 $218 \core_reg2_ok \core_reg1_ok } + connect \Y $207 end - process $group_33 + process $group_51 assign \fus_cu_rdmaskn_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i $206 + assign \fus_cu_rdmaskn_i $207 end end end sync init end - process $group_34 + process $group_52 assign \fus_oper_i_alu_cr0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_cr0__insn_type \insn_type + assign \fus_oper_i_alu_cr0__insn_type \dec_CR_CR_CR__insn_type end end end sync init end - process $group_35 + process $group_53 assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_cr0__fn_unit \fn_unit + assign \fus_oper_i_alu_cr0__fn_unit \dec_CR_CR_CR__fn_unit end end end sync init end - process $group_36 + process $group_54 assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" - case 1'1 - assign \fus_oper_i_alu_cr0__insn \insn - end - end - end - sync init - end - process $group_37 - assign \fus_oper_i_alu_cr0__read_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_cr0__read_cr_whole \read_cr_whole + assign \fus_oper_i_alu_cr0__insn \dec_CR_CR_CR__insn end end end sync init end - process $group_38 - assign \fus_oper_i_alu_cr0__write_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" - case 1'1 - assign \fus_oper_i_alu_cr0__write_cr_whole \write_cr_whole - end - end - end - sync init - end - process $group_39 - assign \fus_cu_issue_i$3 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_55 + assign \fus_cu_issue_i$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$3 \issue_i + assign \fus_cu_issue_i$4 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 6 $216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 6 $229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $230 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 - connect \A { \cr_in2_ok$2 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok } - connect \Y $216 + connect \A { \core_cr_in2_ok$2 \core_cr_in2_ok \core_cr_in1_ok \core_core_cr_rd_ok \core_reg2_ok \core_reg1_ok } + connect \Y $229 end - process $group_40 - assign \fus_cu_rdmaskn_i$5 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_56 + assign \fus_cu_rdmaskn_i$6 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$5 $216 + assign \fus_cu_rdmaskn_i$6 $229 end end end sync init end - process $group_41 + process $group_57 assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_branch0__cia \cia + assign \fus_oper_i_alu_branch0__cia \dec_BRANCH_BRANCH_BRANCH__cia end end end sync init end - process $group_42 + process $group_58 assign \fus_oper_i_alu_branch0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_branch0__insn_type \insn_type + assign \fus_oper_i_alu_branch0__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type end end end sync init end - process $group_43 + process $group_59 assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_branch0__fn_unit \fn_unit + assign \fus_oper_i_alu_branch0__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit end end end sync init end - process $group_44 + process $group_60 assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_branch0__insn \insn + assign \fus_oper_i_alu_branch0__insn \dec_BRANCH_BRANCH_BRANCH__insn end end end sync init end - process $group_45 - assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_61 + assign \fus_oper_i_alu_branch0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_branch0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \imm_ok \imm } + assign { \fus_oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__data } { \dec_BRANCH_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__data } end end end sync init end - process $group_47 + process $group_63 assign \fus_oper_i_alu_branch0__lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_branch0__lk \lk + assign \fus_oper_i_alu_branch0__lk \dec_BRANCH_BRANCH_BRANCH__lk end end end sync init end - process $group_48 + process $group_64 assign \fus_oper_i_alu_branch0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_branch0__is_32bit \is_32bit + assign \fus_oper_i_alu_branch0__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit end end end sync init end - process $group_49 - assign \fus_cu_issue_i$6 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_65 + assign \fus_cu_issue_i$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$6 \issue_i + assign \fus_cu_issue_i$7 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 3 $218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 3 $231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $232 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A { \cr_in1_ok \fast2_ok \fast1_ok } - connect \Y $218 + connect \A { \core_cr_in1_ok \core_fast2_ok \core_fast1_ok } + connect \Y $231 end - process $group_50 - assign \fus_cu_rdmaskn_i$8 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_66 + assign \fus_cu_rdmaskn_i$9 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$8 $218 + assign \fus_cu_rdmaskn_i$9 $231 end end end sync init end - process $group_51 + process $group_67 assign \fus_oper_i_alu_trap0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__insn_type \insn_type + assign \fus_oper_i_alu_trap0__insn_type \core_core_insn_type end end end sync init end - process $group_52 + process $group_68 assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__fn_unit \fn_unit + assign \fus_oper_i_alu_trap0__fn_unit \core_core_fn_unit end end end sync init end - process $group_53 + process $group_69 assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__insn \insn + assign \fus_oper_i_alu_trap0__insn \core_core_insn end end end sync init end - process $group_54 + process $group_70 assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__msr \msr + assign \fus_oper_i_alu_trap0__msr \core_core_msr end end end sync init end - process $group_55 + process $group_71 assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__cia \cia + assign \fus_oper_i_alu_trap0__cia \core_core_cia end end end sync init end - process $group_56 + process $group_72 assign \fus_oper_i_alu_trap0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__is_32bit \is_32bit + assign \fus_oper_i_alu_trap0__is_32bit \core_core_is_32bit end end end sync init end - process $group_57 - assign \fus_oper_i_alu_trap0__traptype 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_73 + assign \fus_oper_i_alu_trap0__traptype 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__traptype \traptype + assign \fus_oper_i_alu_trap0__traptype \core_core_traptype end end end sync init end - process $group_58 + process $group_74 assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_trap0__trapaddr \trapaddr + assign \fus_oper_i_alu_trap0__trapaddr \core_core_trapaddr end end end sync init end - process $group_59 - assign \fus_cu_issue_i$9 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_75 + assign \fus_cu_issue_i$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$9 \issue_i + assign \fus_cu_issue_i$10 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 4 $220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 4 $233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $234 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A { \fast2_ok \fast1_ok \reg2_ok \reg1_ok } - connect \Y $220 + connect \A { \core_fast2_ok \core_fast1_ok \core_reg2_ok \core_reg1_ok } + connect \Y $233 end - process $group_60 - assign \fus_cu_rdmaskn_i$11 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_76 + assign \fus_cu_rdmaskn_i$12 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$11 $220 + assign \fus_cu_rdmaskn_i$12 $233 end end end sync init end - process $group_61 + process $group_77 assign \fus_oper_i_alu_logical0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__insn_type \insn_type + assign \fus_oper_i_alu_logical0__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type end end end sync init end - process $group_62 + process $group_78 assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__fn_unit \fn_unit + assign \fus_oper_i_alu_logical0__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit end end end sync init end - process $group_63 - assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_79 + assign \fus_oper_i_alu_logical0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_logical0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \imm_ok \imm } + assign { \fus_oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__data } { \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data } end end end sync init end - process $group_65 + process $group_81 assign \fus_oper_i_alu_logical0__rc__rc 1'0 - assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_logical0__rc__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \rc_ok \rc } + assign { \fus_oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__rc } { \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc } end end end sync init end - process $group_67 + process $group_83 assign \fus_oper_i_alu_logical0__oe__oe 1'0 - assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_logical0__oe__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \oe_ok \oe } + assign { \fus_oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__oe } { \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe } end end end sync init end - process $group_69 + process $group_85 assign \fus_oper_i_alu_logical0__invert_in 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__invert_in \invert_in + assign \fus_oper_i_alu_logical0__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in end end end sync init end - process $group_70 + process $group_86 assign \fus_oper_i_alu_logical0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__zero_a \zero_a + assign \fus_oper_i_alu_logical0__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a end end end sync init end - process $group_71 + process $group_87 assign \fus_oper_i_alu_logical0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__input_carry \input_carry + assign \fus_oper_i_alu_logical0__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry end end end sync init end - process $group_72 + process $group_88 assign \fus_oper_i_alu_logical0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__invert_out \invert_out + assign \fus_oper_i_alu_logical0__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out end end end sync init end - process $group_73 + process $group_89 assign \fus_oper_i_alu_logical0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__write_cr0 \write_cr0 + assign \fus_oper_i_alu_logical0__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 end end end sync init end - process $group_74 + process $group_90 assign \fus_oper_i_alu_logical0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__output_carry \output_carry + assign \fus_oper_i_alu_logical0__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry end end end sync init end - process $group_75 + process $group_91 assign \fus_oper_i_alu_logical0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__is_32bit \is_32bit + assign \fus_oper_i_alu_logical0__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit end end end sync init end - process $group_76 + process $group_92 assign \fus_oper_i_alu_logical0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__is_signed \is_signed + assign \fus_oper_i_alu_logical0__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed end end end sync init end - process $group_77 + process $group_93 assign \fus_oper_i_alu_logical0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__data_len \data_len + assign \fus_oper_i_alu_logical0__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len end end end sync init end - process $group_78 + process $group_94 assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_logical0__insn \insn + assign \fus_oper_i_alu_logical0__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn end end end sync init end - process $group_79 - assign \fus_cu_issue_i$12 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_95 + assign \fus_cu_issue_i$13 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$12 \issue_i + assign \fus_cu_issue_i$13 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 2 $222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 3 $235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $237 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \reg2_ok \reg1_ok } - connect \Y $222 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $236 end - process $group_80 - assign \fus_cu_rdmaskn_i$14 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $238 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $238 + connect \B 1'1 + connect \Y $240 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $236 + connect \B $240 + connect \Y $242 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $244 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $242 + connect \B $244 + connect \Y $246 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { $246 \core_reg2_ok \core_reg1_ok } + connect \Y $235 + end + process $group_96 + assign \fus_cu_rdmaskn_i$15 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$14 $222 + assign \fus_cu_rdmaskn_i$15 $235 end end end sync init end - process $group_81 + process $group_97 assign \fus_oper_i_alu_spr0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_spr0__insn_type \insn_type + assign \fus_oper_i_alu_spr0__insn_type \dec_SPR_SPR_SPR__insn_type end end end sync init end - process $group_82 + process $group_98 assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_spr0__fn_unit \fn_unit + assign \fus_oper_i_alu_spr0__fn_unit \dec_SPR_SPR_SPR__fn_unit end end end sync init end - process $group_83 + process $group_99 assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_spr0__insn \insn + assign \fus_oper_i_alu_spr0__insn \dec_SPR_SPR_SPR__insn end end end sync init end - process $group_84 + process $group_100 assign \fus_oper_i_alu_spr0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_spr0__is_32bit \is_32bit + assign \fus_oper_i_alu_spr0__is_32bit \dec_SPR_SPR_SPR__is_32bit end end end sync init end - process $group_85 - assign \fus_cu_issue_i$15 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_101 + assign \fus_cu_issue_i$16 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$15 \issue_i + assign \fus_cu_issue_i$16 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 6 $224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 6 $249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $225 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $250 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $252 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $252 + connect \B 1'1 + connect \Y $254 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $225 - connect \B \xer_in - connect \Y $227 + connect \A $250 + connect \B $254 + connect \Y $256 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $229 + wire width 1 $258 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $230 + cell $and $259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $229 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $258 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $231 + wire width 1 $260 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $232 + cell $or $261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $229 - connect \B \xer_in - connect \Y $231 + connect \A $256 + connect \B $258 + connect \Y $260 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $233 + wire width 1 $262 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $234 + cell $and $263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $262 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 3 $264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $and $265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 2'10 + connect \Y $264 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 1 $266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $eq $267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A $264 + connect \B 2'10 + connect \Y $266 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 1 $268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $or $269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $262 + connect \B $266 + connect \Y $268 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire width 1 $270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $271 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \input_carry + connect \A \core_core_input_carry connect \B 2'10 - connect \Y $233 + connect \Y $270 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 $272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $272 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $272 + connect \B 3'100 + connect \Y $274 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $233 - connect \B \xer_in - connect \Y $235 + connect \A $270 + connect \B $274 + connect \Y $276 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $278 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 - connect \A { $235 $231 $227 \fast1_ok \spr1_ok \reg1_ok } - connect \Y $224 + connect \A { $276 $268 $260 \core_fast1_ok \core_spr1_ok \core_reg1_ok } + connect \Y $249 end - process $group_86 - assign \fus_cu_rdmaskn_i$17 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_102 + assign \fus_cu_rdmaskn_i$18 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$17 $224 + assign \fus_cu_rdmaskn_i$18 $249 end end end sync init end - process $group_87 + process $group_103 assign \fus_oper_i_alu_div0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__insn_type \insn_type + assign \fus_oper_i_alu_div0__insn_type \dec_DIV_DIV_DIV__insn_type end end end sync init end - process $group_88 + process $group_104 assign \fus_oper_i_alu_div0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__fn_unit \fn_unit + assign \fus_oper_i_alu_div0__fn_unit \dec_DIV_DIV_DIV__fn_unit end end end sync init end - process $group_89 - assign \fus_oper_i_alu_div0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_div0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_105 + assign \fus_oper_i_alu_div0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_div0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm } { \imm_ok \imm } + assign { \fus_oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__data } { \dec_DIV_DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__data } end end end sync init end - process $group_91 + process $group_107 assign \fus_oper_i_alu_div0__rc__rc 1'0 - assign \fus_oper_i_alu_div0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_div0__rc__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc } { \rc_ok \rc } + assign { \fus_oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__rc } { \dec_DIV_DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__rc } end end end sync init end - process $group_93 + process $group_109 assign \fus_oper_i_alu_div0__oe__oe 1'0 - assign \fus_oper_i_alu_div0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_div0__oe__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe } { \oe_ok \oe } + assign { \fus_oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__oe } { \dec_DIV_DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__oe } end end end sync init end - process $group_95 + process $group_111 assign \fus_oper_i_alu_div0__invert_in 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__invert_in \invert_in + assign \fus_oper_i_alu_div0__invert_in \dec_DIV_DIV_DIV__invert_in end end end sync init end - process $group_96 + process $group_112 assign \fus_oper_i_alu_div0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__zero_a \zero_a + assign \fus_oper_i_alu_div0__zero_a \dec_DIV_DIV_DIV__zero_a end end end sync init end - process $group_97 + process $group_113 assign \fus_oper_i_alu_div0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__input_carry \input_carry + assign \fus_oper_i_alu_div0__input_carry \dec_DIV_DIV_DIV__input_carry end end end sync init end - process $group_98 + process $group_114 assign \fus_oper_i_alu_div0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__invert_out \invert_out + assign \fus_oper_i_alu_div0__invert_out \dec_DIV_DIV_DIV__invert_out end end end sync init end - process $group_99 + process $group_115 assign \fus_oper_i_alu_div0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__write_cr0 \write_cr0 + assign \fus_oper_i_alu_div0__write_cr0 \dec_DIV_DIV_DIV__write_cr0 end end end sync init end - process $group_100 + process $group_116 assign \fus_oper_i_alu_div0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__output_carry \output_carry + assign \fus_oper_i_alu_div0__output_carry \dec_DIV_DIV_DIV__output_carry end end end sync init end - process $group_101 + process $group_117 assign \fus_oper_i_alu_div0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__is_32bit \is_32bit + assign \fus_oper_i_alu_div0__is_32bit \dec_DIV_DIV_DIV__is_32bit end end end sync init end - process $group_102 + process $group_118 assign \fus_oper_i_alu_div0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__is_signed \is_signed + assign \fus_oper_i_alu_div0__is_signed \dec_DIV_DIV_DIV__is_signed end end end sync init end - process $group_103 + process $group_119 assign \fus_oper_i_alu_div0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__data_len \data_len + assign \fus_oper_i_alu_div0__data_len \dec_DIV_DIV_DIV__data_len end end end sync init end - process $group_104 + process $group_120 assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_div0__insn \insn + assign \fus_oper_i_alu_div0__insn \dec_DIV_DIV_DIV__insn end end end sync init end - process $group_105 - assign \fus_cu_issue_i$18 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_121 + assign \fus_cu_issue_i$19 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$18 \issue_i + assign \fus_cu_issue_i$19 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 3 $238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $239 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 3 $279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $280 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $282 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $282 + connect \B 1'1 + connect \Y $284 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $280 + connect \B $284 + connect \Y $286 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $239 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $288 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $241 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $239 - connect \B \xer_in - connect \Y $241 + connect \A $286 + connect \B $288 + connect \Y $290 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $292 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A { $241 \reg2_ok \reg1_ok } - connect \Y $238 + connect \A { $290 \core_reg2_ok \core_reg1_ok } + connect \Y $279 end - process $group_106 - assign \fus_cu_rdmaskn_i$20 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_122 + assign \fus_cu_rdmaskn_i$21 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$20 $238 + assign \fus_cu_rdmaskn_i$21 $279 end end end sync init end - process $group_107 + process $group_123 assign \fus_oper_i_alu_mul0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_mul0__insn_type \insn_type + assign \fus_oper_i_alu_mul0__insn_type \dec_MUL_MUL_MUL__insn_type end end end sync init end - process $group_108 + process $group_124 assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_mul0__fn_unit \fn_unit + assign \fus_oper_i_alu_mul0__fn_unit \dec_MUL_MUL_MUL__fn_unit end end end sync init end - process $group_109 - assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_125 + assign \fus_oper_i_alu_mul0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_mul0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \imm_ok \imm } + assign { \fus_oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__data } { \dec_MUL_MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__data } end end end sync init end - process $group_111 + process $group_127 assign \fus_oper_i_alu_mul0__rc__rc 1'0 - assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_mul0__rc__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \rc_ok \rc } + assign { \fus_oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__rc } { \dec_MUL_MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__rc } end end end sync init end - process $group_113 + process $group_129 assign \fus_oper_i_alu_mul0__oe__oe 1'0 - assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_mul0__oe__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \oe_ok \oe } + assign { \fus_oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__oe } { \dec_MUL_MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__oe } end end end sync init end - process $group_115 + process $group_131 assign \fus_oper_i_alu_mul0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_mul0__write_cr0 \write_cr0 + assign \fus_oper_i_alu_mul0__write_cr0 \dec_MUL_MUL_MUL__write_cr0 end end end sync init end - process $group_116 + process $group_132 assign \fus_oper_i_alu_mul0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_mul0__is_32bit \is_32bit + assign \fus_oper_i_alu_mul0__is_32bit \dec_MUL_MUL_MUL__is_32bit end end end sync init end - process $group_117 + process $group_133 assign \fus_oper_i_alu_mul0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_mul0__is_signed \is_signed + assign \fus_oper_i_alu_mul0__is_signed \dec_MUL_MUL_MUL__is_signed end end end sync init end - process $group_118 + process $group_134 assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_mul0__insn \insn + assign \fus_oper_i_alu_mul0__insn \dec_MUL_MUL_MUL__insn end end end sync init end - process $group_119 - assign \fus_cu_issue_i$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_135 + assign \fus_cu_issue_i$22 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$21 \issue_i + assign \fus_cu_issue_i$22 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 3 $244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 3 $293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $294 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $296 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $296 + connect \B 1'1 + connect \Y $298 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $294 + connect \B $298 + connect \Y $300 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $245 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $302 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $245 - connect \B \xer_in - connect \Y $247 + connect \A $300 + connect \B $302 + connect \Y $304 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $306 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A { $247 \reg2_ok \reg1_ok } - connect \Y $244 + connect \A { $304 \core_reg2_ok \core_reg1_ok } + connect \Y $293 end - process $group_120 - assign \fus_cu_rdmaskn_i$23 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_136 + assign \fus_cu_rdmaskn_i$24 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$23 $244 + assign \fus_cu_rdmaskn_i$24 $293 end end end sync init end - process $group_121 + process $group_137 assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type + assign \fus_oper_i_alu_shift_rot0__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type end end end sync init end - process $group_122 + process $group_138 assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__fn_unit \fn_unit + assign \fus_oper_i_alu_shift_rot0__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit end end end sync init end - process $group_123 - assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_139 + assign \fus_oper_i_alu_shift_rot0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_shift_rot0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \imm_ok \imm } + assign { \fus_oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__data } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data } end end end sync init end - process $group_125 + process $group_141 assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0 - assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_shift_rot0__rc__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \rc_ok \rc } + assign { \fus_oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__rc } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc } end end end sync init end - process $group_127 + process $group_143 assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0 - assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_alu_shift_rot0__oe__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \oe_ok \oe } + assign { \fus_oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__oe } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe } end end end sync init end - process $group_129 - assign { } 0'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_145 + assign \fus_oper_i_alu_shift_rot0__write_cr0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { } {} + assign \fus_oper_i_alu_shift_rot0__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 end end end sync init end - process $group_130 + process $group_146 assign \fus_oper_i_alu_shift_rot0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__input_carry \input_carry + assign \fus_oper_i_alu_shift_rot0__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry end end end sync init end - process $group_131 + process $group_147 assign \fus_oper_i_alu_shift_rot0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__output_carry \output_carry + assign \fus_oper_i_alu_shift_rot0__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry end end end sync init end - process $group_132 + process $group_148 assign \fus_oper_i_alu_shift_rot0__input_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__input_cr \input_cr + assign \fus_oper_i_alu_shift_rot0__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr end end end sync init end - process $group_133 + process $group_149 assign \fus_oper_i_alu_shift_rot0__output_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__output_cr \output_cr + assign \fus_oper_i_alu_shift_rot0__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr end end end sync init end - process $group_134 + process $group_150 assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__is_32bit \is_32bit + assign \fus_oper_i_alu_shift_rot0__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit end end end sync init end - process $group_135 + process $group_151 assign \fus_oper_i_alu_shift_rot0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__is_signed \is_signed + assign \fus_oper_i_alu_shift_rot0__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed end end end sync init end - process $group_136 + process $group_152 assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_alu_shift_rot0__insn \insn + assign \fus_oper_i_alu_shift_rot0__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn end end end sync init end - process $group_137 - assign \fus_cu_issue_i$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_153 + assign \fus_cu_issue_i$25 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$24 \issue_i + assign \fus_cu_issue_i$25 \issue_i end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 4 $250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 5 $307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $308 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $310 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $310 + connect \B 1'1 + connect \Y $312 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $308 + connect \B $312 + connect \Y $314 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $316 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $314 + connect \B $316 + connect \Y $318 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire width 1 $320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $321 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \input_carry + connect \A \core_core_input_carry connect \B 2'10 - connect \Y $251 + connect \Y $320 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 $322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $322 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $322 + connect \B 3'100 + connect \Y $324 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $251 - connect \B \xer_in - connect \Y $253 + connect \A $320 + connect \B $324 + connect \Y $326 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $328 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { $253 \reg3_ok \reg2_ok \reg1_ok } - connect \Y $250 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { $326 $318 \core_reg3_ok \core_reg2_ok \core_reg1_ok } + connect \Y $307 end - process $group_138 - assign \fus_cu_rdmaskn_i$26 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_154 + assign \fus_cu_rdmaskn_i$27 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$26 $250 + assign \fus_cu_rdmaskn_i$27 $307 end end end sync init end - process $group_139 + process $group_155 assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__insn_type \insn_type + assign \fus_oper_i_ldst_ldst0__insn_type \dec_LDST_LDST_LDST__insn_type end end end sync init end - process $group_140 - assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_156 + assign \fus_oper_i_ldst_ldst0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \imm_ok \imm } + assign \fus_oper_i_ldst_ldst0__fn_unit \dec_LDST_LDST_LDST__fn_unit end end end sync init end - process $group_142 + process $group_157 + assign \fus_oper_i_ldst_ldst0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_ldst_ldst0__imm_data__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + case 1'1 + assign { \fus_oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__data } { \dec_LDST_LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__data } + end + end + end + sync init + end + process $group_159 assign \fus_oper_i_ldst_ldst0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__zero_a \zero_a + assign \fus_oper_i_ldst_ldst0__zero_a \dec_LDST_LDST_LDST__zero_a end end end sync init end - process $group_143 + process $group_160 assign \fus_oper_i_ldst_ldst0__rc__rc 1'0 - assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_ldst_ldst0__rc__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \rc_ok \rc } + assign { \fus_oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__rc } { \dec_LDST_LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__rc } end end end sync init end - process $group_145 + process $group_162 assign \fus_oper_i_ldst_ldst0__oe__oe 1'0 - assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + assign \fus_oper_i_ldst_ldst0__oe__ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \oe_ok \oe } + assign { \fus_oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__oe } { \dec_LDST_LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__oe } end end end sync init end - process $group_147 + process $group_164 assign \fus_oper_i_ldst_ldst0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__is_32bit \is_32bit + assign \fus_oper_i_ldst_ldst0__is_32bit \dec_LDST_LDST_LDST__is_32bit end end end sync init end - process $group_148 + process $group_165 assign \fus_oper_i_ldst_ldst0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__is_signed \is_signed + assign \fus_oper_i_ldst_ldst0__is_signed \dec_LDST_LDST_LDST__is_signed end end end sync init end - process $group_149 + process $group_166 assign \fus_oper_i_ldst_ldst0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__data_len \data_len + assign \fus_oper_i_ldst_ldst0__data_len \dec_LDST_LDST_LDST__data_len end end end sync init end - process $group_150 + process $group_167 assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__byte_reverse \byte_reverse + assign \fus_oper_i_ldst_ldst0__byte_reverse \dec_LDST_LDST_LDST__byte_reverse end end end sync init end - process $group_151 + process $group_168 assign \fus_oper_i_ldst_ldst0__sign_extend 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__sign_extend \sign_extend + assign \fus_oper_i_ldst_ldst0__sign_extend \dec_LDST_LDST_LDST__sign_extend end end end sync init end - process $group_152 + process $group_169 assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_oper_i_ldst_ldst0__ldst_mode \ldst_mode + assign \fus_oper_i_ldst_ldst0__ldst_mode \dec_LDST_LDST_LDST__ldst_mode end end end sync init end - process $group_153 - assign \fus_cu_issue_i$27 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_170 + assign \fus_oper_i_ldst_ldst0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_issue_i$27 \issue_i + assign \fus_oper_i_ldst_ldst0__insn \dec_LDST_LDST_LDST__insn end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - wire width 3 $256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" - cell $not $257 + process $group_171 + assign \fus_cu_issue_i$28 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + case 1'1 + assign \fus_cu_issue_i$28 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + wire width 3 $329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + cell $not $330 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A { \reg3_ok \reg2_ok \reg1_ok } - connect \Y $256 + connect \A { \core_reg3_ok \core_reg2_ok \core_reg1_ok } + connect \Y $329 end - process $group_154 - assign \fus_cu_rdmaskn_i$29 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + process $group_172 + assign \fus_cu_rdmaskn_i$30 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" attribute \nmigen.decoding "OP_ATTN/5" case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" attribute \nmigen.decoding "OP_NOP/1" case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" attribute \nmigen.decoding "" case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" case 1'1 - assign \fus_cu_rdmaskn_i$29 $256 + assign \fus_cu_rdmaskn_i$30 $329 end end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_INT_ra_0 - process $group_155 + process $group_173 assign \rdflag_INT_ra_0 1'0 - assign \rdflag_INT_ra_0 \reg1_ok + assign \rdflag_INT_ra_0 \core_reg1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106366,70 +214707,70 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $258 + connect \Y $331 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $258 + connect \A $331 connect \B \rdflag_INT_ra_0 - connect \Y $260 + connect \Y $333 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_alu0_0 - connect \Y $262 + connect \Y $335 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $260 - connect \B $262 - connect \Y $264 + connect \A $333 + connect \B $335 + connect \Y $337 end - process $group_156 + process $group_174 assign \pick_INT_ra_alu0_0 1'0 - assign \pick_INT_ra_alu0_0 $264 + assign \pick_INT_ra_alu0_0 $337 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_ra_ldst0_8 - process $group_157 + process $group_175 assign \rdpick_INT_ra_i 9'000000000 assign \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 assign \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 @@ -106442,19 +214783,19 @@ module \core assign \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ca_alu0_0$next - process $group_158 + process $group_176 assign \fus_cu_rd__go_i 4'0000 assign \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 assign \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 @@ -106462,12 +214803,12 @@ module \core assign \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106475,14 +214816,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $266 + connect \Y $339 end - process $group_159 + process $group_177 assign \rp_INT_ra_alu0_0 1'0 - assign \rp_INT_ra_alu0_0 $266 + assign \rp_INT_ra_alu0_0 $339 sync init end - process $group_160 + process $group_178 assign \dp_INT_ra_alu0_0$next \dp_INT_ra_alu0_0 assign \dp_INT_ra_alu0_0$next \rp_INT_ra_alu0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -106495,127 +214836,127 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_alu0_0 \dp_INT_ra_alu0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $342 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_alu0_0 - connect \Y $268 + connect \Y $341 end - process $group_161 + process $group_179 assign \addr_en_INT_ra_alu0_0 5'00000 - assign \addr_en_INT_ra_alu0_0 $268 + assign \addr_en_INT_ra_alu0_0 $341 sync init end - process $group_162 + process $group_180 assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 assign \fus_src1_i \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [0] + connect \A \fus_cu_rd__rel_o$31 [0] connect \B \fu_enable [1] - connect \Y $270 + connect \Y $343 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $270 + connect \A $343 connect \B \rdflag_INT_ra_0 - connect \Y $272 + connect \Y $345 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_cr0_1 - connect \Y $274 + connect \Y $347 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $272 - connect \B $274 - connect \Y $276 + connect \A $345 + connect \B $347 + connect \Y $349 end - process $group_163 + process $group_181 assign \pick_INT_ra_cr0_1 1'0 - assign \pick_INT_ra_cr0_1 $276 + assign \pick_INT_ra_cr0_1 $349 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_c_cr0_0$next - process $group_164 - assign \fus_cu_rd__go_i$31 6'000000 - assign \fus_cu_rd__go_i$31 [0] \dp_INT_ra_cr0_1 - assign \fus_cu_rd__go_i$31 [1] \dp_INT_rb_cr0_1 - assign \fus_cu_rd__go_i$31 [2] \dp_CR_full_cr_cr0_0 - assign \fus_cu_rd__go_i$31 [3] \dp_CR_cr_a_cr0_0 - assign \fus_cu_rd__go_i$31 [4] \dp_CR_cr_b_cr0_0 - assign \fus_cu_rd__go_i$31 [5] \dp_CR_cr_c_cr0_0 + process $group_182 + assign \fus_cu_rd__go_i$32 6'000000 + assign \fus_cu_rd__go_i$32 [0] \dp_INT_ra_cr0_1 + assign \fus_cu_rd__go_i$32 [1] \dp_INT_rb_cr0_1 + assign \fus_cu_rd__go_i$32 [2] \dp_CR_full_cr_cr0_0 + assign \fus_cu_rd__go_i$32 [3] \dp_CR_cr_a_cr0_0 + assign \fus_cu_rd__go_i$32 [4] \dp_CR_cr_b_cr0_0 + assign \fus_cu_rd__go_i$32 [5] \dp_CR_cr_c_cr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106623,14 +214964,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $278 + connect \Y $351 end - process $group_165 + process $group_183 assign \rp_INT_ra_cr0_1 1'0 - assign \rp_INT_ra_cr0_1 $278 + assign \rp_INT_ra_cr0_1 $351 sync init end - process $group_166 + process $group_184 assign \dp_INT_ra_cr0_1$next \dp_INT_ra_cr0_1 assign \dp_INT_ra_cr0_1$next \rp_INT_ra_cr0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -106643,117 +214984,117 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_cr0_1 \dp_INT_ra_cr0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $354 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_cr0_1 - connect \Y $280 + connect \Y $353 end - process $group_167 + process $group_185 assign \addr_en_INT_ra_cr0_1 5'00000 - assign \addr_en_INT_ra_cr0_1 $280 + assign \addr_en_INT_ra_cr0_1 $353 sync init end - process $group_168 - assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_186 + assign \fus_src1_i$33 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_cr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$32 \int_src1__data_o + assign \fus_src1_i$33 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [0] + connect \A \fus_cu_rd__rel_o$34 [0] connect \B \fu_enable [3] - connect \Y $282 + connect \Y $355 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $282 + connect \A $355 connect \B \rdflag_INT_ra_0 - connect \Y $284 + connect \Y $357 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_trap0_2 - connect \Y $286 + connect \Y $359 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $288 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $284 - connect \B $286 - connect \Y $288 + connect \A $357 + connect \B $359 + connect \Y $361 end - process $group_169 + process $group_187 assign \pick_INT_ra_trap0_2 1'0 - assign \pick_INT_ra_trap0_2 $288 + assign \pick_INT_ra_trap0_2 $361 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast2_trap0_1$next - process $group_170 - assign \fus_cu_rd__go_i$34 4'0000 - assign \fus_cu_rd__go_i$34 [0] \dp_INT_ra_trap0_2 - assign \fus_cu_rd__go_i$34 [1] \dp_INT_rb_trap0_2 - assign \fus_cu_rd__go_i$34 [2] \dp_FAST_fast1_trap0_1 - assign \fus_cu_rd__go_i$34 [3] \dp_FAST_fast2_trap0_1 + process $group_188 + assign \fus_cu_rd__go_i$35 4'0000 + assign \fus_cu_rd__go_i$35 [0] \dp_INT_ra_trap0_2 + assign \fus_cu_rd__go_i$35 [1] \dp_INT_rb_trap0_2 + assign \fus_cu_rd__go_i$35 [2] \dp_FAST_fast1_trap0_1 + assign \fus_cu_rd__go_i$35 [3] \dp_FAST_fast2_trap0_1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106761,14 +215102,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o - connect \Y $290 + connect \Y $363 end - process $group_171 + process $group_189 assign \rp_INT_ra_trap0_2 1'0 - assign \rp_INT_ra_trap0_2 $290 + assign \rp_INT_ra_trap0_2 $363 sync init end - process $group_172 + process $group_190 assign \dp_INT_ra_trap0_2$next \dp_INT_ra_trap0_2 assign \dp_INT_ra_trap0_2$next \rp_INT_ra_trap0_2 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -106781,107 +215122,112 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_trap0_2 \dp_INT_ra_trap0_2$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $292 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $366 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_trap0_2 - connect \Y $292 + connect \Y $365 end - process $group_173 + process $group_191 assign \addr_en_INT_ra_trap0_2 5'00000 - assign \addr_en_INT_ra_trap0_2 $292 + assign \addr_en_INT_ra_trap0_2 $365 sync init end - process $group_174 - assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_192 + assign \fus_src1_i$36 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_trap0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$35 \int_src1__data_o + assign \fus_src1_i$36 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $294 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$36 [0] + connect \A \fus_cu_rd__rel_o$37 [0] connect \B \fu_enable [4] - connect \Y $294 + connect \Y $367 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $294 + connect \A $367 connect \B \rdflag_INT_ra_0 - connect \Y $296 + connect \Y $369 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $298 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_logical0_3 - connect \Y $298 + connect \Y $371 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $296 - connect \B $298 - connect \Y $300 + connect \A $369 + connect \B $371 + connect \Y $373 end - process $group_175 + process $group_193 assign \pick_INT_ra_logical0_3 1'0 - assign \pick_INT_ra_logical0_3 $300 + assign \pick_INT_ra_logical0_3 $373 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_logical0_3$next - process $group_176 - assign \fus_cu_rd__go_i$37 2'00 - assign \fus_cu_rd__go_i$37 [0] \dp_INT_ra_logical0_3 - assign \fus_cu_rd__go_i$37 [1] \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_logical0_1$next + process $group_194 + assign \fus_cu_rd__go_i$38 3'000 + assign \fus_cu_rd__go_i$38 [0] \dp_INT_ra_logical0_3 + assign \fus_cu_rd__go_i$38 [1] \dp_INT_rb_logical0_3 + assign \fus_cu_rd__go_i$38 [2] \dp_XER_xer_so_logical0_1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106889,14 +215235,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $302 + connect \Y $375 end - process $group_177 + process $group_195 assign \rp_INT_ra_logical0_3 1'0 - assign \rp_INT_ra_logical0_3 $302 + assign \rp_INT_ra_logical0_3 $375 sync init end - process $group_178 + process $group_196 assign \dp_INT_ra_logical0_3$next \dp_INT_ra_logical0_3 assign \dp_INT_ra_logical0_3$next \rp_INT_ra_logical0_3 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -106909,127 +215255,127 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_logical0_3 \dp_INT_ra_logical0_3$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $378 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_logical0_3 - connect \Y $304 + connect \Y $377 end - process $group_179 + process $group_197 assign \addr_en_INT_ra_logical0_3 5'00000 - assign \addr_en_INT_ra_logical0_3 $304 + assign \addr_en_INT_ra_logical0_3 $377 sync init end - process $group_180 - assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_198 + assign \fus_src1_i$39 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_logical0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$38 \int_src1__data_o + assign \fus_src1_i$39 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [0] + connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [5] - connect \Y $306 + connect \Y $379 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $308 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $306 + connect \A $379 connect \B \rdflag_INT_ra_0 - connect \Y $308 + connect \Y $381 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_spr0_4 - connect \Y $310 + connect \Y $383 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $308 - connect \B $310 - connect \Y $312 + connect \A $381 + connect \B $383 + connect \Y $385 end - process $group_181 + process $group_199 assign \pick_INT_ra_spr0_4 1'0 - assign \pick_INT_ra_spr0_4 $312 + assign \pick_INT_ra_spr0_4 $385 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \dp_XER_xer_so_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \dp_XER_xer_so_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_SPR_spr1_spr0_0$next - process $group_182 - assign \fus_cu_rd__go_i$40 6'000000 - assign \fus_cu_rd__go_i$40 [0] \dp_INT_ra_spr0_4 - assign \fus_cu_rd__go_i$40 [3] \dp_XER_xer_so_spr0_1 - assign \fus_cu_rd__go_i$40 [5] \dp_XER_xer_ca_spr0_1 - assign \fus_cu_rd__go_i$40 [4] \dp_XER_xer_ov_spr0_0 - assign \fus_cu_rd__go_i$40 [2] \dp_FAST_fast1_spr0_2 - assign \fus_cu_rd__go_i$40 [1] \dp_SPR_spr1_spr0_0 + process $group_200 + assign \fus_cu_rd__go_i$41 6'000000 + assign \fus_cu_rd__go_i$41 [0] \dp_INT_ra_spr0_4 + assign \fus_cu_rd__go_i$41 [3] \dp_XER_xer_so_spr0_2 + assign \fus_cu_rd__go_i$41 [5] \dp_XER_xer_ca_spr0_1 + assign \fus_cu_rd__go_i$41 [4] \dp_XER_xer_ov_spr0_0 + assign \fus_cu_rd__go_i$41 [2] \dp_FAST_fast1_spr0_2 + assign \fus_cu_rd__go_i$41 [1] \dp_SPR_spr1_spr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107037,14 +215383,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $314 + connect \Y $387 end - process $group_183 + process $group_201 assign \rp_INT_ra_spr0_4 1'0 - assign \rp_INT_ra_spr0_4 $314 + assign \rp_INT_ra_spr0_4 $387 sync init end - process $group_184 + process $group_202 assign \dp_INT_ra_spr0_4$next \dp_INT_ra_spr0_4 assign \dp_INT_ra_spr0_4$next \rp_INT_ra_spr0_4 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107057,112 +215403,112 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_spr0_4 \dp_INT_ra_spr0_4$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $317 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $390 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_spr0_4 - connect \Y $316 + connect \Y $389 end - process $group_185 + process $group_203 assign \addr_en_INT_ra_spr0_4 5'00000 - assign \addr_en_INT_ra_spr0_4 $316 + assign \addr_en_INT_ra_spr0_4 $389 sync init end - process $group_186 - assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_204 + assign \fus_src1_i$42 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_spr0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$41 \int_src1__data_o + assign \fus_src1_i$42 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $318 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [0] + connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [6] - connect \Y $318 + connect \Y $391 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $318 + connect \A $391 connect \B \rdflag_INT_ra_0 - connect \Y $320 + connect \Y $393 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_div0_5 - connect \Y $322 + connect \Y $395 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $320 - connect \B $322 - connect \Y $324 + connect \A $393 + connect \B $395 + connect \Y $397 end - process $group_187 + process $group_205 assign \pick_INT_ra_div0_5 1'0 - assign \pick_INT_ra_div0_5 $324 + assign \pick_INT_ra_div0_5 $397 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \dp_XER_xer_so_div0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \dp_XER_xer_so_div0_2$next - process $group_188 - assign \fus_cu_rd__go_i$43 3'000 - assign \fus_cu_rd__go_i$43 [0] \dp_INT_ra_div0_5 - assign \fus_cu_rd__go_i$43 [1] \dp_INT_rb_div0_4 - assign \fus_cu_rd__go_i$43 [2] \dp_XER_xer_so_div0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_div0_3$next + process $group_206 + assign \fus_cu_rd__go_i$44 3'000 + assign \fus_cu_rd__go_i$44 [0] \dp_INT_ra_div0_5 + assign \fus_cu_rd__go_i$44 [1] \dp_INT_rb_div0_4 + assign \fus_cu_rd__go_i$44 [2] \dp_XER_xer_so_div0_3 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107170,14 +215516,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $326 + connect \Y $399 end - process $group_189 + process $group_207 assign \rp_INT_ra_div0_5 1'0 - assign \rp_INT_ra_div0_5 $326 + assign \rp_INT_ra_div0_5 $399 sync init end - process $group_190 + process $group_208 assign \dp_INT_ra_div0_5$next \dp_INT_ra_div0_5 assign \dp_INT_ra_div0_5$next \rp_INT_ra_div0_5 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107190,112 +215536,112 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_div0_5 \dp_INT_ra_div0_5$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $328 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $402 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_div0_5 - connect \Y $328 + connect \Y $401 end - process $group_191 + process $group_209 assign \addr_en_INT_ra_div0_5 5'00000 - assign \addr_en_INT_ra_div0_5 $328 + assign \addr_en_INT_ra_div0_5 $401 sync init end - process $group_192 - assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_210 + assign \fus_src1_i$45 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_div0_5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$44 \int_src1__data_o + assign \fus_src1_i$45 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [0] + connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [7] - connect \Y $330 + connect \Y $403 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $332 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $330 + connect \A $403 connect \B \rdflag_INT_ra_0 - connect \Y $332 + connect \Y $405 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $334 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_mul0_6 - connect \Y $334 + connect \Y $407 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $332 - connect \B $334 - connect \Y $336 + connect \A $405 + connect \B $407 + connect \Y $409 end - process $group_193 + process $group_211 assign \pick_INT_ra_mul0_6 1'0 - assign \pick_INT_ra_mul0_6 $336 + assign \pick_INT_ra_mul0_6 $409 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \dp_XER_xer_so_mul0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \dp_XER_xer_so_mul0_3$next - process $group_194 - assign \fus_cu_rd__go_i$46 3'000 - assign \fus_cu_rd__go_i$46 [0] \dp_INT_ra_mul0_6 - assign \fus_cu_rd__go_i$46 [1] \dp_INT_rb_mul0_5 - assign \fus_cu_rd__go_i$46 [2] \dp_XER_xer_so_mul0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_mul0_4$next + process $group_212 + assign \fus_cu_rd__go_i$47 3'000 + assign \fus_cu_rd__go_i$47 [0] \dp_INT_ra_mul0_6 + assign \fus_cu_rd__go_i$47 [1] \dp_INT_rb_mul0_5 + assign \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_mul0_4 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $338 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107303,14 +215649,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $338 + connect \Y $411 end - process $group_195 + process $group_213 assign \rp_INT_ra_mul0_6 1'0 - assign \rp_INT_ra_mul0_6 $338 + assign \rp_INT_ra_mul0_6 $411 sync init end - process $group_196 + process $group_214 assign \dp_INT_ra_mul0_6$next \dp_INT_ra_mul0_6 assign \dp_INT_ra_mul0_6$next \rp_INT_ra_mul0_6 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107323,117 +215669,122 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_mul0_6 \dp_INT_ra_mul0_6$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $340 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $414 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_mul0_6 - connect \Y $340 + connect \Y $413 end - process $group_197 + process $group_215 assign \addr_en_INT_ra_mul0_6 5'00000 - assign \addr_en_INT_ra_mul0_6 $340 + assign \addr_en_INT_ra_mul0_6 $413 sync init end - process $group_198 - assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_216 + assign \fus_src1_i$48 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_mul0_6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$47 \int_src1__data_o + assign \fus_src1_i$48 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $342 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [0] + connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [8] - connect \Y $342 + connect \Y $415 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $344 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $342 + connect \A $415 connect \B \rdflag_INT_ra_0 - connect \Y $344 + connect \Y $417 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $346 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_shiftrot0_7 - connect \Y $346 + connect \Y $419 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $348 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $344 - connect \B $346 - connect \Y $348 + connect \A $417 + connect \B $419 + connect \Y $421 end - process $group_199 + process $group_217 assign \pick_INT_ra_shiftrot0_7 1'0 - assign \pick_INT_ra_shiftrot0_7 $348 + assign \pick_INT_ra_shiftrot0_7 $421 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire width 1 \dp_XER_xer_so_shiftrot0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_XER_xer_ca_shiftrot0_2$next - process $group_200 - assign \fus_cu_rd__go_i$49 4'0000 - assign \fus_cu_rd__go_i$49 [0] \dp_INT_ra_shiftrot0_7 - assign \fus_cu_rd__go_i$49 [1] \dp_INT_rb_shiftrot0_6 - assign \fus_cu_rd__go_i$49 [2] \dp_INT_rc_shiftrot0_0 - assign \fus_cu_rd__go_i$49 [3] \dp_XER_xer_ca_shiftrot0_2 + process $group_218 + assign \fus_cu_rd__go_i$50 5'00000 + assign \fus_cu_rd__go_i$50 [0] \dp_INT_ra_shiftrot0_7 + assign \fus_cu_rd__go_i$50 [1] \dp_INT_rb_shiftrot0_6 + assign \fus_cu_rd__go_i$50 [2] \dp_INT_rc_shiftrot0_0 + assign \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_shiftrot0_5 + assign \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ca_shiftrot0_2 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $350 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107441,14 +215792,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $350 + connect \Y $423 end - process $group_201 + process $group_219 assign \rp_INT_ra_shiftrot0_7 1'0 - assign \rp_INT_ra_shiftrot0_7 $350 + assign \rp_INT_ra_shiftrot0_7 $423 sync init end - process $group_202 + process $group_220 assign \dp_INT_ra_shiftrot0_7$next \dp_INT_ra_shiftrot0_7 assign \dp_INT_ra_shiftrot0_7$next \rp_INT_ra_shiftrot0_7 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107461,112 +215812,112 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_shiftrot0_7 \dp_INT_ra_shiftrot0_7$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $426 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $352 + connect \Y $425 end - process $group_203 + process $group_221 assign \addr_en_INT_ra_shiftrot0_7 5'00000 - assign \addr_en_INT_ra_shiftrot0_7 $352 + assign \addr_en_INT_ra_shiftrot0_7 $425 sync init end - process $group_204 - assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_222 + assign \fus_src1_i$51 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_shiftrot0_7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$50 \int_src1__data_o + assign \fus_src1_i$51 \int_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $354 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$51 [0] + connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [9] - connect \Y $354 + connect \Y $427 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $356 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $354 + connect \A $427 connect \B \rdflag_INT_ra_0 - connect \Y $356 + connect \Y $429 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_ra_ldst0_8 - connect \Y $358 + connect \Y $431 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $356 - connect \B $358 - connect \Y $360 + connect \A $429 + connect \B $431 + connect \Y $433 end - process $group_205 + process $group_223 assign \pick_INT_ra_ldst0_8 1'0 - assign \pick_INT_ra_ldst0_8 $360 + assign \pick_INT_ra_ldst0_8 $433 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_INT_rc_ldst0_1$next - process $group_206 - assign \fus_cu_rd__go_i$52 3'000 - assign \fus_cu_rd__go_i$52 [0] \dp_INT_ra_ldst0_8 - assign \fus_cu_rd__go_i$52 [1] \dp_INT_rb_ldst0_7 - assign \fus_cu_rd__go_i$52 [2] \dp_INT_rc_ldst0_1 + process $group_224 + assign \fus_cu_rd__go_i$53 3'000 + assign \fus_cu_rd__go_i$53 [0] \dp_INT_ra_ldst0_8 + assign \fus_cu_rd__go_i$53 [1] \dp_INT_rb_ldst0_7 + assign \fus_cu_rd__go_i$53 [2] \dp_INT_rc_ldst0_1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107574,14 +215925,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $362 + connect \Y $435 end - process $group_207 + process $group_225 assign \rp_INT_ra_ldst0_8 1'0 - assign \rp_INT_ra_ldst0_8 $362 + assign \rp_INT_ra_ldst0_8 $435 sync init end - process $group_208 + process $group_226 assign \dp_INT_ra_ldst0_8$next \dp_INT_ra_ldst0_8 assign \dp_INT_ra_ldst0_8$next \rp_INT_ra_ldst0_8 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107594,37 +215945,37 @@ module \core sync posedge \coresync_clk update \dp_INT_ra_ldst0_8 \dp_INT_ra_ldst0_8$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $438 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg1 + connect \B \core_reg1 connect \S \rp_INT_ra_ldst0_8 - connect \Y $364 + connect \Y $437 end - process $group_209 + process $group_227 assign \addr_en_INT_ra_ldst0_8 5'00000 - assign \addr_en_INT_ra_ldst0_8 $364 + assign \addr_en_INT_ra_ldst0_8 $437 sync init end - process $group_210 - assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_228 + assign \fus_src1_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_ra_ldst0_8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$53 \int_src1__data_o + assign \fus_src1_i$54 \int_src1__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $366 + wire width 5 $439 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $367 + cell $or $440 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107632,12 +215983,12 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_alu0_0 connect \B \addr_en_INT_ra_cr0_1 - connect \Y $366 + connect \Y $439 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $368 + wire width 5 $441 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $369 + cell $or $442 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107645,25 +215996,25 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_trap0_2 connect \B \addr_en_INT_ra_logical0_3 - connect \Y $368 + connect \Y $441 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $370 + wire width 5 $443 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $371 + cell $or $444 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $366 - connect \B $368 - connect \Y $370 + connect \A $439 + connect \B $441 + connect \Y $443 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $372 + wire width 5 $445 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $373 + cell $or $446 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107671,12 +216022,12 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_spr0_4 connect \B \addr_en_INT_ra_div0_5 - connect \Y $372 + connect \Y $445 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $374 + wire width 5 $447 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $375 + cell $or $448 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107684,80 +216035,80 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_shiftrot0_7 connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $374 + connect \Y $447 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $376 + wire width 5 $449 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $377 + cell $or $450 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_mul0_6 - connect \B $374 - connect \Y $376 + connect \B $447 + connect \Y $449 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $378 + wire width 5 $451 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $379 + cell $or $452 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $372 - connect \B $376 - connect \Y $378 + connect \A $445 + connect \B $449 + connect \Y $451 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $380 + wire width 5 $453 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $381 + cell $or $454 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $370 - connect \B $378 - connect \Y $380 + connect \A $443 + connect \B $451 + connect \Y $453 end - process $group_211 + process $group_229 assign \int_src1__addr 5'00000 - assign \int_src1__addr $380 + assign \int_src1__addr $453 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 $382 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - cell $reduce_bool $383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + wire width 1 $455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + cell $reduce_bool $456 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $382 + connect \Y $455 end - process $group_212 + process $group_230 assign \int_src1__ren 1'0 - assign \int_src1__ren $382 + assign \int_src1__ren $455 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_INT_rb_0 - process $group_213 + process $group_231 assign \rdflag_INT_rb_0 1'0 - assign \rdflag_INT_rb_0 \reg2_ok + assign \rdflag_INT_rb_0 \core_reg2_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107765,64 +216116,64 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $384 + connect \Y $457 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $384 + connect \A $457 connect \B \rdflag_INT_rb_0 - connect \Y $386 + connect \Y $459 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_alu0_0 - connect \Y $388 + connect \Y $461 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $386 - connect \B $388 - connect \Y $390 + connect \A $459 + connect \B $461 + connect \Y $463 end - process $group_214 + process $group_232 assign \pick_INT_rb_alu0_0 1'0 - assign \pick_INT_rb_alu0_0 $390 + assign \pick_INT_rb_alu0_0 $463 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rb_ldst0_7 - process $group_215 + process $group_233 assign \rdpick_INT_rb_i 8'00000000 assign \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 assign \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 @@ -107834,12 +216185,12 @@ module \core assign \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $392 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107847,14 +216198,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [0] connect \B \rdpick_INT_rb_en_o - connect \Y $392 + connect \Y $465 end - process $group_216 + process $group_234 assign \rp_INT_rb_alu0_0 1'0 - assign \rp_INT_rb_alu0_0 $392 + assign \rp_INT_rb_alu0_0 $465 sync init end - process $group_217 + process $group_235 assign \dp_INT_rb_alu0_0$next \dp_INT_rb_alu0_0 assign \dp_INT_rb_alu0_0$next \rp_INT_rb_alu0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107867,93 +216218,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_alu0_0 \dp_INT_rb_alu0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $394 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $468 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_alu0_0 - connect \Y $394 + connect \Y $467 end - process $group_218 + process $group_236 assign \addr_en_INT_rb_alu0_0 5'00000 - assign \addr_en_INT_rb_alu0_0 $394 + assign \addr_en_INT_rb_alu0_0 $467 sync init end - process $group_219 + process $group_237 assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 assign \fus_src2_i \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [1] + connect \A \fus_cu_rd__rel_o$31 [1] connect \B \fu_enable [1] - connect \Y $396 + connect \Y $469 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $396 + connect \A $469 connect \B \rdflag_INT_rb_0 - connect \Y $398 + connect \Y $471 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_cr0_1 - connect \Y $400 + connect \Y $473 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $398 - connect \B $400 - connect \Y $402 + connect \A $471 + connect \B $473 + connect \Y $475 end - process $group_220 + process $group_238 assign \pick_INT_rb_cr0_1 1'0 - assign \pick_INT_rb_cr0_1 $402 + assign \pick_INT_rb_cr0_1 $475 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $404 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107961,14 +216312,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [1] connect \B \rdpick_INT_rb_en_o - connect \Y $404 + connect \Y $477 end - process $group_221 + process $group_239 assign \rp_INT_rb_cr0_1 1'0 - assign \rp_INT_rb_cr0_1 $404 + assign \rp_INT_rb_cr0_1 $477 sync init end - process $group_222 + process $group_240 assign \dp_INT_rb_cr0_1$next \dp_INT_rb_cr0_1 assign \dp_INT_rb_cr0_1$next \rp_INT_rb_cr0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -107981,93 +216332,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_cr0_1 \dp_INT_rb_cr0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $480 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_cr0_1 - connect \Y $406 + connect \Y $479 end - process $group_223 + process $group_241 assign \addr_en_INT_rb_cr0_1 5'00000 - assign \addr_en_INT_rb_cr0_1 $406 + assign \addr_en_INT_rb_cr0_1 $479 sync init end - process $group_224 - assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_242 + assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_cr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$54 \int_src2__data_o + assign \fus_src2_i$55 \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [1] + connect \A \fus_cu_rd__rel_o$34 [1] connect \B \fu_enable [3] - connect \Y $408 + connect \Y $481 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $408 + connect \A $481 connect \B \rdflag_INT_rb_0 - connect \Y $410 + connect \Y $483 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $412 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_trap0_2 - connect \Y $412 + connect \Y $485 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $414 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $410 - connect \B $412 - connect \Y $414 + connect \A $483 + connect \B $485 + connect \Y $487 end - process $group_225 + process $group_243 assign \pick_INT_rb_trap0_2 1'0 - assign \pick_INT_rb_trap0_2 $414 + assign \pick_INT_rb_trap0_2 $487 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $416 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108075,14 +216426,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [2] connect \B \rdpick_INT_rb_en_o - connect \Y $416 + connect \Y $489 end - process $group_226 + process $group_244 assign \rp_INT_rb_trap0_2 1'0 - assign \rp_INT_rb_trap0_2 $416 + assign \rp_INT_rb_trap0_2 $489 sync init end - process $group_227 + process $group_245 assign \dp_INT_rb_trap0_2$next \dp_INT_rb_trap0_2 assign \dp_INT_rb_trap0_2$next \rp_INT_rb_trap0_2 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108095,93 +216446,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_trap0_2 \dp_INT_rb_trap0_2$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $418 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $492 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_trap0_2 - connect \Y $418 + connect \Y $491 end - process $group_228 + process $group_246 assign \addr_en_INT_rb_trap0_2 5'00000 - assign \addr_en_INT_rb_trap0_2 $418 + assign \addr_en_INT_rb_trap0_2 $491 sync init end - process $group_229 - assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_247 + assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_trap0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$55 \int_src2__data_o + assign \fus_src2_i$56 \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$36 [1] + connect \A \fus_cu_rd__rel_o$37 [1] connect \B \fu_enable [4] - connect \Y $420 + connect \Y $493 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $422 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $420 + connect \A $493 connect \B \rdflag_INT_rb_0 - connect \Y $422 + connect \Y $495 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_logical0_3 - connect \Y $424 + connect \Y $497 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $422 - connect \B $424 - connect \Y $426 + connect \A $495 + connect \B $497 + connect \Y $499 end - process $group_230 + process $group_248 assign \pick_INT_rb_logical0_3 1'0 - assign \pick_INT_rb_logical0_3 $426 + assign \pick_INT_rb_logical0_3 $499 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $428 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108189,14 +216540,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [3] connect \B \rdpick_INT_rb_en_o - connect \Y $428 + connect \Y $501 end - process $group_231 + process $group_249 assign \rp_INT_rb_logical0_3 1'0 - assign \rp_INT_rb_logical0_3 $428 + assign \rp_INT_rb_logical0_3 $501 sync init end - process $group_232 + process $group_250 assign \dp_INT_rb_logical0_3$next \dp_INT_rb_logical0_3 assign \dp_INT_rb_logical0_3$next \rp_INT_rb_logical0_3 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108209,93 +216560,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_logical0_3 \dp_INT_rb_logical0_3$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $430 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $504 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_logical0_3 - connect \Y $430 + connect \Y $503 end - process $group_233 + process $group_251 assign \addr_en_INT_rb_logical0_3 5'00000 - assign \addr_en_INT_rb_logical0_3 $430 + assign \addr_en_INT_rb_logical0_3 $503 sync init end - process $group_234 - assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_252 + assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_logical0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$56 \int_src2__data_o + assign \fus_src2_i$57 \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $432 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [1] + connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [6] - connect \Y $432 + connect \Y $505 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $434 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $432 + connect \A $505 connect \B \rdflag_INT_rb_0 - connect \Y $434 + connect \Y $507 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $436 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_div0_4 - connect \Y $436 + connect \Y $509 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $438 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $439 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $434 - connect \B $436 - connect \Y $438 + connect \A $507 + connect \B $509 + connect \Y $511 end - process $group_235 + process $group_253 assign \pick_INT_rb_div0_4 1'0 - assign \pick_INT_rb_div0_4 $438 + assign \pick_INT_rb_div0_4 $511 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $440 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108303,14 +216654,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [4] connect \B \rdpick_INT_rb_en_o - connect \Y $440 + connect \Y $513 end - process $group_236 + process $group_254 assign \rp_INT_rb_div0_4 1'0 - assign \rp_INT_rb_div0_4 $440 + assign \rp_INT_rb_div0_4 $513 sync init end - process $group_237 + process $group_255 assign \dp_INT_rb_div0_4$next \dp_INT_rb_div0_4 assign \dp_INT_rb_div0_4$next \rp_INT_rb_div0_4 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108323,93 +216674,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_div0_4 \dp_INT_rb_div0_4$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $442 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $516 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_div0_4 - connect \Y $442 + connect \Y $515 end - process $group_238 + process $group_256 assign \addr_en_INT_rb_div0_4 5'00000 - assign \addr_en_INT_rb_div0_4 $442 + assign \addr_en_INT_rb_div0_4 $515 sync init end - process $group_239 - assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_257 + assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_div0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$57 \int_src2__data_o + assign \fus_src2_i$58 \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $445 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [1] + connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [7] - connect \Y $444 + connect \Y $517 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $446 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $444 + connect \A $517 connect \B \rdflag_INT_rb_0 - connect \Y $446 + connect \Y $519 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_mul0_5 - connect \Y $448 + connect \Y $521 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $446 - connect \B $448 - connect \Y $450 + connect \A $519 + connect \B $521 + connect \Y $523 end - process $group_240 + process $group_258 assign \pick_INT_rb_mul0_5 1'0 - assign \pick_INT_rb_mul0_5 $450 + assign \pick_INT_rb_mul0_5 $523 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108417,14 +216768,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [5] connect \B \rdpick_INT_rb_en_o - connect \Y $452 + connect \Y $525 end - process $group_241 + process $group_259 assign \rp_INT_rb_mul0_5 1'0 - assign \rp_INT_rb_mul0_5 $452 + assign \rp_INT_rb_mul0_5 $525 sync init end - process $group_242 + process $group_260 assign \dp_INT_rb_mul0_5$next \dp_INT_rb_mul0_5 assign \dp_INT_rb_mul0_5$next \rp_INT_rb_mul0_5 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108437,93 +216788,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_mul0_5 \dp_INT_rb_mul0_5$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $528 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_mul0_5 - connect \Y $454 + connect \Y $527 end - process $group_243 + process $group_261 assign \addr_en_INT_rb_mul0_5 5'00000 - assign \addr_en_INT_rb_mul0_5 $454 + assign \addr_en_INT_rb_mul0_5 $527 sync init end - process $group_244 - assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_262 + assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_mul0_5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$58 \int_src2__data_o + assign \fus_src2_i$59 \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $456 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [1] + connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [8] - connect \Y $456 + connect \Y $529 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $458 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $456 + connect \A $529 connect \B \rdflag_INT_rb_0 - connect \Y $458 + connect \Y $531 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_shiftrot0_6 - connect \Y $460 + connect \Y $533 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $462 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $458 - connect \B $460 - connect \Y $462 + connect \A $531 + connect \B $533 + connect \Y $535 end - process $group_245 + process $group_263 assign \pick_INT_rb_shiftrot0_6 1'0 - assign \pick_INT_rb_shiftrot0_6 $462 + assign \pick_INT_rb_shiftrot0_6 $535 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $464 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108531,14 +216882,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [6] connect \B \rdpick_INT_rb_en_o - connect \Y $464 + connect \Y $537 end - process $group_246 + process $group_264 assign \rp_INT_rb_shiftrot0_6 1'0 - assign \rp_INT_rb_shiftrot0_6 $464 + assign \rp_INT_rb_shiftrot0_6 $537 sync init end - process $group_247 + process $group_265 assign \dp_INT_rb_shiftrot0_6$next \dp_INT_rb_shiftrot0_6 assign \dp_INT_rb_shiftrot0_6$next \rp_INT_rb_shiftrot0_6 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108551,93 +216902,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_shiftrot0_6 \dp_INT_rb_shiftrot0_6$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $540 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $466 + connect \Y $539 end - process $group_248 + process $group_266 assign \addr_en_INT_rb_shiftrot0_6 5'00000 - assign \addr_en_INT_rb_shiftrot0_6 $466 + assign \addr_en_INT_rb_shiftrot0_6 $539 sync init end - process $group_249 - assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_267 + assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_shiftrot0_6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$59 \int_src2__data_o + assign \fus_src2_i$60 \int_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$51 [1] + connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [9] - connect \Y $468 + connect \Y $541 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $470 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $468 + connect \A $541 connect \B \rdflag_INT_rb_0 - connect \Y $470 + connect \Y $543 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rb_ldst0_7 - connect \Y $472 + connect \Y $545 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $470 - connect \B $472 - connect \Y $474 + connect \A $543 + connect \B $545 + connect \Y $547 end - process $group_250 + process $group_268 assign \pick_INT_rb_ldst0_7 1'0 - assign \pick_INT_rb_ldst0_7 $474 + assign \pick_INT_rb_ldst0_7 $547 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108645,14 +216996,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [7] connect \B \rdpick_INT_rb_en_o - connect \Y $476 + connect \Y $549 end - process $group_251 + process $group_269 assign \rp_INT_rb_ldst0_7 1'0 - assign \rp_INT_rb_ldst0_7 $476 + assign \rp_INT_rb_ldst0_7 $549 sync init end - process $group_252 + process $group_270 assign \dp_INT_rb_ldst0_7$next \dp_INT_rb_ldst0_7 assign \dp_INT_rb_ldst0_7$next \rp_INT_rb_ldst0_7 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108665,37 +217016,37 @@ module \core sync posedge \coresync_clk update \dp_INT_rb_ldst0_7 \dp_INT_rb_ldst0_7$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $552 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg2 + connect \B \core_reg2 connect \S \rp_INT_rb_ldst0_7 - connect \Y $478 + connect \Y $551 end - process $group_253 + process $group_271 assign \addr_en_INT_rb_ldst0_7 5'00000 - assign \addr_en_INT_rb_ldst0_7 $478 + assign \addr_en_INT_rb_ldst0_7 $551 sync init end - process $group_254 - assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_272 + assign \fus_src2_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rb_ldst0_7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$60 \int_src2__data_o + assign \fus_src2_i$61 \int_src2__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $480 + wire width 5 $553 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $481 + cell $or $554 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -108703,12 +217054,12 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_alu0_0 connect \B \addr_en_INT_rb_cr0_1 - connect \Y $480 + connect \Y $553 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $482 + wire width 5 $555 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $483 + cell $or $556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -108716,25 +217067,25 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_trap0_2 connect \B \addr_en_INT_rb_logical0_3 - connect \Y $482 + connect \Y $555 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $484 + wire width 5 $557 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $485 + cell $or $558 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $480 - connect \B $482 - connect \Y $484 + connect \A $553 + connect \B $555 + connect \Y $557 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $486 + wire width 5 $559 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $487 + cell $or $560 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -108742,12 +217093,12 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_div0_4 connect \B \addr_en_INT_rb_mul0_5 - connect \Y $486 + connect \Y $559 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $488 + wire width 5 $561 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $489 + cell $or $562 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -108755,131 +217106,131 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_shiftrot0_6 connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $488 + connect \Y $561 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $490 + wire width 5 $563 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $491 + cell $or $564 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $486 - connect \B $488 - connect \Y $490 + connect \A $559 + connect \B $561 + connect \Y $563 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $492 + wire width 5 $565 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $493 + cell $or $566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $484 - connect \B $490 - connect \Y $492 + connect \A $557 + connect \B $563 + connect \Y $565 end - process $group_255 + process $group_273 assign \int_src2__addr 5'00000 - assign \int_src2__addr $492 + assign \int_src2__addr $565 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 $494 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - cell $reduce_bool $495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + wire width 1 $567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + cell $reduce_bool $568 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $494 + connect \Y $567 end - process $group_256 + process $group_274 assign \int_src2__ren 1'0 - assign \int_src2__ren $494 + assign \int_src2__ren $567 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_INT_rc_0 - process $group_257 + process $group_275 assign \rdflag_INT_rc_0 1'0 - assign \rdflag_INT_rc_0 \reg3_ok + assign \rdflag_INT_rc_0 \core_reg3_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $496 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [2] + connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [8] - connect \Y $496 + connect \Y $569 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $498 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $496 + connect \A $569 connect \B \rdflag_INT_rc_0 - connect \Y $498 + connect \Y $571 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $500 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rc_shiftrot0_0 - connect \Y $500 + connect \Y $573 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $498 - connect \B $500 - connect \Y $502 + connect \A $571 + connect \B $573 + connect \Y $575 end - process $group_258 + process $group_276 assign \pick_INT_rc_shiftrot0_0 1'0 - assign \pick_INT_rc_shiftrot0_0 $502 + assign \pick_INT_rc_shiftrot0_0 $575 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_INT_rc_ldst0_1 - process $group_259 + process $group_277 assign \rdpick_INT_rc_i 2'00 assign \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 assign \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $504 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108887,14 +217238,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [0] connect \B \rdpick_INT_rc_en_o - connect \Y $504 + connect \Y $577 end - process $group_260 + process $group_278 assign \rp_INT_rc_shiftrot0_0 1'0 - assign \rp_INT_rc_shiftrot0_0 $504 + assign \rp_INT_rc_shiftrot0_0 $577 sync init end - process $group_261 + process $group_279 assign \dp_INT_rc_shiftrot0_0$next \dp_INT_rc_shiftrot0_0 assign \dp_INT_rc_shiftrot0_0$next \rp_INT_rc_shiftrot0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -108907,93 +217258,93 @@ module \core sync posedge \coresync_clk update \dp_INT_rc_shiftrot0_0 \dp_INT_rc_shiftrot0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $506 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $580 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg3 + connect \B \core_reg3 connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $506 + connect \Y $579 end - process $group_262 + process $group_280 assign \addr_en_INT_rc_shiftrot0_0 5'00000 - assign \addr_en_INT_rc_shiftrot0_0 $506 + assign \addr_en_INT_rc_shiftrot0_0 $579 sync init end - process $group_263 + process $group_281 assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rc_shiftrot0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 assign \fus_src3_i \int_src3__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$51 [2] + connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [9] - connect \Y $508 + connect \Y $581 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $510 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $508 + connect \A $581 connect \B \rdflag_INT_rc_0 - connect \Y $510 + connect \Y $583 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $512 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rc_ldst0_1 - connect \Y $512 + connect \Y $585 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $510 - connect \B $512 - connect \Y $514 + connect \A $583 + connect \B $585 + connect \Y $587 end - process $group_264 + process $group_282 assign \pick_INT_rc_ldst0_1 1'0 - assign \pick_INT_rc_ldst0_1 $514 + assign \pick_INT_rc_ldst0_1 $587 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109001,14 +217352,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [1] connect \B \rdpick_INT_rc_en_o - connect \Y $516 + connect \Y $589 end - process $group_265 + process $group_283 assign \rp_INT_rc_ldst0_1 1'0 - assign \rp_INT_rc_ldst0_1 $516 + assign \rp_INT_rc_ldst0_1 $589 sync init end - process $group_266 + process $group_284 assign \dp_INT_rc_ldst0_1$next \dp_INT_rc_ldst0_1 assign \dp_INT_rc_ldst0_1$next \rp_INT_rc_ldst0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -109021,37 +217372,37 @@ module \core sync posedge \coresync_clk update \dp_INT_rc_ldst0_1 \dp_INT_rc_ldst0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 5 \addr_en_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 5 $518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 5 $591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $592 parameter \WIDTH 5 connect \A 5'00000 - connect \B \reg3 + connect \B \core_reg3 connect \S \rp_INT_rc_ldst0_1 - connect \Y $518 + connect \Y $591 end - process $group_267 + process $group_285 assign \addr_en_INT_rc_ldst0_1 5'00000 - assign \addr_en_INT_rc_ldst0_1 $518 + assign \addr_en_INT_rc_ldst0_1 $591 sync init end - process $group_268 - assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_286 + assign \fus_src3_i$62 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_INT_rc_ldst0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$61 \int_src3__data_o + assign \fus_src3_i$62 \int_src3__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $520 + wire width 5 $593 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $521 + cell $or $594 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -109059,67 +217410,119 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rc_shiftrot0_0 connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $520 + connect \Y $593 end - process $group_269 + process $group_287 assign \int_src3__addr 5'00000 - assign \int_src3__addr $520 + assign \int_src3__addr $593 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 $522 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - cell $reduce_bool $523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + wire width 1 $595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + cell $reduce_bool $596 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $522 + connect \Y $595 end - process $group_270 + process $group_288 assign \int_src3__ren 1'0 - assign \int_src3__ren $522 + assign \int_src3__ren $595 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $524 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $524 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $597 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 $599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $599 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $526 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $599 + connect \B 1'1 + connect \Y $601 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 1 $603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $524 - connect \B \xer_in - connect \Y $526 + connect \A $597 + connect \B $601 + connect \Y $603 end - process $group_271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $605 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $603 + connect \B $605 + connect \Y $607 + end + process $group_289 assign \rdflag_XER_xer_so_0 1'0 - assign \rdflag_XER_xer_so_0 $526 + assign \rdflag_XER_xer_so_0 $607 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $528 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109127,69 +217530,75 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $528 + connect \Y $609 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $528 + connect \A $609 connect \B \rdflag_XER_xer_so_0 - connect \Y $530 + connect \Y $611 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_alu0_0 - connect \Y $532 + connect \Y $613 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $534 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $530 - connect \B $532 - connect \Y $534 + connect \A $611 + connect \B $613 + connect \Y $615 end - process $group_272 + process $group_290 assign \pick_XER_xer_so_alu0_0 1'0 - assign \pick_XER_xer_so_alu0_0 $534 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" - wire width 1 \pick_XER_xer_so_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" - wire width 1 \pick_XER_xer_so_div0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" - wire width 1 \pick_XER_xer_so_mul0_3 - process $group_273 - assign \rdpick_XER_xer_so_i 4'0000 + assign \pick_XER_xer_so_alu0_0 $615 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" + wire width 1 \pick_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" + wire width 1 \pick_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" + wire width 1 \pick_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" + wire width 1 \pick_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" + wire width 1 \pick_XER_xer_so_shiftrot0_5 + process $group_291 + assign \rdpick_XER_xer_so_i 6'000000 assign \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - assign \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_spr0_1 - assign \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_div0_2 - assign \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_mul0_3 + assign \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 + assign \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 + assign \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 + assign \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 + assign \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $536 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109197,14 +217606,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $536 + connect \Y $617 end - process $group_274 + process $group_292 assign \rp_XER_xer_so_alu0_0 1'0 - assign \rp_XER_xer_so_alu0_0 $536 + assign \rp_XER_xer_so_alu0_0 $617 sync init end - process $group_275 + process $group_293 assign \dp_XER_xer_so_alu0_0$next \dp_XER_xer_so_alu0_0 assign \dp_XER_xer_so_alu0_0$next \rp_XER_xer_so_alu0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -109217,93 +217626,93 @@ module \core sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 \dp_XER_xer_so_alu0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 1 \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 1 $538 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 1 $619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $620 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $538 + connect \Y $619 end - process $group_276 + process $group_294 assign \addr_en_XER_xer_so_alu0_0 1'0 - assign \addr_en_XER_xer_so_alu0_0 $538 + assign \addr_en_XER_xer_so_alu0_0 $619 sync init end - process $group_277 - assign \fus_src3_i$62 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_295 + assign \fus_src3_i$63 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_XER_xer_so_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$62 \xer_src1__data_o [0] + assign \fus_src3_i$63 \xer_src1__data_o [0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $540 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [3] - connect \B \fu_enable [5] - connect \Y $540 + connect \A \fus_cu_rd__rel_o$37 [2] + connect \B \fu_enable [4] + connect \Y $621 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $542 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $540 + connect \A $621 connect \B \rdflag_XER_xer_so_0 - connect \Y $542 + connect \Y $623 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $544 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_spr0_1 - connect \Y $544 + connect \A \dp_XER_xer_so_logical0_1 + connect \Y $625 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $546 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $542 - connect \B $544 - connect \Y $546 + connect \A $623 + connect \B $625 + connect \Y $627 end - process $group_278 - assign \pick_XER_xer_so_spr0_1 1'0 - assign \pick_XER_xer_so_spr0_1 $546 + process $group_296 + assign \pick_XER_xer_so_logical0_1 1'0 + assign \pick_XER_xer_so_logical0_1 $627 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" - wire width 1 \rp_XER_xer_so_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $548 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 \rp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109311,374 +217720,654 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $548 + connect \Y $629 end - process $group_279 - assign \rp_XER_xer_so_spr0_1 1'0 - assign \rp_XER_xer_so_spr0_1 $548 + process $group_297 + assign \rp_XER_xer_so_logical0_1 1'0 + assign \rp_XER_xer_so_logical0_1 $629 sync init end - process $group_280 - assign \dp_XER_xer_so_spr0_1$next \dp_XER_xer_so_spr0_1 - assign \dp_XER_xer_so_spr0_1$next \rp_XER_xer_so_spr0_1 + process $group_298 + assign \dp_XER_xer_so_logical0_1$next \dp_XER_xer_so_logical0_1 + assign \dp_XER_xer_so_logical0_1$next \rp_XER_xer_so_logical0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \dp_XER_xer_so_spr0_1$next 1'0 + assign \dp_XER_xer_so_logical0_1$next 1'0 end sync init - update \dp_XER_xer_so_spr0_1 1'0 + update \dp_XER_xer_so_logical0_1 1'0 sync posedge \coresync_clk - update \dp_XER_xer_so_spr0_1 \dp_XER_xer_so_spr0_1$next + update \dp_XER_xer_so_logical0_1 \dp_XER_xer_so_logical0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" + wire width 1 \addr_en_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 1 $631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $632 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_logical0_1 + connect \Y $631 + end + process $group_299 + assign \addr_en_XER_xer_so_logical0_1 1'0 + assign \addr_en_XER_xer_so_logical0_1 $631 + sync init + end + process $group_300 + assign \fus_src3_i$64 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch { \dp_XER_xer_so_logical0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + case 1'1 + assign \fus_src3_i$64 \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [3] + connect \B \fu_enable [5] + connect \Y $633 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $633 + connect \B \rdflag_XER_xer_so_0 + connect \Y $635 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_spr0_2 + connect \Y $637 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $635 + connect \B $637 + connect \Y $639 + end + process $group_301 + assign \pick_XER_xer_so_spr0_2 1'0 + assign \pick_XER_xer_so_spr0_2 $639 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 \rp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [2] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $641 + end + process $group_302 + assign \rp_XER_xer_so_spr0_2 1'0 + assign \rp_XER_xer_so_spr0_2 $641 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 \addr_en_XER_xer_so_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 1 $550 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $551 + process $group_303 + assign \dp_XER_xer_so_spr0_2$next \dp_XER_xer_so_spr0_2 + assign \dp_XER_xer_so_spr0_2$next \rp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_so_spr0_2$next 1'0 + end + sync init + update \dp_XER_xer_so_spr0_2 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_2 \dp_XER_xer_so_spr0_2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" + wire width 1 \addr_en_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 1 $643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $644 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \rp_XER_xer_so_spr0_1 - connect \Y $550 + connect \S \rp_XER_xer_so_spr0_2 + connect \Y $643 end - process $group_281 - assign \addr_en_XER_xer_so_spr0_1 1'0 - assign \addr_en_XER_xer_so_spr0_1 $550 + process $group_304 + assign \addr_en_XER_xer_so_spr0_2 1'0 + assign \addr_en_XER_xer_so_spr0_2 $643 sync init end - process $group_282 + process $group_305 assign \fus_src4_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" - switch { \dp_XER_xer_so_spr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch { \dp_XER_xer_so_spr0_2 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 assign \fus_src4_i \xer_src1__data_o [0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $552 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [2] + connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [6] - connect \Y $552 + connect \Y $645 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $554 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $552 + connect \A $645 connect \B \rdflag_XER_xer_so_0 - connect \Y $554 + connect \Y $647 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $556 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_div0_2 - connect \Y $556 + connect \A \dp_XER_xer_so_div0_3 + connect \Y $649 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $554 - connect \B $556 - connect \Y $558 + connect \A $647 + connect \B $649 + connect \Y $651 end - process $group_283 - assign \pick_XER_xer_so_div0_2 1'0 - assign \pick_XER_xer_so_div0_2 $558 + process $group_306 + assign \pick_XER_xer_so_div0_3 1'0 + assign \pick_XER_xer_so_div0_3 $651 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" - wire width 1 \rp_XER_xer_so_div0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $560 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 \rp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [2] + connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $560 + connect \Y $653 end - process $group_284 - assign \rp_XER_xer_so_div0_2 1'0 - assign \rp_XER_xer_so_div0_2 $560 + process $group_307 + assign \rp_XER_xer_so_div0_3 1'0 + assign \rp_XER_xer_so_div0_3 $653 sync init end - process $group_285 - assign \dp_XER_xer_so_div0_2$next \dp_XER_xer_so_div0_2 - assign \dp_XER_xer_so_div0_2$next \rp_XER_xer_so_div0_2 + process $group_308 + assign \dp_XER_xer_so_div0_3$next \dp_XER_xer_so_div0_3 + assign \dp_XER_xer_so_div0_3$next \rp_XER_xer_so_div0_3 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \dp_XER_xer_so_div0_2$next 1'0 + assign \dp_XER_xer_so_div0_3$next 1'0 end sync init - update \dp_XER_xer_so_div0_2 1'0 + update \dp_XER_xer_so_div0_3 1'0 sync posedge \coresync_clk - update \dp_XER_xer_so_div0_2 \dp_XER_xer_so_div0_2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 \addr_en_XER_xer_so_div0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 1 $562 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $563 + update \dp_XER_xer_so_div0_3 \dp_XER_xer_so_div0_3$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" + wire width 1 \addr_en_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 1 $655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $656 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \rp_XER_xer_so_div0_2 - connect \Y $562 + connect \S \rp_XER_xer_so_div0_3 + connect \Y $655 end - process $group_286 - assign \addr_en_XER_xer_so_div0_2 1'0 - assign \addr_en_XER_xer_so_div0_2 $562 + process $group_309 + assign \addr_en_XER_xer_so_div0_3 1'0 + assign \addr_en_XER_xer_so_div0_3 $655 sync init end - process $group_287 - assign \fus_src3_i$63 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" - switch { \dp_XER_xer_so_div0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_310 + assign \fus_src3_i$65 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch { \dp_XER_xer_so_div0_3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$63 \xer_src1__data_o [0] + assign \fus_src3_i$65 \xer_src1__data_o [0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [2] + connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [7] - connect \Y $564 + connect \Y $657 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $566 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $564 + connect \A $657 connect \B \rdflag_XER_xer_so_0 - connect \Y $566 + connect \Y $659 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_mul0_3 - connect \Y $568 + connect \A \dp_XER_xer_so_mul0_4 + connect \Y $661 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $570 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $566 - connect \B $568 - connect \Y $570 + connect \A $659 + connect \B $661 + connect \Y $663 end - process $group_288 - assign \pick_XER_xer_so_mul0_3 1'0 - assign \pick_XER_xer_so_mul0_3 $570 + process $group_311 + assign \pick_XER_xer_so_mul0_4 1'0 + assign \pick_XER_xer_so_mul0_4 $663 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" - wire width 1 \rp_XER_xer_so_mul0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $572 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 \rp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [3] + connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $572 + connect \Y $665 end - process $group_289 - assign \rp_XER_xer_so_mul0_3 1'0 - assign \rp_XER_xer_so_mul0_3 $572 + process $group_312 + assign \rp_XER_xer_so_mul0_4 1'0 + assign \rp_XER_xer_so_mul0_4 $665 sync init end - process $group_290 - assign \dp_XER_xer_so_mul0_3$next \dp_XER_xer_so_mul0_3 - assign \dp_XER_xer_so_mul0_3$next \rp_XER_xer_so_mul0_3 + process $group_313 + assign \dp_XER_xer_so_mul0_4$next \dp_XER_xer_so_mul0_4 + assign \dp_XER_xer_so_mul0_4$next \rp_XER_xer_so_mul0_4 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \dp_XER_xer_so_mul0_3$next 1'0 + assign \dp_XER_xer_so_mul0_4$next 1'0 end sync init - update \dp_XER_xer_so_mul0_3 1'0 + update \dp_XER_xer_so_mul0_4 1'0 sync posedge \coresync_clk - update \dp_XER_xer_so_mul0_3 \dp_XER_xer_so_mul0_3$next + update \dp_XER_xer_so_mul0_4 \dp_XER_xer_so_mul0_4$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" + wire width 1 \addr_en_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 1 $667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $668 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_mul0_4 + connect \Y $667 + end + process $group_314 + assign \addr_en_XER_xer_so_mul0_4 1'0 + assign \addr_en_XER_xer_so_mul0_4 $667 + sync init + end + process $group_315 + assign \fus_src3_i$66 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch { \dp_XER_xer_so_mul0_4 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + case 1'1 + assign \fus_src3_i$66 \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$49 [3] + connect \B \fu_enable [8] + connect \Y $669 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $669 + connect \B \rdflag_XER_xer_so_0 + connect \Y $671 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_shiftrot0_5 + connect \Y $673 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $671 + connect \B $673 + connect \Y $675 + end + process $group_316 + assign \pick_XER_xer_so_shiftrot0_5 1'0 + assign \pick_XER_xer_so_shiftrot0_5 $675 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 \rp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [5] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $677 + end + process $group_317 + assign \rp_XER_xer_so_shiftrot0_5 1'0 + assign \rp_XER_xer_so_shiftrot0_5 $677 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - wire width 1 \addr_en_XER_xer_so_mul0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 1 $574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $575 + process $group_318 + assign \dp_XER_xer_so_shiftrot0_5$next \dp_XER_xer_so_shiftrot0_5 + assign \dp_XER_xer_so_shiftrot0_5$next \rp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_so_shiftrot0_5$next 1'0 + end + sync init + update \dp_XER_xer_so_shiftrot0_5 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_so_shiftrot0_5 \dp_XER_xer_so_shiftrot0_5$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" + wire width 1 \addr_en_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 1 $679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $680 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \rp_XER_xer_so_mul0_3 - connect \Y $574 + connect \S \rp_XER_xer_so_shiftrot0_5 + connect \Y $679 end - process $group_291 - assign \addr_en_XER_xer_so_mul0_3 1'0 - assign \addr_en_XER_xer_so_mul0_3 $574 + process $group_319 + assign \addr_en_XER_xer_so_shiftrot0_5 1'0 + assign \addr_en_XER_xer_so_shiftrot0_5 $679 sync init end - process $group_292 - assign \fus_src3_i$64 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" - switch { \dp_XER_xer_so_mul0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_320 + assign \fus_src4_i$67 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch { \dp_XER_xer_so_shiftrot0_5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$64 \xer_src1__data_o [0] + assign \fus_src4_i$67 \xer_src1__data_o [0] end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $576 + wire width 3 $681 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $577 + wire width 1 $682 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $578 + cell $or $683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_logical0_1 + connect \B \addr_en_XER_xer_so_spr0_2 + connect \Y $682 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $684 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \addr_en_XER_xer_so_spr0_1 - connect \Y $577 + connect \B $682 + connect \Y $684 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $579 + wire width 1 $686 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $580 + cell $or $687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_div0_2 - connect \B \addr_en_XER_xer_so_mul0_3 - connect \Y $579 + connect \A \addr_en_XER_xer_so_mul0_4 + connect \B \addr_en_XER_xer_so_shiftrot0_5 + connect \Y $686 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $581 + wire width 1 $688 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $582 + cell $or $689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $577 - connect \B $579 - connect \Y $581 + connect \A \addr_en_XER_xer_so_div0_3 + connect \B $686 + connect \Y $688 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $690 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $684 + connect \B $688 + connect \Y $690 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $583 + cell $pos $692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A $581 - connect \Y $576 + connect \A $690 + connect \Y $681 end - process $group_293 + process $group_321 assign \xer_src1__ren 3'000 - assign \xer_src1__ren $576 + assign \xer_src1__ren $681 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $584 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire width 1 $693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $694 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \input_carry + connect \A \core_core_input_carry connect \B 2'10 - connect \Y $584 + connect \Y $693 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $586 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 $695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $695 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $695 + connect \B 3'100 + connect \Y $697 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 1 $699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $584 - connect \B \xer_in - connect \Y $586 + connect \A $693 + connect \B $697 + connect \Y $699 end - process $group_294 + process $group_322 assign \rdflag_XER_xer_ca_0 1'0 - assign \rdflag_XER_xer_ca_0 $586 + assign \rdflag_XER_xer_ca_0 $699 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $588 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109686,66 +218375,66 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $588 + connect \Y $701 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $590 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $588 + connect \A $701 connect \B \rdflag_XER_xer_ca_0 - connect \Y $590 + connect \Y $703 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $592 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_alu0_0 - connect \Y $592 + connect \Y $705 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $594 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $590 - connect \B $592 - connect \Y $594 + connect \A $703 + connect \B $705 + connect \Y $707 end - process $group_295 + process $group_323 assign \pick_XER_xer_ca_alu0_0 1'0 - assign \pick_XER_xer_ca_alu0_0 $594 + assign \pick_XER_xer_ca_alu0_0 $707 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_XER_xer_ca_shiftrot0_2 - process $group_296 + process $group_324 assign \rdpick_XER_xer_ca_i 3'000 assign \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 assign \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 assign \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $596 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109753,14 +218442,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $596 + connect \Y $709 end - process $group_297 + process $group_325 assign \rp_XER_xer_ca_alu0_0 1'0 - assign \rp_XER_xer_ca_alu0_0 $596 + assign \rp_XER_xer_ca_alu0_0 $709 sync init end - process $group_298 + process $group_326 assign \dp_XER_xer_ca_alu0_0$next \dp_XER_xer_ca_alu0_0 assign \dp_XER_xer_ca_alu0_0$next \rp_XER_xer_ca_alu0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -109773,93 +218462,93 @@ module \core sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 \dp_XER_xer_ca_alu0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 2 $598 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 2 $711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $712 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $598 + connect \Y $711 end - process $group_299 + process $group_327 assign \addr_en_XER_xer_ca_alu0_0 2'00 - assign \addr_en_XER_xer_ca_alu0_0 $598 + assign \addr_en_XER_xer_ca_alu0_0 $711 sync init end - process $group_300 - assign \fus_src4_i$65 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_328 + assign \fus_src4_i$68 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_XER_xer_ca_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src4_i$65 \xer_src2__data_o + assign \fus_src4_i$68 \xer_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $600 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [5] + connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [5] - connect \Y $600 + connect \Y $713 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $602 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $600 + connect \A $713 connect \B \rdflag_XER_xer_ca_0 - connect \Y $602 + connect \Y $715 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $604 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_spr0_1 - connect \Y $604 + connect \Y $717 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $606 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $602 - connect \B $604 - connect \Y $606 + connect \A $715 + connect \B $717 + connect \Y $719 end - process $group_301 + process $group_329 assign \pick_XER_xer_ca_spr0_1 1'0 - assign \pick_XER_xer_ca_spr0_1 $606 + assign \pick_XER_xer_ca_spr0_1 $719 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $608 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109867,14 +218556,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $608 + connect \Y $721 end - process $group_302 + process $group_330 assign \rp_XER_xer_ca_spr0_1 1'0 - assign \rp_XER_xer_ca_spr0_1 $608 + assign \rp_XER_xer_ca_spr0_1 $721 sync init end - process $group_303 + process $group_331 assign \dp_XER_xer_ca_spr0_1$next \dp_XER_xer_ca_spr0_1 assign \dp_XER_xer_ca_spr0_1$next \rp_XER_xer_ca_spr0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -109887,93 +218576,93 @@ module \core sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 \dp_XER_xer_ca_spr0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 2 $610 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 2 $723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $724 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $610 + connect \Y $723 end - process $group_304 + process $group_332 assign \addr_en_XER_xer_ca_spr0_1 2'00 - assign \addr_en_XER_xer_ca_spr0_1 $610 + assign \addr_en_XER_xer_ca_spr0_1 $723 sync init end - process $group_305 + process $group_333 assign \fus_src6_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_XER_xer_ca_spr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 assign \fus_src6_i \xer_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $612 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [3] + connect \A \fus_cu_rd__rel_o$49 [4] connect \B \fu_enable [8] - connect \Y $612 + connect \Y $725 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $614 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $612 + connect \A $725 connect \B \rdflag_XER_xer_ca_0 - connect \Y $614 + connect \Y $727 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $616 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_shiftrot0_2 - connect \Y $616 + connect \Y $729 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $618 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $614 - connect \B $616 - connect \Y $618 + connect \A $727 + connect \B $729 + connect \Y $731 end - process $group_306 + process $group_334 assign \pick_XER_xer_ca_shiftrot0_2 1'0 - assign \pick_XER_xer_ca_shiftrot0_2 $618 + assign \pick_XER_xer_ca_shiftrot0_2 $731 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109981,14 +218670,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $620 + connect \Y $733 end - process $group_307 + process $group_335 assign \rp_XER_xer_ca_shiftrot0_2 1'0 - assign \rp_XER_xer_ca_shiftrot0_2 $620 + assign \rp_XER_xer_ca_shiftrot0_2 $733 sync init end - process $group_308 + process $group_336 assign \dp_XER_xer_ca_shiftrot0_2$next \dp_XER_xer_ca_shiftrot0_2 assign \dp_XER_xer_ca_shiftrot0_2$next \rp_XER_xer_ca_shiftrot0_2 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110001,39 +218690,39 @@ module \core sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 \dp_XER_xer_ca_shiftrot0_2$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 2 $622 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 2 $735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $736 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $622 + connect \Y $735 end - process $group_309 + process $group_337 assign \addr_en_XER_xer_ca_shiftrot0_2 2'00 - assign \addr_en_XER_xer_ca_shiftrot0_2 $622 + assign \addr_en_XER_xer_ca_shiftrot0_2 $735 sync init end - process $group_310 - assign \fus_src4_i$66 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_338 + assign \fus_src5_i 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_XER_xer_ca_shiftrot0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src4_i$66 \xer_src2__data_o + assign \fus_src5_i \xer_src2__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $624 + wire width 3 $737 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $625 + wire width 2 $738 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $626 + cell $or $739 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -110041,134 +218730,160 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $625 + connect \Y $738 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $627 + wire width 2 $740 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $628 + cell $or $741 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B $625 - connect \Y $627 + connect \B $738 + connect \Y $740 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $629 + cell $pos $742 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A $627 - connect \Y $624 + connect \A $740 + connect \Y $737 end - process $group_311 + process $group_339 assign \xer_src2__ren 3'000 - assign \xer_src2__ren $624 + assign \xer_src2__ren $737 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $630 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $and $744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oe - connect \B \oe_ok - connect \Y $630 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $743 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $632 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 3 $745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $and $746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 2'10 + connect \Y $745 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 1 $747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $eq $748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A $745 + connect \B 2'10 + connect \Y $747 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 1 $749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $or $750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $630 - connect \B \xer_in - connect \Y $632 + connect \A $743 + connect \B $747 + connect \Y $749 end - process $group_312 + process $group_340 assign \rdflag_XER_xer_ov_0 1'0 - assign \rdflag_XER_xer_ov_0 $632 + assign \rdflag_XER_xer_ov_0 $749 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $634 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [4] + connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [5] - connect \Y $634 + connect \Y $751 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $634 + connect \A $751 connect \B \rdflag_XER_xer_ov_0 - connect \Y $636 + connect \Y $753 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ov_spr0_0 - connect \Y $638 + connect \Y $755 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $640 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $636 - connect \B $638 - connect \Y $640 + connect \A $753 + connect \B $755 + connect \Y $757 end - process $group_313 + process $group_341 assign \pick_XER_xer_ov_spr0_0 1'0 - assign \pick_XER_xer_ov_spr0_0 $640 + assign \pick_XER_xer_ov_spr0_0 $757 sync init end - process $group_314 + process $group_342 assign \rdpick_XER_xer_ov_i 1'0 assign \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $642 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -110176,14 +218891,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $642 + connect \Y $759 end - process $group_315 + process $group_343 assign \rp_XER_xer_ov_spr0_0 1'0 - assign \rp_XER_xer_ov_spr0_0 $642 + assign \rp_XER_xer_ov_spr0_0 $759 sync init end - process $group_316 + process $group_344 assign \dp_XER_xer_ov_spr0_0$next \dp_XER_xer_ov_spr0_0 assign \dp_XER_xer_ov_spr0_0$next \rp_XER_xer_ov_spr0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110196,112 +218911,112 @@ module \core sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 \dp_XER_xer_ov_spr0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 3 $644 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 3 $761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $762 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $644 + connect \Y $761 end - process $group_317 + process $group_345 assign \addr_en_XER_xer_ov_spr0_0 3'000 - assign \addr_en_XER_xer_ov_spr0_0 $644 + assign \addr_en_XER_xer_ov_spr0_0 $761 sync init end - process $group_318 - assign \fus_src5_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_346 + assign \fus_src5_i$69 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_XER_xer_ov_spr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src5_i \xer_src3__data_o + assign \fus_src5_i$69 \xer_src3__data_o end sync init end - process $group_319 + process $group_347 assign \xer_src3__ren 3'000 assign \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_CR_full_cr_0 - process $group_320 + process $group_348 assign \rdflag_CR_full_cr_0 1'0 - assign \rdflag_CR_full_cr_0 \read_cr_whole + assign \rdflag_CR_full_cr_0 \core_core_cr_rd_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $646 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [2] + connect \A \fus_cu_rd__rel_o$31 [2] connect \B \fu_enable [1] - connect \Y $646 + connect \Y $763 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $648 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $646 + connect \A $763 connect \B \rdflag_CR_full_cr_0 - connect \Y $648 + connect \Y $765 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $650 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $650 + connect \Y $767 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $648 - connect \B $650 - connect \Y $652 + connect \A $765 + connect \B $767 + connect \Y $769 end - process $group_321 + process $group_349 assign \pick_CR_full_cr_cr0_0 1'0 - assign \pick_CR_full_cr_cr0_0 $652 + assign \pick_CR_full_cr_cr0_0 $769 sync init end - process $group_322 + process $group_350 assign \rdpick_CR_full_cr_i 1'0 assign \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $654 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -110309,14 +219024,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $654 + connect \Y $771 end - process $group_323 + process $group_351 assign \rp_CR_full_cr_cr0_0 1'0 - assign \rp_CR_full_cr_cr0_0 $654 + assign \rp_CR_full_cr_cr0_0 $771 sync init end - process $group_324 + process $group_352 assign \dp_CR_full_cr_cr0_0$next \dp_CR_full_cr_cr0_0 assign \dp_CR_full_cr_cr0_0$next \rp_CR_full_cr_cr0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110329,115 +219044,115 @@ module \core sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 \dp_CR_full_cr_cr0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 8 \addr_en_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 8 $656 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 8 $773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $774 parameter \WIDTH 8 connect \A 8'00000000 - connect \B 8'11111111 + connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $656 + connect \Y $773 end - process $group_325 + process $group_353 assign \addr_en_CR_full_cr_cr0_0 8'00000000 - assign \addr_en_CR_full_cr_cr0_0 $656 + assign \addr_en_CR_full_cr_cr0_0 $773 sync init end - process $group_326 - assign \fus_src3_i$67 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_354 + assign \fus_src3_i$70 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_CR_full_cr_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$67 \cr_full_rd__data_o + assign \fus_src3_i$70 \cr_full_rd__data_o end sync init end - process $group_327 + process $group_355 assign \cr_full_rd__ren 8'00000000 assign \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_CR_cr_a_0 - process $group_328 + process $group_356 assign \rdflag_CR_cr_a_0 1'0 - assign \rdflag_CR_cr_a_0 \cr_in1_ok + assign \rdflag_CR_cr_a_0 \core_cr_in1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $658 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [3] + connect \A \fus_cu_rd__rel_o$31 [3] connect \B \fu_enable [1] - connect \Y $658 + connect \Y $775 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $660 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $658 + connect \A $775 connect \B \rdflag_CR_cr_a_0 - connect \Y $660 + connect \Y $777 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $662 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $662 + connect \Y $779 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $664 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $660 - connect \B $662 - connect \Y $664 + connect \A $777 + connect \B $779 + connect \Y $781 end - process $group_329 + process $group_357 assign \pick_CR_cr_a_cr0_0 1'0 - assign \pick_CR_cr_a_cr0_0 $664 + assign \pick_CR_cr_a_cr0_0 $781 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_CR_cr_a_branch0_1 - process $group_330 + process $group_358 assign \rdpick_CR_cr_a_i 2'00 assign \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 assign \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $666 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -110445,14 +219160,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $666 + connect \Y $783 end - process $group_331 + process $group_359 assign \rp_CR_cr_a_cr0_0 1'0 - assign \rp_CR_cr_a_cr0_0 $666 + assign \rp_CR_cr_a_cr0_0 $783 sync init end - process $group_332 + process $group_360 assign \dp_CR_cr_a_cr0_0$next \dp_CR_cr_a_cr0_0 assign \dp_CR_cr_a_cr0_0$next \rp_CR_cr_a_cr0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110465,138 +219180,138 @@ module \core sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 \dp_CR_cr_a_cr0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 16 \addr_en_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 4 $668 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sub $669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 4 $785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sub $786 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_in1 - connect \Y $668 + connect \B \core_cr_in1 + connect \Y $785 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $670 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sshl $671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 16 $787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sshl $788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $668 - connect \Y $670 + connect \B $785 + connect \Y $787 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 16 $672 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 16 $789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $790 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $670 + connect \B $787 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $672 + connect \Y $789 end - process $group_333 + process $group_361 assign \addr_en_CR_cr_a_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_a_cr0_0 $672 + assign \addr_en_CR_cr_a_cr0_0 $789 sync init end - process $group_334 - assign \fus_src4_i$68 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_362 + assign \fus_src4_i$71 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_CR_cr_a_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src4_i$68 \cr_src1__data_o + assign \fus_src4_i$71 \cr_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $674 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$69 [2] + connect \A \fus_cu_rd__rel_o$72 [2] connect \B \fu_enable [2] - connect \Y $674 + connect \Y $791 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $676 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $674 + connect \A $791 connect \B \rdflag_CR_cr_a_0 - connect \Y $676 + connect \Y $793 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $678 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $678 + connect \Y $795 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $680 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $676 - connect \B $678 - connect \Y $680 + connect \A $793 + connect \B $795 + connect \Y $797 end - process $group_335 + process $group_363 assign \pick_CR_cr_a_branch0_1 1'0 - assign \pick_CR_cr_a_branch0_1 $680 + assign \pick_CR_cr_a_branch0_1 $797 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" wire width 1 \dp_FAST_fast2_branch0_0$next - process $group_336 - assign \fus_cu_rd__go_i$70 3'000 - assign \fus_cu_rd__go_i$70 [2] \dp_CR_cr_a_branch0_1 - assign \fus_cu_rd__go_i$70 [0] \dp_FAST_fast1_branch0_0 - assign \fus_cu_rd__go_i$70 [1] \dp_FAST_fast2_branch0_0 + process $group_364 + assign \fus_cu_rd__go_i$73 3'000 + assign \fus_cu_rd__go_i$73 [2] \dp_CR_cr_a_branch0_1 + assign \fus_cu_rd__go_i$73 [0] \dp_FAST_fast1_branch0_0 + assign \fus_cu_rd__go_i$73 [1] \dp_FAST_fast2_branch0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $682 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -110604,14 +219319,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $682 + connect \Y $799 end - process $group_337 + process $group_365 assign \rp_CR_cr_a_branch0_1 1'0 - assign \rp_CR_cr_a_branch0_1 $682 + assign \rp_CR_cr_a_branch0_1 $799 sync init end - process $group_338 + process $group_366 assign \dp_CR_cr_a_branch0_1$next \dp_CR_cr_a_branch0_1 assign \dp_CR_cr_a_branch0_1$next \rp_CR_cr_a_branch0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110624,65 +219339,65 @@ module \core sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 \dp_CR_cr_a_branch0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 16 \addr_en_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 4 $684 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sub $685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 4 $801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sub $802 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_in1 - connect \Y $684 + connect \B \core_cr_in1 + connect \Y $801 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $686 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sshl $687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 16 $803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sshl $804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $684 - connect \Y $686 + connect \B $801 + connect \Y $803 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 16 $688 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 16 $805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $806 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $686 + connect \B $803 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $688 + connect \Y $805 end - process $group_339 + process $group_367 assign \addr_en_CR_cr_a_branch0_1 16'0000000000000000 - assign \addr_en_CR_cr_a_branch0_1 $688 + assign \addr_en_CR_cr_a_branch0_1 $805 sync init end - process $group_340 - assign \fus_src3_i$71 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_368 + assign \fus_src3_i$74 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_CR_cr_a_branch0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$71 \cr_src1__data_o + assign \fus_src3_i$74 \cr_src1__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $690 + wire width 16 $807 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $691 + wire width 16 $808 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $692 + cell $or $809 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -110690,88 +219405,88 @@ module \core parameter \Y_WIDTH 16 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $691 + connect \Y $808 end - connect $690 $691 - process $group_341 + connect $807 $808 + process $group_369 assign \cr_src1__ren 8'00000000 - assign \cr_src1__ren $690 [7:0] + assign \cr_src1__ren $807 [7:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_CR_cr_b_0 - process $group_342 + process $group_370 assign \rdflag_CR_cr_b_0 1'0 - assign \rdflag_CR_cr_b_0 \cr_in2_ok + assign \rdflag_CR_cr_b_0 \core_cr_in2_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [4] + connect \A \fus_cu_rd__rel_o$31 [4] connect \B \fu_enable [1] - connect \Y $693 + connect \Y $810 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $693 + connect \A $810 connect \B \rdflag_CR_cr_b_0 - connect \Y $695 + connect \Y $812 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $697 + connect \Y $814 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $695 - connect \B $697 - connect \Y $699 + connect \A $812 + connect \B $814 + connect \Y $816 end - process $group_343 + process $group_371 assign \pick_CR_cr_b_cr0_0 1'0 - assign \pick_CR_cr_b_cr0_0 $699 + assign \pick_CR_cr_b_cr0_0 $816 sync init end - process $group_344 + process $group_372 assign \rdpick_CR_cr_b_i 1'0 assign \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $701 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -110779,14 +219494,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $701 + connect \Y $818 end - process $group_345 + process $group_373 assign \rp_CR_cr_b_cr0_0 1'0 - assign \rp_CR_cr_b_cr0_0 $701 + assign \rp_CR_cr_b_cr0_0 $818 sync init end - process $group_346 + process $group_374 assign \dp_CR_cr_b_cr0_0$next \dp_CR_cr_b_cr0_0 assign \dp_CR_cr_b_cr0_0$next \rp_CR_cr_b_cr0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110799,138 +219514,138 @@ module \core sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 \dp_CR_cr_b_cr0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 16 \addr_en_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 4 $703 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - cell $sub $704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + wire width 4 $820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + cell $sub $821 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_in2 - connect \Y $703 + connect \B \core_cr_in2 + connect \Y $820 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 16 $705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - cell $sshl $706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + wire width 16 $822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + cell $sshl $823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $703 - connect \Y $705 + connect \B $820 + connect \Y $822 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 16 $707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 16 $824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $825 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $705 + connect \B $822 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $707 + connect \Y $824 end - process $group_347 + process $group_375 assign \addr_en_CR_cr_b_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_b_cr0_0 $707 + assign \addr_en_CR_cr_b_cr0_0 $824 sync init end - process $group_348 - assign \fus_src5_i$72 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_376 + assign \fus_src5_i$75 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_CR_cr_b_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src5_i$72 \cr_src2__data_o + assign \fus_src5_i$75 \cr_src2__data_o end sync init end - process $group_349 + process $group_377 assign \cr_src2__ren 8'00000000 assign \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_CR_cr_c_0 - process $group_350 + process $group_378 assign \rdflag_CR_cr_c_0 1'0 - assign \rdflag_CR_cr_c_0 \cr_in2_ok$2 + assign \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $709 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [5] + connect \A \fus_cu_rd__rel_o$31 [5] connect \B \fu_enable [1] - connect \Y $709 + connect \Y $826 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $711 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $709 + connect \A $826 connect \B \rdflag_CR_cr_c_0 - connect \Y $711 + connect \Y $828 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $713 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $713 + connect \Y $830 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $715 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $711 - connect \B $713 - connect \Y $715 + connect \A $828 + connect \B $830 + connect \Y $832 end - process $group_351 + process $group_379 assign \pick_CR_cr_c_cr0_0 1'0 - assign \pick_CR_cr_c_cr0_0 $715 + assign \pick_CR_cr_c_cr0_0 $832 sync init end - process $group_352 + process $group_380 assign \rdpick_CR_cr_c_i 1'0 assign \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $717 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -110938,14 +219653,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $717 + connect \Y $834 end - process $group_353 + process $group_381 assign \rp_CR_cr_c_cr0_0 1'0 - assign \rp_CR_cr_c_cr0_0 $717 + assign \rp_CR_cr_c_cr0_0 $834 sync init end - process $group_354 + process $group_382 assign \dp_CR_cr_c_cr0_0$next \dp_CR_cr_c_cr0_0 assign \dp_CR_cr_c_cr0_0$next \rp_CR_cr_c_cr0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -110958,144 +219673,144 @@ module \core sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 \dp_CR_cr_c_cr0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 16 \addr_en_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 4 $719 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - cell $sub $720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + wire width 4 $836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + cell $sub $837 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_in2$1 - connect \Y $719 + connect \B \core_cr_in2$1 + connect \Y $836 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 16 $721 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - cell $sshl $722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + wire width 16 $838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + cell $sshl $839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $719 - connect \Y $721 + connect \B $836 + connect \Y $838 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 16 $723 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 16 $840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $841 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $721 + connect \B $838 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $723 + connect \Y $840 end - process $group_355 + process $group_383 assign \addr_en_CR_cr_c_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_c_cr0_0 $723 + assign \addr_en_CR_cr_c_cr0_0 $840 sync init end - process $group_356 - assign \fus_src6_i$73 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_384 + assign \fus_src6_i$76 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_CR_cr_c_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src6_i$73 \cr_src3__data_o + assign \fus_src6_i$76 \cr_src3__data_o end sync init end - process $group_357 + process $group_385 assign \cr_src3__ren 8'00000000 assign \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_FAST_fast1_0 - process $group_358 + process $group_386 assign \rdflag_FAST_fast1_0 1'0 - assign \rdflag_FAST_fast1_0 \fast1_ok + assign \rdflag_FAST_fast1_0 \core_fast1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $725 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$69 [0] + connect \A \fus_cu_rd__rel_o$72 [0] connect \B \fu_enable [2] - connect \Y $725 + connect \Y $842 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $727 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $725 + connect \A $842 connect \B \rdflag_FAST_fast1_0 - connect \Y $727 + connect \Y $844 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $729 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $729 + connect \Y $846 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $731 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $727 - connect \B $729 - connect \Y $731 + connect \A $844 + connect \B $846 + connect \Y $848 end - process $group_359 + process $group_387 assign \pick_FAST_fast1_branch0_0 1'0 - assign \pick_FAST_fast1_branch0_0 $731 + assign \pick_FAST_fast1_branch0_0 $848 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_FAST_fast1_spr0_2 - process $group_360 + process $group_388 assign \rdpick_FAST_fast1_i 3'000 assign \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 assign \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 assign \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $733 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111103,14 +219818,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $733 + connect \Y $850 end - process $group_361 + process $group_389 assign \rp_FAST_fast1_branch0_0 1'0 - assign \rp_FAST_fast1_branch0_0 $733 + assign \rp_FAST_fast1_branch0_0 $850 sync init end - process $group_362 + process $group_390 assign \dp_FAST_fast1_branch0_0$next \dp_FAST_fast1_branch0_0 assign \dp_FAST_fast1_branch0_0$next \rp_FAST_fast1_branch0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -111123,93 +219838,93 @@ module \core sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 \dp_FAST_fast1_branch0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 3 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 3 $735 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 3 $852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $853 parameter \WIDTH 3 connect \A 3'000 - connect \B \fast1 + connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $735 + connect \Y $852 end - process $group_363 + process $group_391 assign \addr_en_FAST_fast1_branch0_0 3'000 - assign \addr_en_FAST_fast1_branch0_0 $735 + assign \addr_en_FAST_fast1_branch0_0 $852 sync init end - process $group_364 - assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_392 + assign \fus_src1_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_FAST_fast1_branch0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src1_i$74 \fast_src1__data_o + assign \fus_src1_i$77 \fast_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [2] + connect \A \fus_cu_rd__rel_o$34 [2] connect \B \fu_enable [3] - connect \Y $737 + connect \Y $854 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $739 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $737 + connect \A $854 connect \B \rdflag_FAST_fast1_0 - connect \Y $739 + connect \Y $856 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $741 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $741 + connect \Y $858 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $743 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $739 - connect \B $741 - connect \Y $743 + connect \A $856 + connect \B $858 + connect \Y $860 end - process $group_365 + process $group_393 assign \pick_FAST_fast1_trap0_1 1'0 - assign \pick_FAST_fast1_trap0_1 $743 + assign \pick_FAST_fast1_trap0_1 $860 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $745 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111217,14 +219932,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $745 + connect \Y $862 end - process $group_366 + process $group_394 assign \rp_FAST_fast1_trap0_1 1'0 - assign \rp_FAST_fast1_trap0_1 $745 + assign \rp_FAST_fast1_trap0_1 $862 sync init end - process $group_367 + process $group_395 assign \dp_FAST_fast1_trap0_1$next \dp_FAST_fast1_trap0_1 assign \dp_FAST_fast1_trap0_1$next \rp_FAST_fast1_trap0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -111237,93 +219952,93 @@ module \core sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 \dp_FAST_fast1_trap0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 3 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 3 $747 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 3 $864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $865 parameter \WIDTH 3 connect \A 3'000 - connect \B \fast1 + connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $747 + connect \Y $864 end - process $group_368 + process $group_396 assign \addr_en_FAST_fast1_trap0_1 3'000 - assign \addr_en_FAST_fast1_trap0_1 $747 + assign \addr_en_FAST_fast1_trap0_1 $864 sync init end - process $group_369 - assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_397 + assign \fus_src3_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_FAST_fast1_trap0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$75 \fast_src1__data_o + assign \fus_src3_i$78 \fast_src1__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $749 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [2] + connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [5] - connect \Y $749 + connect \Y $866 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $749 + connect \A $866 connect \B \rdflag_FAST_fast1_0 - connect \Y $751 + connect \Y $868 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $753 + connect \Y $870 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $751 - connect \B $753 - connect \Y $755 + connect \A $868 + connect \B $870 + connect \Y $872 end - process $group_370 + process $group_398 assign \pick_FAST_fast1_spr0_2 1'0 - assign \pick_FAST_fast1_spr0_2 $755 + assign \pick_FAST_fast1_spr0_2 $872 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $757 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111331,14 +220046,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $757 + connect \Y $874 end - process $group_371 + process $group_399 assign \rp_FAST_fast1_spr0_2 1'0 - assign \rp_FAST_fast1_spr0_2 $757 + assign \rp_FAST_fast1_spr0_2 $874 sync init end - process $group_372 + process $group_400 assign \dp_FAST_fast1_spr0_2$next \dp_FAST_fast1_spr0_2 assign \dp_FAST_fast1_spr0_2$next \rp_FAST_fast1_spr0_2 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -111351,37 +220066,37 @@ module \core sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 \dp_FAST_fast1_spr0_2$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 3 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 3 $759 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 3 $876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $877 parameter \WIDTH 3 connect \A 3'000 - connect \B \fast1 + connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $759 + connect \Y $876 end - process $group_373 + process $group_401 assign \addr_en_FAST_fast1_spr0_2 3'000 - assign \addr_en_FAST_fast1_spr0_2 $759 + assign \addr_en_FAST_fast1_spr0_2 $876 sync init end - process $group_374 - assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_402 + assign \fus_src3_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_FAST_fast1_spr0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src3_i$76 \fast_src1__data_o + assign \fus_src3_i$79 \fast_src1__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $761 + wire width 3 $878 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $762 + cell $or $879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -111389,118 +220104,118 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_trap0_1 connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $761 + connect \Y $878 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $763 + wire width 3 $880 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $764 + cell $or $881 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 - connect \B $761 - connect \Y $763 + connect \B $878 + connect \Y $880 end - process $group_375 + process $group_403 assign \fast_src1__addr 3'000 - assign \fast_src1__addr $763 + assign \fast_src1__addr $880 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 $765 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - cell $reduce_bool $766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + wire width 1 $882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + cell $reduce_bool $883 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $765 + connect \Y $882 end - process $group_376 + process $group_404 assign \fast_src1__ren 1'0 - assign \fast_src1__ren $765 + assign \fast_src1__ren $882 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_FAST_fast2_0 - process $group_377 + process $group_405 assign \rdflag_FAST_fast2_0 1'0 - assign \rdflag_FAST_fast2_0 \fast2_ok + assign \rdflag_FAST_fast2_0 \core_fast2_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $767 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$69 [1] + connect \A \fus_cu_rd__rel_o$72 [1] connect \B \fu_enable [2] - connect \Y $767 + connect \Y $884 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $769 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $767 + connect \A $884 connect \B \rdflag_FAST_fast2_0 - connect \Y $769 + connect \Y $886 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_branch0_0 - connect \Y $771 + connect \Y $888 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $773 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $769 - connect \B $771 - connect \Y $773 + connect \A $886 + connect \B $888 + connect \Y $890 end - process $group_378 + process $group_406 assign \pick_FAST_fast2_branch0_0 1'0 - assign \pick_FAST_fast2_branch0_0 $773 + assign \pick_FAST_fast2_branch0_0 $890 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_FAST_fast2_trap0_1 - process $group_379 + process $group_407 assign \rdpick_FAST_fast2_i 2'00 assign \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 assign \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $775 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111508,14 +220223,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [0] connect \B \rdpick_FAST_fast2_en_o - connect \Y $775 + connect \Y $892 end - process $group_380 + process $group_408 assign \rp_FAST_fast2_branch0_0 1'0 - assign \rp_FAST_fast2_branch0_0 $775 + assign \rp_FAST_fast2_branch0_0 $892 sync init end - process $group_381 + process $group_409 assign \dp_FAST_fast2_branch0_0$next \dp_FAST_fast2_branch0_0 assign \dp_FAST_fast2_branch0_0$next \rp_FAST_fast2_branch0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -111528,93 +220243,93 @@ module \core sync posedge \coresync_clk update \dp_FAST_fast2_branch0_0 \dp_FAST_fast2_branch0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 3 \addr_en_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 3 $777 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 3 $894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $895 parameter \WIDTH 3 connect \A 3'000 - connect \B \fast2 + connect \B \core_fast2 connect \S \rp_FAST_fast2_branch0_0 - connect \Y $777 + connect \Y $894 end - process $group_382 + process $group_410 assign \addr_en_FAST_fast2_branch0_0 3'000 - assign \addr_en_FAST_fast2_branch0_0 $777 + assign \addr_en_FAST_fast2_branch0_0 $894 sync init end - process $group_383 - assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_411 + assign \fus_src2_i$80 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_FAST_fast2_branch0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$77 \fast_src2__data_o + assign \fus_src2_i$80 \fast_src2__data_o end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [3] + connect \A \fus_cu_rd__rel_o$34 [3] connect \B \fu_enable [3] - connect \Y $779 + connect \Y $896 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $779 + connect \A $896 connect \B \rdflag_FAST_fast2_0 - connect \Y $781 + connect \Y $898 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $783 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_trap0_1 - connect \Y $783 + connect \Y $900 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $785 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $781 - connect \B $783 - connect \Y $785 + connect \A $898 + connect \B $900 + connect \Y $902 end - process $group_384 + process $group_412 assign \pick_FAST_fast2_trap0_1 1'0 - assign \pick_FAST_fast2_trap0_1 $785 + assign \pick_FAST_fast2_trap0_1 $902 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111622,14 +220337,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [1] connect \B \rdpick_FAST_fast2_en_o - connect \Y $787 + connect \Y $904 end - process $group_385 + process $group_413 assign \rp_FAST_fast2_trap0_1 1'0 - assign \rp_FAST_fast2_trap0_1 $787 + assign \rp_FAST_fast2_trap0_1 $904 sync init end - process $group_386 + process $group_414 assign \dp_FAST_fast2_trap0_1$next \dp_FAST_fast2_trap0_1 assign \dp_FAST_fast2_trap0_1$next \rp_FAST_fast2_trap0_1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -111642,37 +220357,37 @@ module \core sync posedge \coresync_clk update \dp_FAST_fast2_trap0_1 \dp_FAST_fast2_trap0_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 3 \addr_en_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 3 $789 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 3 $906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $907 parameter \WIDTH 3 connect \A 3'000 - connect \B \fast2 + connect \B \core_fast2 connect \S \rp_FAST_fast2_trap0_1 - connect \Y $789 + connect \Y $906 end - process $group_387 + process $group_415 assign \addr_en_FAST_fast2_trap0_1 3'000 - assign \addr_en_FAST_fast2_trap0_1 $789 + assign \addr_en_FAST_fast2_trap0_1 $906 sync init end - process $group_388 - assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_416 + assign \fus_src4_i$81 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_FAST_fast2_trap0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src4_i$78 \fast_src2__data_o + assign \fus_src4_i$81 \fast_src2__data_o end sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $791 + wire width 3 $908 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $792 + cell $or $909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -111680,102 +220395,102 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast2_branch0_0 connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $791 + connect \Y $908 end - process $group_389 + process $group_417 assign \fast_src2__addr 3'000 - assign \fast_src2__addr $791 + assign \fast_src2__addr $908 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 $793 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - cell $reduce_bool $794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + wire width 1 $910 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + cell $reduce_bool $911 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $793 + connect \Y $910 end - process $group_390 + process $group_418 assign \fast_src2__ren 1'0 - assign \fast_src2__ren $793 + assign \fast_src2__ren $910 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" wire width 1 \rdflag_SPR_spr1_0 - process $group_391 + process $group_419 assign \rdflag_SPR_spr1_0 1'0 - assign \rdflag_SPR_spr1_0 \spr1_ok + assign \rdflag_SPR_spr1_0 \core_spr1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" wire width 1 \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $795 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $912 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [1] + connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [5] - connect \Y $795 + connect \Y $912 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - wire width 1 $797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" - cell $and $798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + wire width 1 $914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" + cell $and $915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $795 + connect \A $912 connect \B \rdflag_SPR_spr1_0 - connect \Y $797 + connect \Y $914 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $not $800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $not $917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $799 + connect \Y $916 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - wire width 1 $801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" - cell $and $802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + wire width 1 $918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" + cell $and $919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $797 - connect \B $799 - connect \Y $801 + connect \A $914 + connect \B $916 + connect \Y $918 end - process $group_392 + process $group_420 assign \pick_SPR_spr1_spr0_0 1'0 - assign \pick_SPR_spr1_spr0_0 $801 + assign \pick_SPR_spr1_spr0_0 $918 sync init end - process $group_393 + process $group_421 assign \rdpick_SPR_spr1_i 1'0 assign \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" wire width 1 \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 $803 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - cell $and $804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire width 1 $920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + cell $and $921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111783,14 +220498,14 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $803 + connect \Y $920 end - process $group_394 + process $group_422 assign \rp_SPR_spr1_spr0_0 1'0 - assign \rp_SPR_spr1_spr0_0 $803 + assign \rp_SPR_spr1_spr0_0 $920 sync init end - process $group_395 + process $group_423 assign \dp_SPR_spr1_spr0_0$next \dp_SPR_spr1_spr0_0 assign \dp_SPR_spr1_spr0_0$next \rp_SPR_spr1_spr0_0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -111803,59 +220518,59 @@ module \core sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 \dp_SPR_spr1_spr0_0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - wire width 10 $805 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" - cell $mux $806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + wire width 10 $922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $923 parameter \WIDTH 10 connect \A 10'0000000000 - connect \B \spr1 + connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $805 + connect \Y $922 end - process $group_396 + process $group_424 assign \addr_en_SPR_spr1_spr0_0 10'0000000000 - assign \addr_en_SPR_spr1_spr0_0 $805 + assign \addr_en_SPR_spr1_spr0_0 $922 sync init end - process $group_397 - assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + process $group_425 + assign \fus_src2_i$82 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" switch { \dp_SPR_spr1_spr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" case 1'1 - assign \fus_src2_i$79 \spr_spr1__data_o + assign \fus_src2_i$82 \spr_spr1__data_o end sync init end - process $group_398 + process $group_426 assign \spr_spr1__addr 7'0000000 assign \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 $807 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - cell $reduce_bool $808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + wire width 1 $924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" + cell $reduce_bool $925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A { \rp_SPR_spr1_spr0_0 } - connect \Y $807 + connect \Y $924 end - process $group_399 + process $group_427 assign \spr_spr1__ren 1'0 - assign \spr_spr1__ren $807 + assign \spr_spr1__ren $924 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111863,17 +220578,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $809 + connect \Y $926 end - process $group_400 + process $group_428 assign \wrflag_alu0_o_0 1'0 - assign \wrflag_alu0_o_0 $809 + assign \wrflag_alu0_o_0 $926 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -111881,145 +220596,145 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $811 + connect \Y $928 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $813 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$81 [0] + connect \A \fus_cu_wr__rel_o$84 [0] connect \B \fu_enable [1] - connect \Y $813 + connect \Y $930 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $815 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [0] + connect \A \fus_cu_wr__rel_o$87 [0] connect \B \fu_enable [3] - connect \Y $815 + connect \Y $932 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $817 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [0] + connect \A \fus_cu_wr__rel_o$90 [0] connect \B \fu_enable [4] - connect \Y $817 + connect \Y $934 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $819 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [0] + connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [5] - connect \Y $819 + connect \Y $936 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $821 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [0] + connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [6] - connect \Y $821 + connect \Y $938 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [0] + connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [7] - connect \Y $823 + connect \Y $940 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $825 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [0] + connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [8] - connect \Y $825 + connect \Y $942 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $827 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$101 [0] + connect \A \fus_cu_wr__rel_o$104 [0] connect \B \fu_enable [9] - connect \Y $827 + connect \Y $944 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $829 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$101 [1] + connect \A \fus_cu_wr__rel_o$104 [1] connect \B \fu_enable [9] - connect \Y $829 + connect \Y $946 end - process $group_401 + process $group_429 assign \wrpick_INT_o_i 10'0000000000 - assign \wrpick_INT_o_i [0] $811 - assign \wrpick_INT_o_i [1] $813 - assign \wrpick_INT_o_i [2] $815 - assign \wrpick_INT_o_i [3] $817 - assign \wrpick_INT_o_i [4] $819 - assign \wrpick_INT_o_i [5] $821 - assign \wrpick_INT_o_i [6] $823 - assign \wrpick_INT_o_i [7] $825 - assign \wrpick_INT_o_i [8] $827 - assign \wrpick_INT_o_i [9] $829 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + assign \wrpick_INT_o_i [0] $928 + assign \wrpick_INT_o_i [1] $930 + assign \wrpick_INT_o_i [2] $932 + assign \wrpick_INT_o_i [3] $934 + assign \wrpick_INT_o_i [4] $936 + assign \wrpick_INT_o_i [5] $938 + assign \wrpick_INT_o_i [6] $940 + assign \wrpick_INT_o_i [7] $942 + assign \wrpick_INT_o_i [8] $944 + assign \wrpick_INT_o_i [9] $946 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" wire width 1 \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $831 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112027,18 +220742,18 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $831 + connect \Y $948 end - process $group_402 + process $group_430 assign \wr_pick 1'0 - assign \wr_pick $831 + assign \wr_pick $948 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \wr_pick_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \wr_pick_dly$next - process $group_403 + process $group_431 assign \wr_pick_dly$next \wr_pick_dly assign \wr_pick_dly$next \wr_pick attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -112054,56 +220769,56 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire width 1 \wr_pick_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $833 + wire width 1 $950 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $834 + cell $not $951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $833 + connect \Y $950 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $835 + wire width 1 $952 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $836 + cell $and $953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick - connect \B $833 - connect \Y $835 + connect \B $950 + connect \Y $952 end - process $group_404 + process $group_432 assign \wr_pick_rise 1'0 - assign \wr_pick_rise $835 + assign \wr_pick_rise $952 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$837 + wire width 1 \wr_pick_rise$954 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$838 + wire width 1 \wr_pick_rise$955 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$839 + wire width 1 \wr_pick_rise$956 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$840 - process $group_405 + wire width 1 \wr_pick_rise$957 + process $group_433 assign \fus_cu_wr__go_i 5'00000 assign \fus_cu_wr__go_i [0] \wr_pick_rise - assign \fus_cu_wr__go_i [1] \wr_pick_rise$837 - assign \fus_cu_wr__go_i [2] \wr_pick_rise$838 - assign \fus_cu_wr__go_i [3] \wr_pick_rise$839 - assign \fus_cu_wr__go_i [4] \wr_pick_rise$840 + assign \fus_cu_wr__go_i [1] \wr_pick_rise$954 + assign \fus_cu_wr__go_i [2] \wr_pick_rise$955 + assign \fus_cu_wr__go_i [3] \wr_pick_rise$956 + assign \fus_cu_wr__go_i [4] \wr_pick_rise$957 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" wire width 1 \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $841 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112111,56 +220826,56 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $841 + connect \Y $958 end - process $group_406 + process $group_434 assign \wp 1'0 - assign \wp $841 + assign \wp $958 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" wire width 5 \addr_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $843 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $961 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego + connect \B \core_rego connect \S \wp - connect \Y $843 + connect \Y $960 end - process $group_407 + process $group_435 assign \addr_en 5'00000 - assign \addr_en $843 + assign \addr_en $960 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $845 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$80 - connect \B \fus_cu_busy_o$4 - connect \Y $845 + connect \A \fus_o_ok$83 + connect \B \fus_cu_busy_o$5 + connect \Y $962 end - process $group_408 + process $group_436 assign \wrflag_cr0_o_0 1'0 - assign \wrflag_cr0_o_0 $845 + assign \wrflag_cr0_o_0 $962 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$847 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112168,134 +220883,134 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $848 + connect \Y $965 end - process $group_409 - assign \wr_pick$847 1'0 - assign \wr_pick$847 $848 + process $group_437 + assign \wr_pick$964 1'0 + assign \wr_pick$964 $965 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$850 + wire width 1 \wr_pick_dly$967 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$850$next - process $group_410 - assign \wr_pick_dly$850$next \wr_pick_dly$850 - assign \wr_pick_dly$850$next \wr_pick$847 + wire width 1 \wr_pick_dly$967$next + process $group_438 + assign \wr_pick_dly$967$next \wr_pick_dly$967 + assign \wr_pick_dly$967$next \wr_pick$964 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$850$next 1'0 + assign \wr_pick_dly$967$next 1'0 end sync init - update \wr_pick_dly$850 1'0 + update \wr_pick_dly$967 1'0 sync posedge \coresync_clk - update \wr_pick_dly$850 \wr_pick_dly$850$next + update \wr_pick_dly$967 \wr_pick_dly$967$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$851 + wire width 1 \wr_pick_rise$968 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $852 + wire width 1 $969 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $853 + cell $not $970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$850 - connect \Y $852 + connect \A \wr_pick_dly$967 + connect \Y $969 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $854 + wire width 1 $971 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $855 + cell $and $972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$847 - connect \B $852 - connect \Y $854 + connect \A \wr_pick$964 + connect \B $969 + connect \Y $971 end - process $group_411 - assign \wr_pick_rise$851 1'0 - assign \wr_pick_rise$851 $854 + process $group_439 + assign \wr_pick_rise$968 1'0 + assign \wr_pick_rise$968 $971 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$856 + wire width 1 \wr_pick_rise$973 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$857 - process $group_412 - assign \fus_cu_wr__go_i$82 3'000 - assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$851 - assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$856 - assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$857 + wire width 1 \wr_pick_rise$974 + process $group_440 + assign \fus_cu_wr__go_i$85 3'000 + assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$968 + assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$973 + assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$974 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$858 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $859 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$975 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $976 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$847 + connect \A \wr_pick$964 connect \B \wrpick_INT_o_en_o - connect \Y $859 + connect \Y $976 end - process $group_413 - assign \wp$858 1'0 - assign \wp$858 $859 + process $group_441 + assign \wp$975 1'0 + assign \wp$975 $976 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$861 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $862 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $863 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $980 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$858 - connect \Y $862 + connect \B \core_rego + connect \S \wp$975 + connect \Y $979 end - process $group_414 - assign \addr_en$861 5'00000 - assign \addr_en$861 $862 + process $group_442 + assign \addr_en$978 5'00000 + assign \addr_en$978 $979 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $864 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$83 - connect \B \fus_cu_busy_o$10 - connect \Y $864 + connect \A \fus_o_ok$86 + connect \B \fus_cu_busy_o$11 + connect \Y $981 end - process $group_415 + process $group_443 assign \wrflag_trap0_o_0 1'0 - assign \wrflag_trap0_o_0 $864 + assign \wrflag_trap0_o_0 $981 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $867 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112303,140 +221018,140 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $867 + connect \Y $984 end - process $group_416 - assign \wr_pick$866 1'0 - assign \wr_pick$866 $867 + process $group_444 + assign \wr_pick$983 1'0 + assign \wr_pick$983 $984 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$869 + wire width 1 \wr_pick_dly$986 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$869$next - process $group_417 - assign \wr_pick_dly$869$next \wr_pick_dly$869 - assign \wr_pick_dly$869$next \wr_pick$866 + wire width 1 \wr_pick_dly$986$next + process $group_445 + assign \wr_pick_dly$986$next \wr_pick_dly$986 + assign \wr_pick_dly$986$next \wr_pick$983 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$869$next 1'0 + assign \wr_pick_dly$986$next 1'0 end sync init - update \wr_pick_dly$869 1'0 + update \wr_pick_dly$986 1'0 sync posedge \coresync_clk - update \wr_pick_dly$869 \wr_pick_dly$869$next + update \wr_pick_dly$986 \wr_pick_dly$986$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$870 + wire width 1 \wr_pick_rise$987 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $871 + wire width 1 $988 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $872 + cell $not $989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$869 - connect \Y $871 + connect \A \wr_pick_dly$986 + connect \Y $988 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $873 + wire width 1 $990 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $874 + cell $and $991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$866 - connect \B $871 - connect \Y $873 + connect \A \wr_pick$983 + connect \B $988 + connect \Y $990 end - process $group_418 - assign \wr_pick_rise$870 1'0 - assign \wr_pick_rise$870 $873 + process $group_446 + assign \wr_pick_rise$987 1'0 + assign \wr_pick_rise$987 $990 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$875 + wire width 1 \wr_pick_rise$992 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$876 + wire width 1 \wr_pick_rise$993 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$877 + wire width 1 \wr_pick_rise$994 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$878 - process $group_419 - assign \fus_cu_wr__go_i$85 5'00000 - assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$870 - assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$875 - assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$876 - assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$877 - assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$878 + wire width 1 \wr_pick_rise$995 + process $group_447 + assign \fus_cu_wr__go_i$88 5'00000 + assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$987 + assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$992 + assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$993 + assign \fus_cu_wr__go_i$88 [3] \wr_pick_rise$994 + assign \fus_cu_wr__go_i$88 [4] \wr_pick_rise$995 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$879 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $880 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$866 + connect \A \wr_pick$983 connect \B \wrpick_INT_o_en_o - connect \Y $880 + connect \Y $997 end - process $group_420 - assign \wp$879 1'0 - assign \wp$879 $880 + process $group_448 + assign \wp$996 1'0 + assign \wp$996 $997 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$882 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $883 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1001 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$879 - connect \Y $883 + connect \B \core_rego + connect \S \wp$996 + connect \Y $1000 end - process $group_421 - assign \addr_en$882 5'00000 - assign \addr_en$882 $883 + process $group_449 + assign \addr_en$999 5'00000 + assign \addr_en$999 $1000 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $885 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$86 - connect \B \fus_cu_busy_o$13 - connect \Y $885 + connect \A \fus_o_ok$89 + connect \B \fus_cu_busy_o$14 + connect \Y $1002 end - process $group_422 + process $group_450 assign \wrflag_logical0_o_0 1'0 - assign \wrflag_logical0_o_0 $885 + assign \wrflag_logical0_o_0 $1002 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$887 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $888 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112444,134 +221159,131 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $888 + connect \Y $1005 end - process $group_423 - assign \wr_pick$887 1'0 - assign \wr_pick$887 $888 + process $group_451 + assign \wr_pick$1004 1'0 + assign \wr_pick$1004 $1005 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$890 + wire width 1 \wr_pick_dly$1007 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$890$next - process $group_424 - assign \wr_pick_dly$890$next \wr_pick_dly$890 - assign \wr_pick_dly$890$next \wr_pick$887 + wire width 1 \wr_pick_dly$1007$next + process $group_452 + assign \wr_pick_dly$1007$next \wr_pick_dly$1007 + assign \wr_pick_dly$1007$next \wr_pick$1004 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$890$next 1'0 + assign \wr_pick_dly$1007$next 1'0 end sync init - update \wr_pick_dly$890 1'0 + update \wr_pick_dly$1007 1'0 sync posedge \coresync_clk - update \wr_pick_dly$890 \wr_pick_dly$890$next + update \wr_pick_dly$1007 \wr_pick_dly$1007$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$891 + wire width 1 \wr_pick_rise$1008 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $892 + wire width 1 $1009 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $893 + cell $not $1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$890 - connect \Y $892 + connect \A \wr_pick_dly$1007 + connect \Y $1009 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $894 + wire width 1 $1011 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $895 + cell $and $1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$887 - connect \B $892 - connect \Y $894 + connect \A \wr_pick$1004 + connect \B $1009 + connect \Y $1011 end - process $group_425 - assign \wr_pick_rise$891 1'0 - assign \wr_pick_rise$891 $894 + process $group_453 + assign \wr_pick_rise$1008 1'0 + assign \wr_pick_rise$1008 $1011 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$896 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$897 - process $group_426 - assign \fus_cu_wr__go_i$88 3'000 - assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$891 - assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$896 - assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$897 + wire width 1 \wr_pick_rise$1013 + process $group_454 + assign \fus_cu_wr__go_i$91 2'00 + assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$1008 + assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$1013 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$898 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $899 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$887 + connect \A \wr_pick$1004 connect \B \wrpick_INT_o_en_o - connect \Y $899 + connect \Y $1015 end - process $group_427 - assign \wp$898 1'0 - assign \wp$898 $899 + process $group_455 + assign \wp$1014 1'0 + assign \wp$1014 $1015 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$901 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $902 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1019 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$898 - connect \Y $902 + connect \B \core_rego + connect \S \wp$1014 + connect \Y $1018 end - process $group_428 - assign \addr_en$901 5'00000 - assign \addr_en$901 $902 + process $group_456 + assign \addr_en$1017 5'00000 + assign \addr_en$1017 $1018 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $904 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$89 - connect \B \fus_cu_busy_o$16 - connect \Y $904 + connect \A \fus_o_ok$92 + connect \B \fus_cu_busy_o$17 + connect \Y $1020 end - process $group_429 + process $group_457 assign \wrflag_spr0_o_0 1'0 - assign \wrflag_spr0_o_0 $904 + assign \wrflag_spr0_o_0 $1020 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$906 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $907 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112579,143 +221291,143 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $907 + connect \Y $1023 end - process $group_430 - assign \wr_pick$906 1'0 - assign \wr_pick$906 $907 + process $group_458 + assign \wr_pick$1022 1'0 + assign \wr_pick$1022 $1023 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$909 + wire width 1 \wr_pick_dly$1025 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$909$next - process $group_431 - assign \wr_pick_dly$909$next \wr_pick_dly$909 - assign \wr_pick_dly$909$next \wr_pick$906 + wire width 1 \wr_pick_dly$1025$next + process $group_459 + assign \wr_pick_dly$1025$next \wr_pick_dly$1025 + assign \wr_pick_dly$1025$next \wr_pick$1022 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$909$next 1'0 + assign \wr_pick_dly$1025$next 1'0 end sync init - update \wr_pick_dly$909 1'0 + update \wr_pick_dly$1025 1'0 sync posedge \coresync_clk - update \wr_pick_dly$909 \wr_pick_dly$909$next + update \wr_pick_dly$1025 \wr_pick_dly$1025$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$910 + wire width 1 \wr_pick_rise$1026 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $911 + wire width 1 $1027 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $912 + cell $not $1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$909 - connect \Y $911 + connect \A \wr_pick_dly$1025 + connect \Y $1027 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $913 + wire width 1 $1029 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $914 + cell $and $1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$906 - connect \B $911 - connect \Y $913 + connect \A \wr_pick$1022 + connect \B $1027 + connect \Y $1029 end - process $group_432 - assign \wr_pick_rise$910 1'0 - assign \wr_pick_rise$910 $913 + process $group_460 + assign \wr_pick_rise$1026 1'0 + assign \wr_pick_rise$1026 $1029 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$915 + wire width 1 \wr_pick_rise$1031 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$916 + wire width 1 \wr_pick_rise$1032 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$917 + wire width 1 \wr_pick_rise$1033 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$918 + wire width 1 \wr_pick_rise$1034 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$919 - process $group_433 - assign \fus_cu_wr__go_i$91 6'000000 - assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$910 - assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$915 - assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$916 - assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$917 - assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$918 - assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$919 + wire width 1 \wr_pick_rise$1035 + process $group_461 + assign \fus_cu_wr__go_i$94 6'000000 + assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$1026 + assign \fus_cu_wr__go_i$94 [5] \wr_pick_rise$1031 + assign \fus_cu_wr__go_i$94 [4] \wr_pick_rise$1032 + assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$1033 + assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$1034 + assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$1035 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$920 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $921 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$906 + connect \A \wr_pick$1022 connect \B \wrpick_INT_o_en_o - connect \Y $921 + connect \Y $1037 end - process $group_434 - assign \wp$920 1'0 - assign \wp$920 $921 + process $group_462 + assign \wp$1036 1'0 + assign \wp$1036 $1037 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$923 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $924 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1039 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1041 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$920 - connect \Y $924 + connect \B \core_rego + connect \S \wp$1036 + connect \Y $1040 end - process $group_435 - assign \addr_en$923 5'00000 - assign \addr_en$923 $924 + process $group_463 + assign \addr_en$1039 5'00000 + assign \addr_en$1039 $1040 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $926 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$92 - connect \B \fus_cu_busy_o$19 - connect \Y $926 + connect \A \fus_o_ok$95 + connect \B \fus_cu_busy_o$20 + connect \Y $1042 end - process $group_436 + process $group_464 assign \wrflag_div0_o_0 1'0 - assign \wrflag_div0_o_0 $926 + assign \wrflag_div0_o_0 $1042 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$928 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $929 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1045 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112723,137 +221435,137 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $929 + connect \Y $1045 end - process $group_437 - assign \wr_pick$928 1'0 - assign \wr_pick$928 $929 + process $group_465 + assign \wr_pick$1044 1'0 + assign \wr_pick$1044 $1045 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$931 + wire width 1 \wr_pick_dly$1047 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$931$next - process $group_438 - assign \wr_pick_dly$931$next \wr_pick_dly$931 - assign \wr_pick_dly$931$next \wr_pick$928 + wire width 1 \wr_pick_dly$1047$next + process $group_466 + assign \wr_pick_dly$1047$next \wr_pick_dly$1047 + assign \wr_pick_dly$1047$next \wr_pick$1044 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$931$next 1'0 + assign \wr_pick_dly$1047$next 1'0 end sync init - update \wr_pick_dly$931 1'0 + update \wr_pick_dly$1047 1'0 sync posedge \coresync_clk - update \wr_pick_dly$931 \wr_pick_dly$931$next + update \wr_pick_dly$1047 \wr_pick_dly$1047$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$932 + wire width 1 \wr_pick_rise$1048 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $933 + wire width 1 $1049 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $934 + cell $not $1050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$931 - connect \Y $933 + connect \A \wr_pick_dly$1047 + connect \Y $1049 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $935 + wire width 1 $1051 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $936 + cell $and $1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$928 - connect \B $933 - connect \Y $935 + connect \A \wr_pick$1044 + connect \B $1049 + connect \Y $1051 end - process $group_439 - assign \wr_pick_rise$932 1'0 - assign \wr_pick_rise$932 $935 + process $group_467 + assign \wr_pick_rise$1048 1'0 + assign \wr_pick_rise$1048 $1051 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$937 + wire width 1 \wr_pick_rise$1053 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$938 + wire width 1 \wr_pick_rise$1054 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$939 - process $group_440 - assign \fus_cu_wr__go_i$94 4'0000 - assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$932 - assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$937 - assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$938 - assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$939 + wire width 1 \wr_pick_rise$1055 + process $group_468 + assign \fus_cu_wr__go_i$97 4'0000 + assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1048 + assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1053 + assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1054 + assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1055 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$940 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $941 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1056 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1057 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$928 + connect \A \wr_pick$1044 connect \B \wrpick_INT_o_en_o - connect \Y $941 + connect \Y $1057 end - process $group_441 - assign \wp$940 1'0 - assign \wp$940 $941 + process $group_469 + assign \wp$1056 1'0 + assign \wp$1056 $1057 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$943 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1061 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$940 - connect \Y $944 + connect \B \core_rego + connect \S \wp$1056 + connect \Y $1060 end - process $group_442 - assign \addr_en$943 5'00000 - assign \addr_en$943 $944 + process $group_470 + assign \addr_en$1059 5'00000 + assign \addr_en$1059 $1060 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $946 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$95 - connect \B \fus_cu_busy_o$22 - connect \Y $946 + connect \A \fus_o_ok$98 + connect \B \fus_cu_busy_o$23 + connect \Y $1062 end - process $group_443 + process $group_471 assign \wrflag_mul0_o_0 1'0 - assign \wrflag_mul0_o_0 $946 + assign \wrflag_mul0_o_0 $1062 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$948 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $949 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112861,137 +221573,137 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $949 + connect \Y $1065 end - process $group_444 - assign \wr_pick$948 1'0 - assign \wr_pick$948 $949 + process $group_472 + assign \wr_pick$1064 1'0 + assign \wr_pick$1064 $1065 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$951 + wire width 1 \wr_pick_dly$1067 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$951$next - process $group_445 - assign \wr_pick_dly$951$next \wr_pick_dly$951 - assign \wr_pick_dly$951$next \wr_pick$948 + wire width 1 \wr_pick_dly$1067$next + process $group_473 + assign \wr_pick_dly$1067$next \wr_pick_dly$1067 + assign \wr_pick_dly$1067$next \wr_pick$1064 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$951$next 1'0 + assign \wr_pick_dly$1067$next 1'0 end sync init - update \wr_pick_dly$951 1'0 + update \wr_pick_dly$1067 1'0 sync posedge \coresync_clk - update \wr_pick_dly$951 \wr_pick_dly$951$next + update \wr_pick_dly$1067 \wr_pick_dly$1067$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$952 + wire width 1 \wr_pick_rise$1068 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $953 + wire width 1 $1069 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $954 + cell $not $1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$951 - connect \Y $953 + connect \A \wr_pick_dly$1067 + connect \Y $1069 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $955 + wire width 1 $1071 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $956 + cell $and $1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$948 - connect \B $953 - connect \Y $955 + connect \A \wr_pick$1064 + connect \B $1069 + connect \Y $1071 end - process $group_446 - assign \wr_pick_rise$952 1'0 - assign \wr_pick_rise$952 $955 + process $group_474 + assign \wr_pick_rise$1068 1'0 + assign \wr_pick_rise$1068 $1071 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$957 + wire width 1 \wr_pick_rise$1073 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$958 + wire width 1 \wr_pick_rise$1074 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$959 - process $group_447 - assign \fus_cu_wr__go_i$97 4'0000 - assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$952 - assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$957 - assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$958 - assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$959 + wire width 1 \wr_pick_rise$1075 + process $group_475 + assign \fus_cu_wr__go_i$100 4'0000 + assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1068 + assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1073 + assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1074 + assign \fus_cu_wr__go_i$100 [3] \wr_pick_rise$1075 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$960 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $961 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$948 + connect \A \wr_pick$1064 connect \B \wrpick_INT_o_en_o - connect \Y $961 + connect \Y $1077 end - process $group_448 - assign \wp$960 1'0 - assign \wp$960 $961 + process $group_476 + assign \wp$1076 1'0 + assign \wp$1076 $1077 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$963 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $964 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1081 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$960 - connect \Y $964 + connect \B \core_rego + connect \S \wp$1076 + connect \Y $1080 end - process $group_449 - assign \addr_en$963 5'00000 - assign \addr_en$963 $964 + process $group_477 + assign \addr_en$1079 5'00000 + assign \addr_en$1079 $1080 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $966 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$98 - connect \B \fus_cu_busy_o$25 - connect \Y $966 + connect \A \fus_o_ok$101 + connect \B \fus_cu_busy_o$26 + connect \Y $1082 end - process $group_450 + process $group_478 assign \wrflag_shiftrot0_o_0 1'0 - assign \wrflag_shiftrot0_o_0 $966 + assign \wrflag_shiftrot0_o_0 $1082 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$968 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $969 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -112999,136 +221711,136 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $969 + connect \Y $1085 end - process $group_451 - assign \wr_pick$968 1'0 - assign \wr_pick$968 $969 + process $group_479 + assign \wr_pick$1084 1'0 + assign \wr_pick$1084 $1085 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$971 + wire width 1 \wr_pick_dly$1087 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$971$next - process $group_452 - assign \wr_pick_dly$971$next \wr_pick_dly$971 - assign \wr_pick_dly$971$next \wr_pick$968 + wire width 1 \wr_pick_dly$1087$next + process $group_480 + assign \wr_pick_dly$1087$next \wr_pick_dly$1087 + assign \wr_pick_dly$1087$next \wr_pick$1084 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$971$next 1'0 + assign \wr_pick_dly$1087$next 1'0 end sync init - update \wr_pick_dly$971 1'0 + update \wr_pick_dly$1087 1'0 sync posedge \coresync_clk - update \wr_pick_dly$971 \wr_pick_dly$971$next + update \wr_pick_dly$1087 \wr_pick_dly$1087$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$972 + wire width 1 \wr_pick_rise$1088 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $973 + wire width 1 $1089 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $974 + cell $not $1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$971 - connect \Y $973 + connect \A \wr_pick_dly$1087 + connect \Y $1089 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $975 + wire width 1 $1091 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $976 + cell $and $1092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$968 - connect \B $973 - connect \Y $975 + connect \A \wr_pick$1084 + connect \B $1089 + connect \Y $1091 end - process $group_453 - assign \wr_pick_rise$972 1'0 - assign \wr_pick_rise$972 $975 + process $group_481 + assign \wr_pick_rise$1088 1'0 + assign \wr_pick_rise$1088 $1091 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$977 + wire width 1 \wr_pick_rise$1093 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$978 - process $group_454 - assign \fus_cu_wr__go_i$100 3'000 - assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$972 - assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$977 - assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$978 + wire width 1 \wr_pick_rise$1094 + process $group_482 + assign \fus_cu_wr__go_i$103 3'000 + assign \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1088 + assign \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1093 + assign \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1094 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$979 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $980 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1095 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$968 + connect \A \wr_pick$1084 connect \B \wrpick_INT_o_en_o - connect \Y $980 + connect \Y $1096 end - process $group_455 - assign \wp$979 1'0 - assign \wp$979 $980 + process $group_483 + assign \wp$1095 1'0 + assign \wp$1095 $1096 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$982 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $983 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1099 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1100 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$979 - connect \Y $983 + connect \B \core_rego + connect \S \wp$1095 + connect \Y $1099 end - process $group_456 - assign \addr_en$982 5'00000 - assign \addr_en$982 $983 + process $group_484 + assign \addr_en$1098 5'00000 + assign \addr_en$1098 $1099 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_ldst0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $985 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok - connect \B \fus_cu_busy_o$28 - connect \Y $985 + connect \B \fus_cu_busy_o$29 + connect \Y $1101 end - process $group_457 + process $group_485 assign \wrflag_ldst0_o_0 1'0 - assign \wrflag_ldst0_o_0 $985 + assign \wrflag_ldst0_o_0 $1101 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$987 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $988 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -113136,133 +221848,133 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $988 + connect \Y $1104 end - process $group_458 - assign \wr_pick$987 1'0 - assign \wr_pick$987 $988 + process $group_486 + assign \wr_pick$1103 1'0 + assign \wr_pick$1103 $1104 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$990 + wire width 1 \wr_pick_dly$1106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$990$next - process $group_459 - assign \wr_pick_dly$990$next \wr_pick_dly$990 - assign \wr_pick_dly$990$next \wr_pick$987 + wire width 1 \wr_pick_dly$1106$next + process $group_487 + assign \wr_pick_dly$1106$next \wr_pick_dly$1106 + assign \wr_pick_dly$1106$next \wr_pick$1103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$990$next 1'0 + assign \wr_pick_dly$1106$next 1'0 end sync init - update \wr_pick_dly$990 1'0 + update \wr_pick_dly$1106 1'0 sync posedge \coresync_clk - update \wr_pick_dly$990 \wr_pick_dly$990$next + update \wr_pick_dly$1106 \wr_pick_dly$1106$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$991 + wire width 1 \wr_pick_rise$1107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $992 + wire width 1 $1108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $993 + cell $not $1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$990 - connect \Y $992 + connect \A \wr_pick_dly$1106 + connect \Y $1108 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $994 + wire width 1 $1110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $995 + cell $and $1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$987 - connect \B $992 - connect \Y $994 + connect \A \wr_pick$1103 + connect \B $1108 + connect \Y $1110 end - process $group_460 - assign \wr_pick_rise$991 1'0 - assign \wr_pick_rise$991 $994 + process $group_488 + assign \wr_pick_rise$1107 1'0 + assign \wr_pick_rise$1107 $1110 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$996 - process $group_461 - assign \fus_cu_wr__go_i$102 2'00 - assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$991 - assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$996 + wire width 1 \wr_pick_rise$1112 + process $group_489 + assign \fus_cu_wr__go_i$105 2'00 + assign \fus_cu_wr__go_i$105 [0] \wr_pick_rise$1107 + assign \fus_cu_wr__go_i$105 [1] \wr_pick_rise$1112 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$997 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $998 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$987 + connect \A \wr_pick$1103 connect \B \wrpick_INT_o_en_o - connect \Y $998 + connect \Y $1114 end - process $group_462 - assign \wp$997 1'0 - assign \wp$997 $998 + process $group_490 + assign \wp$1113 1'0 + assign \wp$1113 $1114 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1118 parameter \WIDTH 5 connect \A 5'00000 - connect \B \rego - connect \S \wp$997 - connect \Y $1001 + connect \B \core_rego + connect \S \wp$1113 + connect \Y $1117 end - process $group_463 - assign \addr_en$1000 5'00000 - assign \addr_en$1000 $1001 + process $group_491 + assign \addr_en$1116 5'00000 + assign \addr_en$1116 $1117 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_ldst0_o_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1003 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ea_ok - connect \B \fus_cu_busy_o$28 - connect \Y $1003 + connect \B \fus_cu_busy_o$29 + connect \Y $1119 end - process $group_464 + process $group_492 assign \wrflag_ldst0_o_1 1'0 - assign \wrflag_ldst0_o_1 $1003 + assign \wrflag_ldst0_o_1 $1119 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1005 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1006 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -113270,166 +221982,166 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $1006 + connect \Y $1122 end - process $group_465 - assign \wr_pick$1005 1'0 - assign \wr_pick$1005 $1006 + process $group_493 + assign \wr_pick$1121 1'0 + assign \wr_pick$1121 $1122 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1008 + wire width 1 \wr_pick_dly$1124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1008$next - process $group_466 - assign \wr_pick_dly$1008$next \wr_pick_dly$1008 - assign \wr_pick_dly$1008$next \wr_pick$1005 + wire width 1 \wr_pick_dly$1124$next + process $group_494 + assign \wr_pick_dly$1124$next \wr_pick_dly$1124 + assign \wr_pick_dly$1124$next \wr_pick$1121 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1008$next 1'0 + assign \wr_pick_dly$1124$next 1'0 end sync init - update \wr_pick_dly$1008 1'0 + update \wr_pick_dly$1124 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1008 \wr_pick_dly$1008$next + update \wr_pick_dly$1124 \wr_pick_dly$1124$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1009 + wire width 1 $1125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1010 + cell $not $1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1008 - connect \Y $1009 + connect \A \wr_pick_dly$1124 + connect \Y $1125 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1011 + wire width 1 $1127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1012 + cell $and $1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1005 - connect \B $1009 - connect \Y $1011 + connect \A \wr_pick$1121 + connect \B $1125 + connect \Y $1127 end - process $group_467 - assign \wr_pick_rise$996 1'0 - assign \wr_pick_rise$996 $1011 + process $group_495 + assign \wr_pick_rise$1112 1'0 + assign \wr_pick_rise$1112 $1127 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1013 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1014 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1005 + connect \A \wr_pick$1121 connect \B \wrpick_INT_o_en_o - connect \Y $1014 + connect \Y $1130 end - process $group_468 - assign \wp$1013 1'0 - assign \wp$1013 $1014 + process $group_496 + assign \wp$1129 1'0 + assign \wp$1129 $1130 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 5 \addr_en$1016 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 5 $1017 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 5 \addr_en$1132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 5 $1133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1134 parameter \WIDTH 5 connect \A 5'00000 - connect \B \ea - connect \S \wp$1013 - connect \Y $1017 + connect \B \core_ea + connect \S \wp$1129 + connect \Y $1133 end - process $group_469 - assign \addr_en$1016 5'00000 - assign \addr_en$1016 $1017 + process $group_497 + assign \addr_en$1132 5'00000 + assign \addr_en$1132 $1133 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1019 + wire width 65 $1135 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1020 + wire width 64 $1136 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1021 + cell $or $1137 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o - connect \B \fus_dest1_o$103 - connect \Y $1020 + connect \B \fus_dest1_o$106 + connect \Y $1136 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1022 + wire width 64 $1138 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1023 + cell $or $1139 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$105 - connect \B \fus_dest1_o$106 - connect \Y $1022 + connect \A \fus_dest1_o$108 + connect \B \fus_dest1_o$109 + connect \Y $1138 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1024 + wire width 64 $1140 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1025 + cell $or $1141 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$104 - connect \B $1022 - connect \Y $1024 + connect \A \fus_dest1_o$107 + connect \B $1138 + connect \Y $1140 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1026 + wire width 64 $1142 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1027 + cell $or $1143 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $1020 - connect \B $1024 - connect \Y $1026 + connect \A $1136 + connect \B $1140 + connect \Y $1142 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1028 + wire width 64 $1144 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1029 + cell $or $1145 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$107 - connect \B \fus_dest1_o$108 - connect \Y $1028 + connect \A \fus_dest1_o$110 + connect \B \fus_dest1_o$111 + connect \Y $1144 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 65 $1030 + wire width 65 $1146 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1031 + cell $or $1147 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -113437,341 +222149,341 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $1030 + connect \Y $1146 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1032 + wire width 65 $1148 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1033 + cell $or $1149 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \fus_dest1_o$109 - connect \B $1030 - connect \Y $1032 + connect \A \fus_dest1_o$112 + connect \B $1146 + connect \Y $1148 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1034 + wire width 65 $1150 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1035 + cell $or $1151 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $1028 - connect \B $1032 - connect \Y $1034 + connect \A $1144 + connect \B $1148 + connect \Y $1150 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1036 + wire width 65 $1152 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1037 + cell $or $1153 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $1026 - connect \B $1034 - connect \Y $1036 + connect \A $1142 + connect \B $1150 + connect \Y $1152 end - connect $1019 $1036 - process $group_470 + connect $1135 $1152 + process $group_498 assign \int_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \int_dest1__data_i $1019 [63:0] + assign \int_dest1__data_i $1135 [63:0] sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1038 + wire width 5 $1154 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1039 + cell $or $1155 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \addr_en - connect \B \addr_en$861 - connect \Y $1038 + connect \B \addr_en$978 + connect \Y $1154 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1040 + wire width 5 $1156 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1041 + cell $or $1157 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$901 - connect \B \addr_en$923 - connect \Y $1040 + connect \A \addr_en$1017 + connect \B \addr_en$1039 + connect \Y $1156 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1042 + wire width 5 $1158 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1043 + cell $or $1159 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$882 - connect \B $1040 - connect \Y $1042 + connect \A \addr_en$999 + connect \B $1156 + connect \Y $1158 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1044 + wire width 5 $1160 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1045 + cell $or $1161 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $1038 - connect \B $1042 - connect \Y $1044 + connect \A $1154 + connect \B $1158 + connect \Y $1160 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1046 + wire width 5 $1162 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1047 + cell $or $1163 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$943 - connect \B \addr_en$963 - connect \Y $1046 + connect \A \addr_en$1059 + connect \B \addr_en$1079 + connect \Y $1162 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1048 + wire width 5 $1164 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1049 + cell $or $1165 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$1000 - connect \B \addr_en$1016 - connect \Y $1048 + connect \A \addr_en$1116 + connect \B \addr_en$1132 + connect \Y $1164 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1050 + wire width 5 $1166 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1051 + cell $or $1167 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$982 - connect \B $1048 - connect \Y $1050 + connect \A \addr_en$1098 + connect \B $1164 + connect \Y $1166 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1052 + wire width 5 $1168 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1053 + cell $or $1169 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $1046 - connect \B $1050 - connect \Y $1052 + connect \A $1162 + connect \B $1166 + connect \Y $1168 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1054 + wire width 5 $1170 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1055 + cell $or $1171 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $1044 - connect \B $1052 - connect \Y $1054 + connect \A $1160 + connect \B $1168 + connect \Y $1170 end - process $group_471 + process $group_499 assign \int_dest1__addr 5'00000 - assign \int_dest1__addr $1054 + assign \int_dest1__addr $1170 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1056 + wire width 1 $1172 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1057 + cell $or $1173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp - connect \B \wp$858 - connect \Y $1056 + connect \B \wp$975 + connect \Y $1172 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1058 + wire width 1 $1174 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1059 + cell $or $1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$898 - connect \B \wp$920 - connect \Y $1058 + connect \A \wp$1014 + connect \B \wp$1036 + connect \Y $1174 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1060 + wire width 1 $1176 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1061 + cell $or $1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$879 - connect \B $1058 - connect \Y $1060 + connect \A \wp$996 + connect \B $1174 + connect \Y $1176 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1062 + wire width 1 $1178 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1063 + cell $or $1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1056 - connect \B $1060 - connect \Y $1062 + connect \A $1172 + connect \B $1176 + connect \Y $1178 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1064 + wire width 1 $1180 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1065 + cell $or $1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$940 - connect \B \wp$960 - connect \Y $1064 + connect \A \wp$1056 + connect \B \wp$1076 + connect \Y $1180 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1066 + wire width 1 $1182 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1067 + cell $or $1183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$997 - connect \B \wp$1013 - connect \Y $1066 + connect \A \wp$1113 + connect \B \wp$1129 + connect \Y $1182 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1068 + wire width 1 $1184 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1069 + cell $or $1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$979 - connect \B $1066 - connect \Y $1068 + connect \A \wp$1095 + connect \B $1182 + connect \Y $1184 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1070 + wire width 1 $1186 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1071 + cell $or $1187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1064 - connect \B $1068 - connect \Y $1070 + connect \A $1180 + connect \B $1184 + connect \Y $1186 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1072 + wire width 1 $1188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1073 + cell $or $1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1062 - connect \B $1070 - connect \Y $1072 + connect \A $1178 + connect \B $1186 + connect \Y $1188 end - process $group_472 + process $group_500 assign \int_dest1__wen 1'0 - assign \int_dest1__wen $1072 + assign \int_dest1__wen $1188 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1074 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok - connect \B \fus_cu_busy_o$4 - connect \Y $1074 + connect \B \fus_cu_busy_o$5 + connect \Y $1190 end - process $group_473 + process $group_501 assign \wrflag_cr0_full_cr_1 1'0 - assign \wrflag_cr0_full_cr_1 $1074 + assign \wrflag_cr0_full_cr_1 $1190 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1076 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$81 [1] + connect \A \fus_cu_wr__rel_o$84 [1] connect \B \fu_enable [1] - connect \Y $1076 + connect \Y $1192 end - process $group_474 + process $group_502 assign \wrpick_CR_full_cr_i 1'0 - assign \wrpick_CR_full_cr_i $1076 + assign \wrpick_CR_full_cr_i $1192 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1078 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1079 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -113779,111 +222491,111 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $1079 + connect \Y $1195 end - process $group_475 - assign \wr_pick$1078 1'0 - assign \wr_pick$1078 $1079 + process $group_503 + assign \wr_pick$1194 1'0 + assign \wr_pick$1194 $1195 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1081 + wire width 1 \wr_pick_dly$1197 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1081$next - process $group_476 - assign \wr_pick_dly$1081$next \wr_pick_dly$1081 - assign \wr_pick_dly$1081$next \wr_pick$1078 + wire width 1 \wr_pick_dly$1197$next + process $group_504 + assign \wr_pick_dly$1197$next \wr_pick_dly$1197 + assign \wr_pick_dly$1197$next \wr_pick$1194 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1081$next 1'0 + assign \wr_pick_dly$1197$next 1'0 end sync init - update \wr_pick_dly$1081 1'0 + update \wr_pick_dly$1197 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1081 \wr_pick_dly$1081$next + update \wr_pick_dly$1197 \wr_pick_dly$1197$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1082 + wire width 1 $1198 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1083 + cell $not $1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1081 - connect \Y $1082 + connect \A \wr_pick_dly$1197 + connect \Y $1198 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1084 + wire width 1 $1200 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1085 + cell $and $1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1078 - connect \B $1082 - connect \Y $1084 + connect \A \wr_pick$1194 + connect \B $1198 + connect \Y $1200 end - process $group_477 - assign \wr_pick_rise$856 1'0 - assign \wr_pick_rise$856 $1084 + process $group_505 + assign \wr_pick_rise$973 1'0 + assign \wr_pick_rise$973 $1200 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1086 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1087 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1078 + connect \A \wr_pick$1194 connect \B \wrpick_CR_full_cr_en_o - connect \Y $1087 + connect \Y $1203 end - process $group_478 - assign \wp$1086 1'0 - assign \wp$1086 $1087 + process $group_506 + assign \wp$1202 1'0 + assign \wp$1202 $1203 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 8 \addr_en$1089 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 8 $1090 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 8 \addr_en$1205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 8 $1206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1207 parameter \WIDTH 8 connect \A 8'00000000 - connect \B 8'11111111 - connect \S \wp$1086 - connect \Y $1090 + connect \B \core_core_cr_wr + connect \S \wp$1202 + connect \Y $1206 end - process $group_479 - assign \addr_en$1089 8'00000000 - assign \addr_en$1089 $1090 + process $group_507 + assign \addr_en$1205 8'00000000 + assign \addr_en$1205 $1206 sync init end - process $group_480 + process $group_508 assign \cr_full_wr__data_i 32'00000000000000000000000000000000 assign \cr_full_wr__data_i \fus_dest2_o sync init end - process $group_481 + process $group_509 assign \cr_full_wr__wen 8'00000000 - assign \cr_full_wr__wen \addr_en$1089 + assign \cr_full_wr__wen \addr_en$1205 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1092 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1093 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -113891,17 +222603,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $1092 + connect \Y $1208 end - process $group_482 + process $group_510 assign \wrflag_alu0_cr_a_1 1'0 - assign \wrflag_alu0_cr_a_1 $1092 + assign \wrflag_alu0_cr_a_1 $1208 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1094 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1095 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -113909,89 +222621,89 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $1094 + connect \Y $1210 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1096 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1097 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$81 [2] + connect \A \fus_cu_wr__rel_o$84 [2] connect \B \fu_enable [1] - connect \Y $1096 + connect \Y $1212 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1099 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [1] + connect \A \fus_cu_wr__rel_o$90 [1] connect \B \fu_enable [4] - connect \Y $1098 + connect \Y $1214 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [1] + connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [6] - connect \Y $1100 + connect \Y $1216 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [1] + connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [7] - connect \Y $1102 + connect \Y $1218 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [1] + connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [8] - connect \Y $1104 + connect \Y $1220 end - process $group_483 + process $group_511 assign \wrpick_CR_cr_a_i 6'000000 - assign \wrpick_CR_cr_a_i [0] $1094 - assign \wrpick_CR_cr_a_i [1] $1096 - assign \wrpick_CR_cr_a_i [2] $1098 - assign \wrpick_CR_cr_a_i [3] $1100 - assign \wrpick_CR_cr_a_i [4] $1102 - assign \wrpick_CR_cr_a_i [5] $1104 + assign \wrpick_CR_cr_a_i [0] $1210 + assign \wrpick_CR_cr_a_i [1] $1212 + assign \wrpick_CR_cr_a_i [2] $1214 + assign \wrpick_CR_cr_a_i [3] $1216 + assign \wrpick_CR_cr_a_i [4] $1218 + assign \wrpick_CR_cr_a_i [5] $1220 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -113999,147 +222711,147 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1107 + connect \Y $1223 end - process $group_484 - assign \wr_pick$1106 1'0 - assign \wr_pick$1106 $1107 + process $group_512 + assign \wr_pick$1222 1'0 + assign \wr_pick$1222 $1223 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1109 + wire width 1 \wr_pick_dly$1225 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1109$next - process $group_485 - assign \wr_pick_dly$1109$next \wr_pick_dly$1109 - assign \wr_pick_dly$1109$next \wr_pick$1106 + wire width 1 \wr_pick_dly$1225$next + process $group_513 + assign \wr_pick_dly$1225$next \wr_pick_dly$1225 + assign \wr_pick_dly$1225$next \wr_pick$1222 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1109$next 1'0 + assign \wr_pick_dly$1225$next 1'0 end sync init - update \wr_pick_dly$1109 1'0 + update \wr_pick_dly$1225 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1109 \wr_pick_dly$1109$next + update \wr_pick_dly$1225 \wr_pick_dly$1225$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1110 + wire width 1 $1226 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1111 + cell $not $1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1109 - connect \Y $1110 + connect \A \wr_pick_dly$1225 + connect \Y $1226 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1112 + wire width 1 $1228 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1113 + cell $and $1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1106 - connect \B $1110 - connect \Y $1112 + connect \A \wr_pick$1222 + connect \B $1226 + connect \Y $1228 end - process $group_486 - assign \wr_pick_rise$837 1'0 - assign \wr_pick_rise$837 $1112 + process $group_514 + assign \wr_pick_rise$954 1'0 + assign \wr_pick_rise$954 $1228 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1106 + connect \A \wr_pick$1222 connect \B \wrpick_CR_cr_a_en_o - connect \Y $1115 + connect \Y $1231 end - process $group_487 - assign \wp$1114 1'0 - assign \wp$1114 $1115 + process $group_515 + assign \wp$1230 1'0 + assign \wp$1230 $1231 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 16 \addr_en$1117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 4 $1118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sub $1119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 16 \addr_en$1233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 $1234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $1235 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_out - connect \Y $1118 + connect \B \core_cr_out + connect \Y $1234 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 16 $1120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sshl $1121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 $1236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $1118 - connect \Y $1120 + connect \B $1234 + connect \Y $1236 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 16 $1122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 16 $1238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1239 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $1120 - connect \S \wp$1114 - connect \Y $1122 + connect \B $1236 + connect \S \wp$1230 + connect \Y $1238 end - process $group_488 - assign \addr_en$1117 16'0000000000000000 - assign \addr_en$1117 $1122 + process $group_516 + assign \addr_en$1233 16'0000000000000000 + assign \addr_en$1233 $1238 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$110 - connect \B \fus_cu_busy_o$4 - connect \Y $1124 + connect \A \fus_cr_a_ok$113 + connect \B \fus_cu_busy_o$5 + connect \Y $1240 end - process $group_489 + process $group_517 assign \wrflag_cr0_cr_a_2 1'0 - assign \wrflag_cr0_cr_a_2 $1124 + assign \wrflag_cr0_cr_a_2 $1240 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -114147,147 +222859,147 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1127 + connect \Y $1243 end - process $group_490 - assign \wr_pick$1126 1'0 - assign \wr_pick$1126 $1127 + process $group_518 + assign \wr_pick$1242 1'0 + assign \wr_pick$1242 $1243 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1129 + wire width 1 \wr_pick_dly$1245 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1129$next - process $group_491 - assign \wr_pick_dly$1129$next \wr_pick_dly$1129 - assign \wr_pick_dly$1129$next \wr_pick$1126 + wire width 1 \wr_pick_dly$1245$next + process $group_519 + assign \wr_pick_dly$1245$next \wr_pick_dly$1245 + assign \wr_pick_dly$1245$next \wr_pick$1242 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1129$next 1'0 + assign \wr_pick_dly$1245$next 1'0 end sync init - update \wr_pick_dly$1129 1'0 + update \wr_pick_dly$1245 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1129 \wr_pick_dly$1129$next + update \wr_pick_dly$1245 \wr_pick_dly$1245$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1130 + wire width 1 $1246 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1131 + cell $not $1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1129 - connect \Y $1130 + connect \A \wr_pick_dly$1245 + connect \Y $1246 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1132 + wire width 1 $1248 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1133 + cell $and $1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1126 - connect \B $1130 - connect \Y $1132 + connect \A \wr_pick$1242 + connect \B $1246 + connect \Y $1248 end - process $group_492 - assign \wr_pick_rise$857 1'0 - assign \wr_pick_rise$857 $1132 + process $group_520 + assign \wr_pick_rise$974 1'0 + assign \wr_pick_rise$974 $1248 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1126 + connect \A \wr_pick$1242 connect \B \wrpick_CR_cr_a_en_o - connect \Y $1135 + connect \Y $1251 end - process $group_493 - assign \wp$1134 1'0 - assign \wp$1134 $1135 + process $group_521 + assign \wp$1250 1'0 + assign \wp$1250 $1251 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 16 \addr_en$1137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 4 $1138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sub $1139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 16 \addr_en$1253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 $1254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $1255 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_out - connect \Y $1138 + connect \B \core_cr_out + connect \Y $1254 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 16 $1140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sshl $1141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 $1256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $1138 - connect \Y $1140 + connect \B $1254 + connect \Y $1256 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 16 $1142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 16 $1258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1259 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $1140 - connect \S \wp$1134 - connect \Y $1142 + connect \B $1256 + connect \S \wp$1250 + connect \Y $1258 end - process $group_494 - assign \addr_en$1137 16'0000000000000000 - assign \addr_en$1137 $1142 + process $group_522 + assign \addr_en$1253 16'0000000000000000 + assign \addr_en$1253 $1258 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$111 - connect \B \fus_cu_busy_o$13 - connect \Y $1144 + connect \A \fus_cr_a_ok$114 + connect \B \fus_cu_busy_o$14 + connect \Y $1260 end - process $group_495 + process $group_523 assign \wrflag_logical0_cr_a_1 1'0 - assign \wrflag_logical0_cr_a_1 $1144 + assign \wrflag_logical0_cr_a_1 $1260 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -114295,147 +223007,147 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1147 + connect \Y $1263 end - process $group_496 - assign \wr_pick$1146 1'0 - assign \wr_pick$1146 $1147 + process $group_524 + assign \wr_pick$1262 1'0 + assign \wr_pick$1262 $1263 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1149 + wire width 1 \wr_pick_dly$1265 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1149$next - process $group_497 - assign \wr_pick_dly$1149$next \wr_pick_dly$1149 - assign \wr_pick_dly$1149$next \wr_pick$1146 + wire width 1 \wr_pick_dly$1265$next + process $group_525 + assign \wr_pick_dly$1265$next \wr_pick_dly$1265 + assign \wr_pick_dly$1265$next \wr_pick$1262 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1149$next 1'0 + assign \wr_pick_dly$1265$next 1'0 end sync init - update \wr_pick_dly$1149 1'0 + update \wr_pick_dly$1265 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1149 \wr_pick_dly$1149$next + update \wr_pick_dly$1265 \wr_pick_dly$1265$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1150 + wire width 1 $1266 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1151 + cell $not $1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1149 - connect \Y $1150 + connect \A \wr_pick_dly$1265 + connect \Y $1266 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1152 + wire width 1 $1268 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1153 + cell $and $1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1146 - connect \B $1150 - connect \Y $1152 + connect \A \wr_pick$1262 + connect \B $1266 + connect \Y $1268 end - process $group_498 - assign \wr_pick_rise$896 1'0 - assign \wr_pick_rise$896 $1152 + process $group_526 + assign \wr_pick_rise$1013 1'0 + assign \wr_pick_rise$1013 $1268 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1146 + connect \A \wr_pick$1262 connect \B \wrpick_CR_cr_a_en_o - connect \Y $1155 + connect \Y $1271 end - process $group_499 - assign \wp$1154 1'0 - assign \wp$1154 $1155 + process $group_527 + assign \wp$1270 1'0 + assign \wp$1270 $1271 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 16 \addr_en$1157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 4 $1158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sub $1159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 16 \addr_en$1273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 $1274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $1275 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_out - connect \Y $1158 + connect \B \core_cr_out + connect \Y $1274 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 16 $1160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sshl $1161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 $1276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $1277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $1158 - connect \Y $1160 + connect \B $1274 + connect \Y $1276 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 16 $1162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 16 $1278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1279 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $1160 - connect \S \wp$1154 - connect \Y $1162 + connect \B $1276 + connect \S \wp$1270 + connect \Y $1278 end - process $group_500 - assign \addr_en$1157 16'0000000000000000 - assign \addr_en$1157 $1162 + process $group_528 + assign \addr_en$1273 16'0000000000000000 + assign \addr_en$1273 $1278 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$112 - connect \B \fus_cu_busy_o$19 - connect \Y $1164 + connect \A \fus_cr_a_ok$115 + connect \B \fus_cu_busy_o$20 + connect \Y $1280 end - process $group_501 + process $group_529 assign \wrflag_div0_cr_a_1 1'0 - assign \wrflag_div0_cr_a_1 $1164 + assign \wrflag_div0_cr_a_1 $1280 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -114443,147 +223155,147 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1167 + connect \Y $1283 end - process $group_502 - assign \wr_pick$1166 1'0 - assign \wr_pick$1166 $1167 + process $group_530 + assign \wr_pick$1282 1'0 + assign \wr_pick$1282 $1283 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1169 + wire width 1 \wr_pick_dly$1285 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1169$next - process $group_503 - assign \wr_pick_dly$1169$next \wr_pick_dly$1169 - assign \wr_pick_dly$1169$next \wr_pick$1166 + wire width 1 \wr_pick_dly$1285$next + process $group_531 + assign \wr_pick_dly$1285$next \wr_pick_dly$1285 + assign \wr_pick_dly$1285$next \wr_pick$1282 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1169$next 1'0 + assign \wr_pick_dly$1285$next 1'0 end sync init - update \wr_pick_dly$1169 1'0 + update \wr_pick_dly$1285 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1169 \wr_pick_dly$1169$next + update \wr_pick_dly$1285 \wr_pick_dly$1285$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1170 + wire width 1 $1286 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1171 + cell $not $1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1169 - connect \Y $1170 + connect \A \wr_pick_dly$1285 + connect \Y $1286 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1172 + wire width 1 $1288 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1173 + cell $and $1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1166 - connect \B $1170 - connect \Y $1172 + connect \A \wr_pick$1282 + connect \B $1286 + connect \Y $1288 end - process $group_504 - assign \wr_pick_rise$937 1'0 - assign \wr_pick_rise$937 $1172 + process $group_532 + assign \wr_pick_rise$1053 1'0 + assign \wr_pick_rise$1053 $1288 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1166 + connect \A \wr_pick$1282 connect \B \wrpick_CR_cr_a_en_o - connect \Y $1175 + connect \Y $1291 end - process $group_505 - assign \wp$1174 1'0 - assign \wp$1174 $1175 + process $group_533 + assign \wp$1290 1'0 + assign \wp$1290 $1291 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 16 \addr_en$1177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 4 $1178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sub $1179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 16 \addr_en$1293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 $1294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $1295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_out - connect \Y $1178 + connect \B \core_cr_out + connect \Y $1294 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 16 $1180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sshl $1181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 $1296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $1178 - connect \Y $1180 + connect \B $1294 + connect \Y $1296 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 16 $1182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 16 $1298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1299 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $1180 - connect \S \wp$1174 - connect \Y $1182 + connect \B $1296 + connect \S \wp$1290 + connect \Y $1298 end - process $group_506 - assign \addr_en$1177 16'0000000000000000 - assign \addr_en$1177 $1182 + process $group_534 + assign \addr_en$1293 16'0000000000000000 + assign \addr_en$1293 $1298 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$113 - connect \B \fus_cu_busy_o$22 - connect \Y $1184 + connect \A \fus_cr_a_ok$116 + connect \B \fus_cu_busy_o$23 + connect \Y $1300 end - process $group_507 + process $group_535 assign \wrflag_mul0_cr_a_1 1'0 - assign \wrflag_mul0_cr_a_1 $1184 + assign \wrflag_mul0_cr_a_1 $1300 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -114591,147 +223303,147 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1187 + connect \Y $1303 end - process $group_508 - assign \wr_pick$1186 1'0 - assign \wr_pick$1186 $1187 + process $group_536 + assign \wr_pick$1302 1'0 + assign \wr_pick$1302 $1303 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1189 + wire width 1 \wr_pick_dly$1305 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1189$next - process $group_509 - assign \wr_pick_dly$1189$next \wr_pick_dly$1189 - assign \wr_pick_dly$1189$next \wr_pick$1186 + wire width 1 \wr_pick_dly$1305$next + process $group_537 + assign \wr_pick_dly$1305$next \wr_pick_dly$1305 + assign \wr_pick_dly$1305$next \wr_pick$1302 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1189$next 1'0 + assign \wr_pick_dly$1305$next 1'0 end sync init - update \wr_pick_dly$1189 1'0 + update \wr_pick_dly$1305 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1189 \wr_pick_dly$1189$next + update \wr_pick_dly$1305 \wr_pick_dly$1305$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1190 + wire width 1 $1306 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1191 + cell $not $1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1189 - connect \Y $1190 + connect \A \wr_pick_dly$1305 + connect \Y $1306 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1192 + wire width 1 $1308 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1193 + cell $and $1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1186 - connect \B $1190 - connect \Y $1192 + connect \A \wr_pick$1302 + connect \B $1306 + connect \Y $1308 end - process $group_510 - assign \wr_pick_rise$957 1'0 - assign \wr_pick_rise$957 $1192 + process $group_538 + assign \wr_pick_rise$1073 1'0 + assign \wr_pick_rise$1073 $1308 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1186 + connect \A \wr_pick$1302 connect \B \wrpick_CR_cr_a_en_o - connect \Y $1195 + connect \Y $1311 end - process $group_511 - assign \wp$1194 1'0 - assign \wp$1194 $1195 + process $group_539 + assign \wp$1310 1'0 + assign \wp$1310 $1311 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 16 \addr_en$1197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 4 $1198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sub $1199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 16 \addr_en$1313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 $1314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $1315 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_out - connect \Y $1198 + connect \B \core_cr_out + connect \Y $1314 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 16 $1200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sshl $1201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 $1316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $1198 - connect \Y $1200 + connect \B $1314 + connect \Y $1316 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 16 $1202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 16 $1318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1319 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $1200 - connect \S \wp$1194 - connect \Y $1202 + connect \B $1316 + connect \S \wp$1310 + connect \Y $1318 end - process $group_512 - assign \addr_en$1197 16'0000000000000000 - assign \addr_en$1197 $1202 + process $group_540 + assign \addr_en$1313 16'0000000000000000 + assign \addr_en$1313 $1318 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$114 - connect \B \fus_cu_busy_o$25 - connect \Y $1204 + connect \A \fus_cr_a_ok$117 + connect \B \fus_cu_busy_o$26 + connect \Y $1320 end - process $group_513 + process $group_541 assign \wrflag_shiftrot0_cr_a_1 1'0 - assign \wrflag_shiftrot0_cr_a_1 $1204 + assign \wrflag_shiftrot0_cr_a_1 $1320 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -114739,270 +223451,270 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $1207 + connect \Y $1323 end - process $group_514 - assign \wr_pick$1206 1'0 - assign \wr_pick$1206 $1207 + process $group_542 + assign \wr_pick$1322 1'0 + assign \wr_pick$1322 $1323 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1209 + wire width 1 \wr_pick_dly$1325 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1209$next - process $group_515 - assign \wr_pick_dly$1209$next \wr_pick_dly$1209 - assign \wr_pick_dly$1209$next \wr_pick$1206 + wire width 1 \wr_pick_dly$1325$next + process $group_543 + assign \wr_pick_dly$1325$next \wr_pick_dly$1325 + assign \wr_pick_dly$1325$next \wr_pick$1322 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1209$next 1'0 + assign \wr_pick_dly$1325$next 1'0 end sync init - update \wr_pick_dly$1209 1'0 + update \wr_pick_dly$1325 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1209 \wr_pick_dly$1209$next + update \wr_pick_dly$1325 \wr_pick_dly$1325$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1210 + wire width 1 $1326 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1211 + cell $not $1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1209 - connect \Y $1210 + connect \A \wr_pick_dly$1325 + connect \Y $1326 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1212 + wire width 1 $1328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1213 + cell $and $1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1206 - connect \B $1210 - connect \Y $1212 + connect \A \wr_pick$1322 + connect \B $1326 + connect \Y $1328 end - process $group_516 - assign \wr_pick_rise$977 1'0 - assign \wr_pick_rise$977 $1212 + process $group_544 + assign \wr_pick_rise$1093 1'0 + assign \wr_pick_rise$1093 $1328 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1206 + connect \A \wr_pick$1322 connect \B \wrpick_CR_cr_a_en_o - connect \Y $1215 + connect \Y $1331 end - process $group_517 - assign \wp$1214 1'0 - assign \wp$1214 $1215 + process $group_545 + assign \wp$1330 1'0 + assign \wp$1330 $1331 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 16 \addr_en$1217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 4 $1218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sub $1219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 16 \addr_en$1333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 $1334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $1335 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_out - connect \Y $1218 + connect \B \core_cr_out + connect \Y $1334 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - wire width 16 $1220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" - cell $sshl $1221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 $1336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $1218 - connect \Y $1220 + connect \B $1334 + connect \Y $1336 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 16 $1222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 16 $1338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1339 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B $1220 - connect \S \wp$1214 - connect \Y $1222 + connect \B $1336 + connect \S \wp$1330 + connect \Y $1338 end - process $group_518 - assign \addr_en$1217 16'0000000000000000 - assign \addr_en$1217 $1222 + process $group_546 + assign \addr_en$1333 16'0000000000000000 + assign \addr_en$1333 $1338 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1224 + wire width 4 $1340 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1225 + cell $or $1341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest3_o - connect \B \fus_dest2_o$116 - connect \Y $1224 + connect \B \fus_dest2_o$119 + connect \Y $1340 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1226 + wire width 4 $1342 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1227 + cell $or $1343 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$115 - connect \B $1224 - connect \Y $1226 + connect \A \fus_dest2_o$118 + connect \B $1340 + connect \Y $1342 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1228 + wire width 4 $1344 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1229 + cell $or $1345 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$118 - connect \B \fus_dest2_o$119 - connect \Y $1228 + connect \A \fus_dest2_o$121 + connect \B \fus_dest2_o$122 + connect \Y $1344 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1230 + wire width 4 $1346 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1231 + cell $or $1347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$117 - connect \B $1228 - connect \Y $1230 + connect \A \fus_dest2_o$120 + connect \B $1344 + connect \Y $1346 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1232 + wire width 4 $1348 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1233 + cell $or $1349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $1226 - connect \B $1230 - connect \Y $1232 + connect \A $1342 + connect \B $1346 + connect \Y $1348 end - process $group_519 + process $group_547 assign \cr_data_i 4'0000 - assign \cr_data_i $1232 + assign \cr_data_i $1348 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1234 + wire width 16 $1350 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $1235 + wire width 16 $1351 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1236 + cell $or $1352 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1137 - connect \B \addr_en$1157 - connect \Y $1235 + connect \A \addr_en$1253 + connect \B \addr_en$1273 + connect \Y $1351 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1237 + wire width 16 $1353 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1238 + cell $or $1354 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1117 - connect \B $1235 - connect \Y $1237 + connect \A \addr_en$1233 + connect \B $1351 + connect \Y $1353 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $1239 + wire width 16 $1355 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1240 + cell $or $1356 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1197 - connect \B \addr_en$1217 - connect \Y $1239 + connect \A \addr_en$1313 + connect \B \addr_en$1333 + connect \Y $1355 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1241 + wire width 16 $1357 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1242 + cell $or $1358 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1177 - connect \B $1239 - connect \Y $1241 + connect \A \addr_en$1293 + connect \B $1355 + connect \Y $1357 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1243 + wire width 16 $1359 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1244 + cell $or $1360 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A $1237 - connect \B $1241 - connect \Y $1243 + connect \A $1353 + connect \B $1357 + connect \Y $1359 end - connect $1234 $1243 - process $group_520 + connect $1350 $1359 + process $group_548 assign \cr_wen 8'00000000 - assign \cr_wen $1234 [7:0] + assign \cr_wen $1350 [7:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115010,17 +223722,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $1245 + connect \Y $1361 end - process $group_521 + process $group_549 assign \wrflag_alu0_xer_ca_2 1'0 - assign \wrflag_alu0_xer_ca_2 $1245 + assign \wrflag_alu0_xer_ca_2 $1361 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115028,61 +223740,47 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $1247 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [2] - connect \B \fu_enable [4] - connect \Y $1249 + connect \Y $1363 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [5] + connect \A \fus_cu_wr__rel_o$93 [5] connect \B \fu_enable [5] - connect \Y $1251 + connect \Y $1365 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [2] + connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [8] - connect \Y $1253 + connect \Y $1367 end - process $group_522 - assign \wrpick_XER_xer_ca_i 4'0000 - assign \wrpick_XER_xer_ca_i [0] $1247 - assign \wrpick_XER_xer_ca_i [1] $1249 - assign \wrpick_XER_xer_ca_i [2] $1251 - assign \wrpick_XER_xer_ca_i [3] $1253 + process $group_550 + assign \wrpick_XER_xer_ca_i 3'000 + assign \wrpick_XER_xer_ca_i [0] $1363 + assign \wrpick_XER_xer_ca_i [1] $1365 + assign \wrpick_XER_xer_ca_i [2] $1367 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115090,565 +223788,417 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1256 - end - process $group_523 - assign \wr_pick$1255 1'0 - assign \wr_pick$1255 $1256 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1258 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1258$next - process $group_524 - assign \wr_pick_dly$1258$next \wr_pick_dly$1258 - assign \wr_pick_dly$1258$next \wr_pick$1255 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1258$next 1'0 - end - sync init - update \wr_pick_dly$1258 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1258 \wr_pick_dly$1258$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1259 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1258 - connect \Y $1259 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1261 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1255 - connect \B $1259 - connect \Y $1261 - end - process $group_525 - assign \wr_pick_rise$838 1'0 - assign \wr_pick_rise$838 $1261 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1255 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1264 - end - process $group_526 - assign \wp$1263 1'0 - assign \wp$1263 $1264 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 2 \addr_en$1266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 2 $1267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1268 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1263 - connect \Y $1267 - end - process $group_527 - assign \addr_en$1266 2'00 - assign \addr_en$1266 $1267 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" - wire width 1 \wrflag_logical0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1269 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$120 - connect \B \fus_cu_busy_o$13 - connect \Y $1269 - end - process $group_528 - assign \wrflag_logical0_xer_ca_2 1'0 - assign \wrflag_logical0_xer_ca_2 $1269 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [1] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1272 + connect \Y $1370 end - process $group_529 - assign \wr_pick$1271 1'0 - assign \wr_pick$1271 $1272 + process $group_551 + assign \wr_pick$1369 1'0 + assign \wr_pick$1369 $1370 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1274 + wire width 1 \wr_pick_dly$1372 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1274$next - process $group_530 - assign \wr_pick_dly$1274$next \wr_pick_dly$1274 - assign \wr_pick_dly$1274$next \wr_pick$1271 + wire width 1 \wr_pick_dly$1372$next + process $group_552 + assign \wr_pick_dly$1372$next \wr_pick_dly$1372 + assign \wr_pick_dly$1372$next \wr_pick$1369 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1274$next 1'0 + assign \wr_pick_dly$1372$next 1'0 end sync init - update \wr_pick_dly$1274 1'0 + update \wr_pick_dly$1372 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1274 \wr_pick_dly$1274$next + update \wr_pick_dly$1372 \wr_pick_dly$1372$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1275 + wire width 1 $1373 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1276 + cell $not $1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1274 - connect \Y $1275 + connect \A \wr_pick_dly$1372 + connect \Y $1373 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1277 + wire width 1 $1375 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1278 + cell $and $1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1271 - connect \B $1275 - connect \Y $1277 + connect \A \wr_pick$1369 + connect \B $1373 + connect \Y $1375 end - process $group_531 - assign \wr_pick_rise$897 1'0 - assign \wr_pick_rise$897 $1277 + process $group_553 + assign \wr_pick_rise$955 1'0 + assign \wr_pick_rise$955 $1375 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1279 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1271 + connect \A \wr_pick$1369 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1280 + connect \Y $1378 end - process $group_532 - assign \wp$1279 1'0 - assign \wp$1279 $1280 + process $group_554 + assign \wp$1377 1'0 + assign \wp$1377 $1378 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 2 \addr_en$1282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 2 $1283 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 2 \addr_en$1380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 2 $1381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1382 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1279 - connect \Y $1283 + connect \S \wp$1377 + connect \Y $1381 end - process $group_533 - assign \addr_en$1282 2'00 - assign \addr_en$1282 $1283 + process $group_555 + assign \addr_en$1380 2'00 + assign \addr_en$1380 $1381 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$121 - connect \B \fus_cu_busy_o$16 - connect \Y $1285 + connect \A \fus_xer_ca_ok$123 + connect \B \fus_cu_busy_o$17 + connect \Y $1383 end - process $group_534 + process $group_556 assign \wrflag_spr0_xer_ca_5 1'0 - assign \wrflag_spr0_xer_ca_5 $1285 + assign \wrflag_spr0_xer_ca_5 $1383 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1287 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1288 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [2] + connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1288 + connect \Y $1386 end - process $group_535 - assign \wr_pick$1287 1'0 - assign \wr_pick$1287 $1288 + process $group_557 + assign \wr_pick$1385 1'0 + assign \wr_pick$1385 $1386 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1290 + wire width 1 \wr_pick_dly$1388 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1290$next - process $group_536 - assign \wr_pick_dly$1290$next \wr_pick_dly$1290 - assign \wr_pick_dly$1290$next \wr_pick$1287 + wire width 1 \wr_pick_dly$1388$next + process $group_558 + assign \wr_pick_dly$1388$next \wr_pick_dly$1388 + assign \wr_pick_dly$1388$next \wr_pick$1385 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1290$next 1'0 + assign \wr_pick_dly$1388$next 1'0 end sync init - update \wr_pick_dly$1290 1'0 + update \wr_pick_dly$1388 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1290 \wr_pick_dly$1290$next + update \wr_pick_dly$1388 \wr_pick_dly$1388$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1291 + wire width 1 $1389 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1292 + cell $not $1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1290 - connect \Y $1291 + connect \A \wr_pick_dly$1388 + connect \Y $1389 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1293 + wire width 1 $1391 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1294 + cell $and $1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1287 - connect \B $1291 - connect \Y $1293 + connect \A \wr_pick$1385 + connect \B $1389 + connect \Y $1391 end - process $group_537 - assign \wr_pick_rise$915 1'0 - assign \wr_pick_rise$915 $1293 + process $group_559 + assign \wr_pick_rise$1031 1'0 + assign \wr_pick_rise$1031 $1391 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1295 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1287 + connect \A \wr_pick$1385 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1296 + connect \Y $1394 end - process $group_538 - assign \wp$1295 1'0 - assign \wp$1295 $1296 + process $group_560 + assign \wp$1393 1'0 + assign \wp$1393 $1394 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 2 \addr_en$1298 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 2 $1299 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 2 \addr_en$1396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 2 $1397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1398 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1295 - connect \Y $1299 + connect \S \wp$1393 + connect \Y $1397 end - process $group_539 - assign \addr_en$1298 2'00 - assign \addr_en$1298 $1299 + process $group_561 + assign \addr_en$1396 2'00 + assign \addr_en$1396 $1397 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1301 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$122 - connect \B \fus_cu_busy_o$25 - connect \Y $1301 + connect \A \fus_xer_ca_ok$124 + connect \B \fus_cu_busy_o$26 + connect \Y $1399 end - process $group_540 + process $group_562 assign \wrflag_shiftrot0_xer_ca_2 1'0 - assign \wrflag_shiftrot0_xer_ca_2 $1301 + assign \wrflag_shiftrot0_xer_ca_2 $1399 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1303 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [3] + connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1304 + connect \Y $1402 end - process $group_541 - assign \wr_pick$1303 1'0 - assign \wr_pick$1303 $1304 + process $group_563 + assign \wr_pick$1401 1'0 + assign \wr_pick$1401 $1402 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1306 + wire width 1 \wr_pick_dly$1404 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1306$next - process $group_542 - assign \wr_pick_dly$1306$next \wr_pick_dly$1306 - assign \wr_pick_dly$1306$next \wr_pick$1303 + wire width 1 \wr_pick_dly$1404$next + process $group_564 + assign \wr_pick_dly$1404$next \wr_pick_dly$1404 + assign \wr_pick_dly$1404$next \wr_pick$1401 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1306$next 1'0 + assign \wr_pick_dly$1404$next 1'0 end sync init - update \wr_pick_dly$1306 1'0 + update \wr_pick_dly$1404 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1306 \wr_pick_dly$1306$next + update \wr_pick_dly$1404 \wr_pick_dly$1404$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1307 + wire width 1 $1405 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1308 + cell $not $1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1306 - connect \Y $1307 + connect \A \wr_pick_dly$1404 + connect \Y $1405 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1309 + wire width 1 $1407 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1310 + cell $and $1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1303 - connect \B $1307 - connect \Y $1309 + connect \A \wr_pick$1401 + connect \B $1405 + connect \Y $1407 end - process $group_543 - assign \wr_pick_rise$978 1'0 - assign \wr_pick_rise$978 $1309 + process $group_565 + assign \wr_pick_rise$1094 1'0 + assign \wr_pick_rise$1094 $1407 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1303 + connect \A \wr_pick$1401 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1312 + connect \Y $1410 end - process $group_544 - assign \wp$1311 1'0 - assign \wp$1311 $1312 + process $group_566 + assign \wp$1409 1'0 + assign \wp$1409 $1410 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 2 \addr_en$1314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 2 $1315 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 2 \addr_en$1412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 2 $1413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1414 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1311 - connect \Y $1315 + connect \S \wp$1409 + connect \Y $1413 end - process $group_545 - assign \addr_en$1314 2'00 - assign \addr_en$1314 $1315 + process $group_567 + assign \addr_en$1412 2'00 + assign \addr_en$1412 $1413 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1317 + wire width 2 $1415 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$123 - connect \B \fus_dest3_o$124 - connect \Y $1317 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1319 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1320 + cell $or $1416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest6_o - connect \B \fus_dest3_o$125 - connect \Y $1319 + connect \B \fus_dest3_o$126 + connect \Y $1415 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1321 + wire width 2 $1417 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1322 + cell $or $1418 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $1317 - connect \B $1319 - connect \Y $1321 + connect \A \fus_dest3_o$125 + connect \B $1415 + connect \Y $1417 end - process $group_546 + process $group_568 assign \xer_data_i 2'00 - assign \xer_data_i $1321 + assign \xer_data_i $1417 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1323 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1324 + wire width 3 $1419 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1266 - connect \B \addr_en$1282 - connect \Y $1324 - end + wire width 2 $1420 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1326 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1327 + cell $or $1421 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1298 - connect \B \addr_en$1314 - connect \Y $1326 + connect \A \addr_en$1396 + connect \B \addr_en$1412 + connect \Y $1420 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1328 + wire width 2 $1422 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1329 + cell $or $1423 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $1324 - connect \B $1326 - connect \Y $1328 + connect \A \addr_en$1380 + connect \B $1420 + connect \Y $1422 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1330 + cell $pos $1424 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A $1328 - connect \Y $1323 + connect \A $1422 + connect \Y $1419 end - process $group_547 + process $group_569 assign \xer_wen 3'000 - assign \xer_wen $1323 + assign \xer_wen $1419 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115656,17 +224206,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $1331 + connect \Y $1425 end - process $group_548 + process $group_570 assign \wrflag_alu0_xer_ov_3 1'0 - assign \wrflag_alu0_xer_ov_3 $1331 + assign \wrflag_alu0_xer_ov_3 $1425 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115674,61 +224224,61 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $1333 + connect \Y $1427 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [4] + connect \A \fus_cu_wr__rel_o$93 [4] connect \B \fu_enable [5] - connect \Y $1335 + connect \Y $1429 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1337 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [2] + connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [6] - connect \Y $1337 + connect \Y $1431 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1339 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [2] + connect \A \fus_cu_wr__rel_o$99 [2] connect \B \fu_enable [7] - connect \Y $1339 + connect \Y $1433 end - process $group_549 + process $group_571 assign \wrpick_XER_xer_ov_i 4'0000 - assign \wrpick_XER_xer_ov_i [0] $1333 - assign \wrpick_XER_xer_ov_i [1] $1335 - assign \wrpick_XER_xer_ov_i [2] $1337 - assign \wrpick_XER_xer_ov_i [3] $1339 + assign \wrpick_XER_xer_ov_i [0] $1427 + assign \wrpick_XER_xer_ov_i [1] $1429 + assign \wrpick_XER_xer_ov_i [2] $1431 + assign \wrpick_XER_xer_ov_i [3] $1433 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1341 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1342 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115736,121 +224286,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1342 + connect \Y $1436 end - process $group_550 - assign \wr_pick$1341 1'0 - assign \wr_pick$1341 $1342 + process $group_572 + assign \wr_pick$1435 1'0 + assign \wr_pick$1435 $1436 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1344 + wire width 1 \wr_pick_dly$1438 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1344$next - process $group_551 - assign \wr_pick_dly$1344$next \wr_pick_dly$1344 - assign \wr_pick_dly$1344$next \wr_pick$1341 + wire width 1 \wr_pick_dly$1438$next + process $group_573 + assign \wr_pick_dly$1438$next \wr_pick_dly$1438 + assign \wr_pick_dly$1438$next \wr_pick$1435 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1344$next 1'0 + assign \wr_pick_dly$1438$next 1'0 end sync init - update \wr_pick_dly$1344 1'0 + update \wr_pick_dly$1438 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1344 \wr_pick_dly$1344$next + update \wr_pick_dly$1438 \wr_pick_dly$1438$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1345 + wire width 1 $1439 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1346 + cell $not $1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1344 - connect \Y $1345 + connect \A \wr_pick_dly$1438 + connect \Y $1439 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1347 + wire width 1 $1441 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1348 + cell $and $1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1341 - connect \B $1345 - connect \Y $1347 + connect \A \wr_pick$1435 + connect \B $1439 + connect \Y $1441 end - process $group_552 - assign \wr_pick_rise$839 1'0 - assign \wr_pick_rise$839 $1347 + process $group_574 + assign \wr_pick_rise$956 1'0 + assign \wr_pick_rise$956 $1441 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1350 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1341 + connect \A \wr_pick$1435 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1350 + connect \Y $1444 end - process $group_553 - assign \wp$1349 1'0 - assign \wp$1349 $1350 + process $group_575 + assign \wp$1443 1'0 + assign \wp$1443 $1444 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1448 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1349 - connect \Y $1353 + connect \S \wp$1443 + connect \Y $1447 end - process $group_554 - assign \addr_en$1352 3'000 - assign \addr_en$1352 $1353 + process $group_576 + assign \addr_en$1446 3'000 + assign \addr_en$1446 $1447 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1355 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$126 - connect \B \fus_cu_busy_o$16 - connect \Y $1355 + connect \A \fus_xer_ov_ok$127 + connect \B \fus_cu_busy_o$17 + connect \Y $1449 end - process $group_555 + process $group_577 assign \wrflag_spr0_xer_ov_4 1'0 - assign \wrflag_spr0_xer_ov_4 $1355 + assign \wrflag_spr0_xer_ov_4 $1449 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1357 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115858,121 +224408,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1358 + connect \Y $1452 end - process $group_556 - assign \wr_pick$1357 1'0 - assign \wr_pick$1357 $1358 + process $group_578 + assign \wr_pick$1451 1'0 + assign \wr_pick$1451 $1452 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1360 + wire width 1 \wr_pick_dly$1454 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1360$next - process $group_557 - assign \wr_pick_dly$1360$next \wr_pick_dly$1360 - assign \wr_pick_dly$1360$next \wr_pick$1357 + wire width 1 \wr_pick_dly$1454$next + process $group_579 + assign \wr_pick_dly$1454$next \wr_pick_dly$1454 + assign \wr_pick_dly$1454$next \wr_pick$1451 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1360$next 1'0 + assign \wr_pick_dly$1454$next 1'0 end sync init - update \wr_pick_dly$1360 1'0 + update \wr_pick_dly$1454 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1360 \wr_pick_dly$1360$next + update \wr_pick_dly$1454 \wr_pick_dly$1454$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1361 + wire width 1 $1455 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1362 + cell $not $1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1360 - connect \Y $1361 + connect \A \wr_pick_dly$1454 + connect \Y $1455 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1363 + wire width 1 $1457 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1364 + cell $and $1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1357 - connect \B $1361 - connect \Y $1363 + connect \A \wr_pick$1451 + connect \B $1455 + connect \Y $1457 end - process $group_558 - assign \wr_pick_rise$916 1'0 - assign \wr_pick_rise$916 $1363 + process $group_580 + assign \wr_pick_rise$1032 1'0 + assign \wr_pick_rise$1032 $1457 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1357 + connect \A \wr_pick$1451 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1366 + connect \Y $1460 end - process $group_559 - assign \wp$1365 1'0 - assign \wp$1365 $1366 + process $group_581 + assign \wp$1459 1'0 + assign \wp$1459 $1460 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1368 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1464 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1365 - connect \Y $1369 + connect \S \wp$1459 + connect \Y $1463 end - process $group_560 - assign \addr_en$1368 3'000 - assign \addr_en$1368 $1369 + process $group_582 + assign \addr_en$1462 3'000 + assign \addr_en$1462 $1463 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$127 - connect \B \fus_cu_busy_o$19 - connect \Y $1371 + connect \A \fus_xer_ov_ok$128 + connect \B \fus_cu_busy_o$20 + connect \Y $1465 end - process $group_561 + process $group_583 assign \wrflag_div0_xer_ov_2 1'0 - assign \wrflag_div0_xer_ov_2 $1371 + assign \wrflag_div0_xer_ov_2 $1465 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1374 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -115980,121 +224530,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1374 + connect \Y $1468 end - process $group_562 - assign \wr_pick$1373 1'0 - assign \wr_pick$1373 $1374 + process $group_584 + assign \wr_pick$1467 1'0 + assign \wr_pick$1467 $1468 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1376 + wire width 1 \wr_pick_dly$1470 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1376$next - process $group_563 - assign \wr_pick_dly$1376$next \wr_pick_dly$1376 - assign \wr_pick_dly$1376$next \wr_pick$1373 + wire width 1 \wr_pick_dly$1470$next + process $group_585 + assign \wr_pick_dly$1470$next \wr_pick_dly$1470 + assign \wr_pick_dly$1470$next \wr_pick$1467 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1376$next 1'0 + assign \wr_pick_dly$1470$next 1'0 end sync init - update \wr_pick_dly$1376 1'0 + update \wr_pick_dly$1470 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1376 \wr_pick_dly$1376$next + update \wr_pick_dly$1470 \wr_pick_dly$1470$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1377 + wire width 1 $1471 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1378 + cell $not $1472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1376 - connect \Y $1377 + connect \A \wr_pick_dly$1470 + connect \Y $1471 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1379 + wire width 1 $1473 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1380 + cell $and $1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1373 - connect \B $1377 - connect \Y $1379 + connect \A \wr_pick$1467 + connect \B $1471 + connect \Y $1473 end - process $group_564 - assign \wr_pick_rise$938 1'0 - assign \wr_pick_rise$938 $1379 + process $group_586 + assign \wr_pick_rise$1054 1'0 + assign \wr_pick_rise$1054 $1473 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1382 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1373 + connect \A \wr_pick$1467 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1382 + connect \Y $1476 end - process $group_565 - assign \wp$1381 1'0 - assign \wp$1381 $1382 + process $group_587 + assign \wp$1475 1'0 + assign \wp$1475 $1476 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1480 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1381 - connect \Y $1385 + connect \S \wp$1475 + connect \Y $1479 end - process $group_566 - assign \addr_en$1384 3'000 - assign \addr_en$1384 $1385 + process $group_588 + assign \addr_en$1478 3'000 + assign \addr_en$1478 $1479 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1387 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$128 - connect \B \fus_cu_busy_o$22 - connect \Y $1387 + connect \A \fus_xer_ov_ok$129 + connect \B \fus_cu_busy_o$23 + connect \Y $1481 end - process $group_567 + process $group_589 assign \wrflag_mul0_xer_ov_2 1'0 - assign \wrflag_mul0_xer_ov_2 $1387 + assign \wrflag_mul0_xer_ov_2 $1481 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116102,99 +224652,99 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1390 + connect \Y $1484 end - process $group_568 - assign \wr_pick$1389 1'0 - assign \wr_pick$1389 $1390 + process $group_590 + assign \wr_pick$1483 1'0 + assign \wr_pick$1483 $1484 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1392 + wire width 1 \wr_pick_dly$1486 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1392$next - process $group_569 - assign \wr_pick_dly$1392$next \wr_pick_dly$1392 - assign \wr_pick_dly$1392$next \wr_pick$1389 + wire width 1 \wr_pick_dly$1486$next + process $group_591 + assign \wr_pick_dly$1486$next \wr_pick_dly$1486 + assign \wr_pick_dly$1486$next \wr_pick$1483 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1392$next 1'0 + assign \wr_pick_dly$1486$next 1'0 end sync init - update \wr_pick_dly$1392 1'0 + update \wr_pick_dly$1486 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1392 \wr_pick_dly$1392$next + update \wr_pick_dly$1486 \wr_pick_dly$1486$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1393 + wire width 1 $1487 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1394 + cell $not $1488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1392 - connect \Y $1393 + connect \A \wr_pick_dly$1486 + connect \Y $1487 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1395 + wire width 1 $1489 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1396 + cell $and $1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1389 - connect \B $1393 - connect \Y $1395 + connect \A \wr_pick$1483 + connect \B $1487 + connect \Y $1489 end - process $group_570 - assign \wr_pick_rise$958 1'0 - assign \wr_pick_rise$958 $1395 + process $group_592 + assign \wr_pick_rise$1074 1'0 + assign \wr_pick_rise$1074 $1489 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1389 + connect \A \wr_pick$1483 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1398 + connect \Y $1492 end - process $group_571 - assign \wp$1397 1'0 - assign \wp$1397 $1398 + process $group_593 + assign \wp$1491 1'0 + assign \wp$1491 $1492 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1496 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1397 - connect \Y $1401 + connect \S \wp$1491 + connect \Y $1495 end - process $group_572 - assign \addr_en$1400 3'000 - assign \addr_en$1400 $1401 + process $group_594 + assign \addr_en$1494 3'000 + assign \addr_en$1494 $1495 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1403 + wire width 2 $1497 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1404 + cell $or $1498 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -116202,89 +224752,89 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $1403 + connect \Y $1497 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1405 + wire width 2 $1499 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1406 + cell $or $1500 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$129 - connect \B \fus_dest3_o$130 - connect \Y $1405 + connect \A \fus_dest3_o$130 + connect \B \fus_dest3_o$131 + connect \Y $1499 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1407 + wire width 2 $1501 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1408 + cell $or $1502 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $1403 - connect \B $1405 - connect \Y $1407 + connect \A $1497 + connect \B $1499 + connect \Y $1501 end - process $group_573 - assign \xer_data_i$153 2'00 - assign \xer_data_i$153 $1407 + process $group_595 + assign \xer_data_i$154 2'00 + assign \xer_data_i$154 $1501 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1409 + wire width 3 $1503 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1410 + cell $or $1504 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1352 - connect \B \addr_en$1368 - connect \Y $1409 + connect \A \addr_en$1446 + connect \B \addr_en$1462 + connect \Y $1503 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1411 + wire width 3 $1505 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1412 + cell $or $1506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1384 - connect \B \addr_en$1400 - connect \Y $1411 + connect \A \addr_en$1478 + connect \B \addr_en$1494 + connect \Y $1505 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1413 + wire width 3 $1507 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1414 + cell $or $1508 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $1409 - connect \B $1411 - connect \Y $1413 + connect \A $1503 + connect \B $1505 + connect \Y $1507 end - process $group_574 - assign \xer_wen$154 3'000 - assign \xer_wen$154 $1413 + process $group_596 + assign \xer_wen$155 3'000 + assign \xer_wen$155 $1507 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116292,17 +224842,17 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $1415 + connect \Y $1509 end - process $group_575 + process $group_597 assign \wrflag_alu0_xer_so_4 1'0 - assign \wrflag_alu0_xer_so_4 $1415 + assign \wrflag_alu0_xer_so_4 $1509 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1417 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116310,61 +224860,61 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $1417 + connect \Y $1511 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [3] + connect \A \fus_cu_wr__rel_o$93 [3] connect \B \fu_enable [5] - connect \Y $1419 + connect \Y $1513 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [3] + connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [6] - connect \Y $1421 + connect \Y $1515 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [3] + connect \A \fus_cu_wr__rel_o$99 [3] connect \B \fu_enable [7] - connect \Y $1423 + connect \Y $1517 end - process $group_576 + process $group_598 assign \wrpick_XER_xer_so_i 4'0000 - assign \wrpick_XER_xer_so_i [0] $1417 - assign \wrpick_XER_xer_so_i [1] $1419 - assign \wrpick_XER_xer_so_i [2] $1421 - assign \wrpick_XER_xer_so_i [3] $1423 + assign \wrpick_XER_xer_so_i [0] $1511 + assign \wrpick_XER_xer_so_i [1] $1513 + assign \wrpick_XER_xer_so_i [2] $1515 + assign \wrpick_XER_xer_so_i [3] $1517 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116372,121 +224922,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1426 + connect \Y $1520 end - process $group_577 - assign \wr_pick$1425 1'0 - assign \wr_pick$1425 $1426 + process $group_599 + assign \wr_pick$1519 1'0 + assign \wr_pick$1519 $1520 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1428 + wire width 1 \wr_pick_dly$1522 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1428$next - process $group_578 - assign \wr_pick_dly$1428$next \wr_pick_dly$1428 - assign \wr_pick_dly$1428$next \wr_pick$1425 + wire width 1 \wr_pick_dly$1522$next + process $group_600 + assign \wr_pick_dly$1522$next \wr_pick_dly$1522 + assign \wr_pick_dly$1522$next \wr_pick$1519 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1428$next 1'0 + assign \wr_pick_dly$1522$next 1'0 end sync init - update \wr_pick_dly$1428 1'0 + update \wr_pick_dly$1522 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1428 \wr_pick_dly$1428$next + update \wr_pick_dly$1522 \wr_pick_dly$1522$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1429 + wire width 1 $1523 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1430 + cell $not $1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1428 - connect \Y $1429 + connect \A \wr_pick_dly$1522 + connect \Y $1523 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1431 + wire width 1 $1525 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1432 + cell $and $1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1425 - connect \B $1429 - connect \Y $1431 + connect \A \wr_pick$1519 + connect \B $1523 + connect \Y $1525 end - process $group_579 - assign \wr_pick_rise$840 1'0 - assign \wr_pick_rise$840 $1431 + process $group_601 + assign \wr_pick_rise$957 1'0 + assign \wr_pick_rise$957 $1525 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1434 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1425 + connect \A \wr_pick$1519 connect \B \wrpick_XER_xer_so_en_o - connect \Y $1434 + connect \Y $1528 end - process $group_580 - assign \wp$1433 1'0 - assign \wp$1433 $1434 + process $group_602 + assign \wp$1527 1'0 + assign \wp$1527 $1528 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 1 \addr_en$1436 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 1 $1437 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 1 \addr_en$1530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 1 $1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1532 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1433 - connect \Y $1437 + connect \S \wp$1527 + connect \Y $1531 end - process $group_581 - assign \addr_en$1436 1'0 - assign \addr_en$1436 $1437 + process $group_603 + assign \addr_en$1530 1'0 + assign \addr_en$1530 $1531 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1439 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$131 - connect \B \fus_cu_busy_o$16 - connect \Y $1439 + connect \A \fus_xer_so_ok$132 + connect \B \fus_cu_busy_o$17 + connect \Y $1533 end - process $group_582 + process $group_604 assign \wrflag_spr0_xer_so_3 1'0 - assign \wrflag_spr0_xer_so_3 $1439 + assign \wrflag_spr0_xer_so_3 $1533 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1441 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1442 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116494,121 +225044,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1442 + connect \Y $1536 end - process $group_583 - assign \wr_pick$1441 1'0 - assign \wr_pick$1441 $1442 + process $group_605 + assign \wr_pick$1535 1'0 + assign \wr_pick$1535 $1536 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1444 + wire width 1 \wr_pick_dly$1538 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1444$next - process $group_584 - assign \wr_pick_dly$1444$next \wr_pick_dly$1444 - assign \wr_pick_dly$1444$next \wr_pick$1441 + wire width 1 \wr_pick_dly$1538$next + process $group_606 + assign \wr_pick_dly$1538$next \wr_pick_dly$1538 + assign \wr_pick_dly$1538$next \wr_pick$1535 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1444$next 1'0 + assign \wr_pick_dly$1538$next 1'0 end sync init - update \wr_pick_dly$1444 1'0 + update \wr_pick_dly$1538 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1444 \wr_pick_dly$1444$next + update \wr_pick_dly$1538 \wr_pick_dly$1538$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1445 + wire width 1 $1539 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1446 + cell $not $1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1444 - connect \Y $1445 + connect \A \wr_pick_dly$1538 + connect \Y $1539 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1447 + wire width 1 $1541 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1448 + cell $and $1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1441 - connect \B $1445 - connect \Y $1447 + connect \A \wr_pick$1535 + connect \B $1539 + connect \Y $1541 end - process $group_585 - assign \wr_pick_rise$917 1'0 - assign \wr_pick_rise$917 $1447 + process $group_607 + assign \wr_pick_rise$1033 1'0 + assign \wr_pick_rise$1033 $1541 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1441 + connect \A \wr_pick$1535 connect \B \wrpick_XER_xer_so_en_o - connect \Y $1450 + connect \Y $1544 end - process $group_586 - assign \wp$1449 1'0 - assign \wp$1449 $1450 + process $group_608 + assign \wp$1543 1'0 + assign \wp$1543 $1544 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 1 \addr_en$1452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 1 $1453 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 1 \addr_en$1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 1 $1547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1548 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1449 - connect \Y $1453 + connect \S \wp$1543 + connect \Y $1547 end - process $group_587 - assign \addr_en$1452 1'0 - assign \addr_en$1452 $1453 + process $group_609 + assign \addr_en$1546 1'0 + assign \addr_en$1546 $1547 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$132 - connect \B \fus_cu_busy_o$19 - connect \Y $1455 + connect \A \fus_xer_so_ok$133 + connect \B \fus_cu_busy_o$20 + connect \Y $1549 end - process $group_588 + process $group_610 assign \wrflag_div0_xer_so_3 1'0 - assign \wrflag_div0_xer_so_3 $1455 + assign \wrflag_div0_xer_so_3 $1549 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1458 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116616,121 +225166,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1458 + connect \Y $1552 end - process $group_589 - assign \wr_pick$1457 1'0 - assign \wr_pick$1457 $1458 + process $group_611 + assign \wr_pick$1551 1'0 + assign \wr_pick$1551 $1552 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1460 + wire width 1 \wr_pick_dly$1554 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1460$next - process $group_590 - assign \wr_pick_dly$1460$next \wr_pick_dly$1460 - assign \wr_pick_dly$1460$next \wr_pick$1457 + wire width 1 \wr_pick_dly$1554$next + process $group_612 + assign \wr_pick_dly$1554$next \wr_pick_dly$1554 + assign \wr_pick_dly$1554$next \wr_pick$1551 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1460$next 1'0 + assign \wr_pick_dly$1554$next 1'0 end sync init - update \wr_pick_dly$1460 1'0 + update \wr_pick_dly$1554 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1460 \wr_pick_dly$1460$next + update \wr_pick_dly$1554 \wr_pick_dly$1554$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1461 + wire width 1 $1555 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1462 + cell $not $1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1460 - connect \Y $1461 + connect \A \wr_pick_dly$1554 + connect \Y $1555 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1463 + wire width 1 $1557 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1464 + cell $and $1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1457 - connect \B $1461 - connect \Y $1463 + connect \A \wr_pick$1551 + connect \B $1555 + connect \Y $1557 end - process $group_591 - assign \wr_pick_rise$939 1'0 - assign \wr_pick_rise$939 $1463 + process $group_613 + assign \wr_pick_rise$1055 1'0 + assign \wr_pick_rise$1055 $1557 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1457 + connect \A \wr_pick$1551 connect \B \wrpick_XER_xer_so_en_o - connect \Y $1466 + connect \Y $1560 end - process $group_592 - assign \wp$1465 1'0 - assign \wp$1465 $1466 + process $group_614 + assign \wp$1559 1'0 + assign \wp$1559 $1560 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 1 \addr_en$1468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 1 $1469 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 1 \addr_en$1562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 1 $1563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1564 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1465 - connect \Y $1469 + connect \S \wp$1559 + connect \Y $1563 end - process $group_593 - assign \addr_en$1468 1'0 - assign \addr_en$1468 $1469 + process $group_615 + assign \addr_en$1562 1'0 + assign \addr_en$1562 $1563 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$133 - connect \B \fus_cu_busy_o$22 - connect \Y $1471 + connect \A \fus_xer_so_ok$134 + connect \B \fus_cu_busy_o$23 + connect \Y $1565 end - process $group_594 + process $group_616 assign \wrflag_mul0_xer_so_3 1'0 - assign \wrflag_mul0_xer_so_3 $1471 + assign \wrflag_mul0_xer_so_3 $1565 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1473 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -116738,303 +225288,303 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $1474 + connect \Y $1568 end - process $group_595 - assign \wr_pick$1473 1'0 - assign \wr_pick$1473 $1474 + process $group_617 + assign \wr_pick$1567 1'0 + assign \wr_pick$1567 $1568 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1476 + wire width 1 \wr_pick_dly$1570 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1476$next - process $group_596 - assign \wr_pick_dly$1476$next \wr_pick_dly$1476 - assign \wr_pick_dly$1476$next \wr_pick$1473 + wire width 1 \wr_pick_dly$1570$next + process $group_618 + assign \wr_pick_dly$1570$next \wr_pick_dly$1570 + assign \wr_pick_dly$1570$next \wr_pick$1567 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1476$next 1'0 + assign \wr_pick_dly$1570$next 1'0 end sync init - update \wr_pick_dly$1476 1'0 + update \wr_pick_dly$1570 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1476 \wr_pick_dly$1476$next + update \wr_pick_dly$1570 \wr_pick_dly$1570$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1477 + wire width 1 $1571 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1478 + cell $not $1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1476 - connect \Y $1477 + connect \A \wr_pick_dly$1570 + connect \Y $1571 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1479 + wire width 1 $1573 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1480 + cell $and $1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1473 - connect \B $1477 - connect \Y $1479 + connect \A \wr_pick$1567 + connect \B $1571 + connect \Y $1573 end - process $group_597 - assign \wr_pick_rise$959 1'0 - assign \wr_pick_rise$959 $1479 + process $group_619 + assign \wr_pick_rise$1075 1'0 + assign \wr_pick_rise$1075 $1573 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1481 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1482 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1473 + connect \A \wr_pick$1567 connect \B \wrpick_XER_xer_so_en_o - connect \Y $1482 + connect \Y $1576 end - process $group_598 - assign \wp$1481 1'0 - assign \wp$1481 $1482 + process $group_620 + assign \wp$1575 1'0 + assign \wp$1575 $1576 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 1 \addr_en$1484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 1 $1485 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 1 \addr_en$1578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 1 $1579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1580 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1481 - connect \Y $1485 + connect \S \wp$1575 + connect \Y $1579 end - process $group_599 - assign \addr_en$1484 1'0 - assign \addr_en$1484 $1485 + process $group_621 + assign \addr_en$1578 1'0 + assign \addr_en$1578 $1579 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1487 + wire width 2 $1581 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1488 + wire width 1 $1582 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1489 + cell $or $1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest5_o$134 - connect \B \fus_dest4_o$135 - connect \Y $1488 + connect \A \fus_dest5_o$135 + connect \B \fus_dest4_o$136 + connect \Y $1582 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1490 + wire width 1 $1584 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1491 + cell $or $1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest4_o$136 - connect \B \fus_dest4_o$137 - connect \Y $1490 + connect \A \fus_dest4_o$137 + connect \B \fus_dest4_o$138 + connect \Y $1584 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1492 + wire width 1 $1586 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1493 + cell $or $1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1488 - connect \B $1490 - connect \Y $1492 + connect \A $1582 + connect \B $1584 + connect \Y $1586 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1494 + cell $pos $1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 - connect \A $1492 - connect \Y $1487 + connect \A $1586 + connect \Y $1581 end - process $group_600 - assign \xer_data_i$155 2'00 - assign \xer_data_i$155 $1487 + process $group_622 + assign \xer_data_i$156 2'00 + assign \xer_data_i$156 $1581 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1495 + wire width 3 $1589 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1496 + wire width 1 $1590 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1497 + cell $or $1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1436 - connect \B \addr_en$1452 - connect \Y $1496 + connect \A \addr_en$1530 + connect \B \addr_en$1546 + connect \Y $1590 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1498 + wire width 1 $1592 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1499 + cell $or $1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1468 - connect \B \addr_en$1484 - connect \Y $1498 + connect \A \addr_en$1562 + connect \B \addr_en$1578 + connect \Y $1592 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1500 + wire width 1 $1594 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1501 + cell $or $1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1496 - connect \B $1498 - connect \Y $1500 + connect \A $1590 + connect \B $1592 + connect \Y $1594 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1502 + cell $pos $1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A $1500 - connect \Y $1495 + connect \A $1594 + connect \Y $1589 end - process $group_601 - assign \xer_wen$156 3'000 - assign \xer_wen$156 $1495 + process $group_623 + assign \xer_wen$157 3'000 + assign \xer_wen$157 $1589 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1503 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast1_ok - connect \B \fus_cu_busy_o$7 - connect \Y $1503 + connect \B \fus_cu_busy_o$8 + connect \Y $1597 end - process $group_602 + process $group_624 assign \wrflag_branch0_fast1_0 1'0 - assign \wrflag_branch0_fast1_0 $1503 + assign \wrflag_branch0_fast1_0 $1597 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1505 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$138 [0] + connect \A \fus_cu_wr__rel_o$139 [0] connect \B \fu_enable [2] - connect \Y $1505 + connect \Y $1599 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1507 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [1] + connect \A \fus_cu_wr__rel_o$87 [1] connect \B \fu_enable [3] - connect \Y $1507 + connect \Y $1601 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1509 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [2] + connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [5] - connect \Y $1509 + connect \Y $1603 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1511 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$138 [1] + connect \A \fus_cu_wr__rel_o$139 [1] connect \B \fu_enable [2] - connect \Y $1511 + connect \Y $1605 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1513 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [2] + connect \A \fus_cu_wr__rel_o$87 [2] connect \B \fu_enable [3] - connect \Y $1513 + connect \Y $1607 end - process $group_603 + process $group_625 assign \wrpick_FAST_fast1_i 5'00000 - assign \wrpick_FAST_fast1_i [0] $1505 - assign \wrpick_FAST_fast1_i [1] $1507 - assign \wrpick_FAST_fast1_i [2] $1509 - assign \wrpick_FAST_fast1_i [3] $1511 - assign \wrpick_FAST_fast1_i [4] $1513 + assign \wrpick_FAST_fast1_i [0] $1599 + assign \wrpick_FAST_fast1_i [1] $1601 + assign \wrpick_FAST_fast1_i [2] $1603 + assign \wrpick_FAST_fast1_i [3] $1605 + assign \wrpick_FAST_fast1_i [4] $1607 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1515 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117042,134 +225592,134 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1516 + connect \Y $1610 end - process $group_604 - assign \wr_pick$1515 1'0 - assign \wr_pick$1515 $1516 + process $group_626 + assign \wr_pick$1609 1'0 + assign \wr_pick$1609 $1610 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1518 + wire width 1 \wr_pick_dly$1612 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1518$next - process $group_605 - assign \wr_pick_dly$1518$next \wr_pick_dly$1518 - assign \wr_pick_dly$1518$next \wr_pick$1515 + wire width 1 \wr_pick_dly$1612$next + process $group_627 + assign \wr_pick_dly$1612$next \wr_pick_dly$1612 + assign \wr_pick_dly$1612$next \wr_pick$1609 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1518$next 1'0 + assign \wr_pick_dly$1612$next 1'0 end sync init - update \wr_pick_dly$1518 1'0 + update \wr_pick_dly$1612 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1518 \wr_pick_dly$1518$next + update \wr_pick_dly$1612 \wr_pick_dly$1612$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1519 + wire width 1 \wr_pick_rise$1613 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1520 + wire width 1 $1614 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1521 + cell $not $1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1518 - connect \Y $1520 + connect \A \wr_pick_dly$1612 + connect \Y $1614 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1522 + wire width 1 $1616 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1523 + cell $and $1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1515 - connect \B $1520 - connect \Y $1522 + connect \A \wr_pick$1609 + connect \B $1614 + connect \Y $1616 end - process $group_606 - assign \wr_pick_rise$1519 1'0 - assign \wr_pick_rise$1519 $1522 + process $group_628 + assign \wr_pick_rise$1613 1'0 + assign \wr_pick_rise$1613 $1616 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1524 + wire width 1 \wr_pick_rise$1618 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1525 - process $group_607 - assign \fus_cu_wr__go_i$139 3'000 - assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1519 - assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1524 - assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1525 + wire width 1 \wr_pick_rise$1619 + process $group_629 + assign \fus_cu_wr__go_i$140 3'000 + assign \fus_cu_wr__go_i$140 [0] \wr_pick_rise$1613 + assign \fus_cu_wr__go_i$140 [1] \wr_pick_rise$1618 + assign \fus_cu_wr__go_i$140 [2] \wr_pick_rise$1619 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1526 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1527 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1515 + connect \A \wr_pick$1609 connect \B \wrpick_FAST_fast1_en_o - connect \Y $1527 + connect \Y $1621 end - process $group_608 - assign \wp$1526 1'0 - assign \wp$1526 $1527 + process $group_630 + assign \wp$1620 1'0 + assign \wp$1620 $1621 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1529 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1625 parameter \WIDTH 3 connect \A 3'000 - connect \B \fasto1 - connect \S \wp$1526 - connect \Y $1530 + connect \B \core_fasto1 + connect \S \wp$1620 + connect \Y $1624 end - process $group_609 - assign \addr_en$1529 3'000 - assign \addr_en$1529 $1530 + process $group_631 + assign \addr_en$1623 3'000 + assign \addr_en$1623 $1624 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$140 - connect \B \fus_cu_busy_o$10 - connect \Y $1532 + connect \A \fus_fast1_ok$141 + connect \B \fus_cu_busy_o$11 + connect \Y $1626 end - process $group_610 + process $group_632 assign \wrflag_trap0_fast1_1 1'0 - assign \wrflag_trap0_fast1_1 $1532 + assign \wrflag_trap0_fast1_1 $1626 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1534 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117177,121 +225727,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1535 + connect \Y $1629 end - process $group_611 - assign \wr_pick$1534 1'0 - assign \wr_pick$1534 $1535 + process $group_633 + assign \wr_pick$1628 1'0 + assign \wr_pick$1628 $1629 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1537 + wire width 1 \wr_pick_dly$1631 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1537$next - process $group_612 - assign \wr_pick_dly$1537$next \wr_pick_dly$1537 - assign \wr_pick_dly$1537$next \wr_pick$1534 + wire width 1 \wr_pick_dly$1631$next + process $group_634 + assign \wr_pick_dly$1631$next \wr_pick_dly$1631 + assign \wr_pick_dly$1631$next \wr_pick$1628 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1537$next 1'0 + assign \wr_pick_dly$1631$next 1'0 end sync init - update \wr_pick_dly$1537 1'0 + update \wr_pick_dly$1631 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1537 \wr_pick_dly$1537$next + update \wr_pick_dly$1631 \wr_pick_dly$1631$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1538 + wire width 1 $1632 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1539 + cell $not $1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1537 - connect \Y $1538 + connect \A \wr_pick_dly$1631 + connect \Y $1632 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1540 + wire width 1 $1634 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1541 + cell $and $1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1534 - connect \B $1538 - connect \Y $1540 + connect \A \wr_pick$1628 + connect \B $1632 + connect \Y $1634 end - process $group_613 - assign \wr_pick_rise$875 1'0 - assign \wr_pick_rise$875 $1540 + process $group_635 + assign \wr_pick_rise$992 1'0 + assign \wr_pick_rise$992 $1634 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1542 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1534 + connect \A \wr_pick$1628 connect \B \wrpick_FAST_fast1_en_o - connect \Y $1543 + connect \Y $1637 end - process $group_614 - assign \wp$1542 1'0 - assign \wp$1542 $1543 + process $group_636 + assign \wp$1636 1'0 + assign \wp$1636 $1637 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1545 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1546 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1641 parameter \WIDTH 3 connect \A 3'000 - connect \B \fasto1 - connect \S \wp$1542 - connect \Y $1546 + connect \B \core_fasto1 + connect \S \wp$1636 + connect \Y $1640 end - process $group_615 - assign \addr_en$1545 3'000 - assign \addr_en$1545 $1546 + process $group_637 + assign \addr_en$1639 3'000 + assign \addr_en$1639 $1640 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1548 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$141 - connect \B \fus_cu_busy_o$16 - connect \Y $1548 + connect \A \fus_fast1_ok$142 + connect \B \fus_cu_busy_o$17 + connect \Y $1642 end - process $group_616 + process $group_638 assign \wrflag_spr0_fast1_2 1'0 - assign \wrflag_spr0_fast1_2 $1548 + assign \wrflag_spr0_fast1_2 $1642 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1550 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1551 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117299,121 +225849,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1551 + connect \Y $1645 end - process $group_617 - assign \wr_pick$1550 1'0 - assign \wr_pick$1550 $1551 + process $group_639 + assign \wr_pick$1644 1'0 + assign \wr_pick$1644 $1645 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1553 + wire width 1 \wr_pick_dly$1647 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1553$next - process $group_618 - assign \wr_pick_dly$1553$next \wr_pick_dly$1553 - assign \wr_pick_dly$1553$next \wr_pick$1550 + wire width 1 \wr_pick_dly$1647$next + process $group_640 + assign \wr_pick_dly$1647$next \wr_pick_dly$1647 + assign \wr_pick_dly$1647$next \wr_pick$1644 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1553$next 1'0 + assign \wr_pick_dly$1647$next 1'0 end sync init - update \wr_pick_dly$1553 1'0 + update \wr_pick_dly$1647 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1553 \wr_pick_dly$1553$next + update \wr_pick_dly$1647 \wr_pick_dly$1647$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1554 + wire width 1 $1648 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1555 + cell $not $1649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1553 - connect \Y $1554 + connect \A \wr_pick_dly$1647 + connect \Y $1648 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1556 + wire width 1 $1650 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1557 + cell $and $1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1550 - connect \B $1554 - connect \Y $1556 + connect \A \wr_pick$1644 + connect \B $1648 + connect \Y $1650 end - process $group_619 - assign \wr_pick_rise$918 1'0 - assign \wr_pick_rise$918 $1556 + process $group_641 + assign \wr_pick_rise$1034 1'0 + assign \wr_pick_rise$1034 $1650 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1559 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1550 + connect \A \wr_pick$1644 connect \B \wrpick_FAST_fast1_en_o - connect \Y $1559 + connect \Y $1653 end - process $group_620 - assign \wp$1558 1'0 - assign \wp$1558 $1559 + process $group_642 + assign \wp$1652 1'0 + assign \wp$1652 $1653 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1561 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1562 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1657 parameter \WIDTH 3 connect \A 3'000 - connect \B \fasto1 - connect \S \wp$1558 - connect \Y $1562 + connect \B \core_fasto1 + connect \S \wp$1652 + connect \Y $1656 end - process $group_621 - assign \addr_en$1561 3'000 - assign \addr_en$1561 $1562 + process $group_643 + assign \addr_en$1655 3'000 + assign \addr_en$1655 $1656 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast2_ok - connect \B \fus_cu_busy_o$7 - connect \Y $1564 + connect \B \fus_cu_busy_o$8 + connect \Y $1658 end - process $group_622 + process $group_644 assign \wrflag_branch0_fast1_1 1'0 - assign \wrflag_branch0_fast1_1 $1564 + assign \wrflag_branch0_fast1_1 $1658 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1566 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1567 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117421,121 +225971,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1567 + connect \Y $1661 end - process $group_623 - assign \wr_pick$1566 1'0 - assign \wr_pick$1566 $1567 + process $group_645 + assign \wr_pick$1660 1'0 + assign \wr_pick$1660 $1661 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1569 + wire width 1 \wr_pick_dly$1663 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1569$next - process $group_624 - assign \wr_pick_dly$1569$next \wr_pick_dly$1569 - assign \wr_pick_dly$1569$next \wr_pick$1566 + wire width 1 \wr_pick_dly$1663$next + process $group_646 + assign \wr_pick_dly$1663$next \wr_pick_dly$1663 + assign \wr_pick_dly$1663$next \wr_pick$1660 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1569$next 1'0 + assign \wr_pick_dly$1663$next 1'0 end sync init - update \wr_pick_dly$1569 1'0 + update \wr_pick_dly$1663 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1569 \wr_pick_dly$1569$next + update \wr_pick_dly$1663 \wr_pick_dly$1663$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1570 + wire width 1 $1664 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1571 + cell $not $1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1569 - connect \Y $1570 + connect \A \wr_pick_dly$1663 + connect \Y $1664 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1572 + wire width 1 $1666 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1573 + cell $and $1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1566 - connect \B $1570 - connect \Y $1572 + connect \A \wr_pick$1660 + connect \B $1664 + connect \Y $1666 end - process $group_625 - assign \wr_pick_rise$1524 1'0 - assign \wr_pick_rise$1524 $1572 + process $group_647 + assign \wr_pick_rise$1618 1'0 + assign \wr_pick_rise$1618 $1666 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1566 + connect \A \wr_pick$1660 connect \B \wrpick_FAST_fast1_en_o - connect \Y $1575 + connect \Y $1669 end - process $group_626 - assign \wp$1574 1'0 - assign \wp$1574 $1575 + process $group_648 + assign \wp$1668 1'0 + assign \wp$1668 $1669 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1577 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1578 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1673 parameter \WIDTH 3 connect \A 3'000 - connect \B \fasto2 - connect \S \wp$1574 - connect \Y $1578 + connect \B \core_fasto2 + connect \S \wp$1668 + connect \Y $1672 end - process $group_627 - assign \addr_en$1577 3'000 - assign \addr_en$1577 $1578 + process $group_649 + assign \addr_en$1671 3'000 + assign \addr_en$1671 $1672 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1580 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok$142 - connect \B \fus_cu_busy_o$10 - connect \Y $1580 + connect \A \fus_fast2_ok$143 + connect \B \fus_cu_busy_o$11 + connect \Y $1674 end - process $group_628 + process $group_650 assign \wrflag_trap0_fast1_2 1'0 - assign \wrflag_trap0_fast1_2 $1580 + assign \wrflag_trap0_fast1_2 $1674 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1582 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1583 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117543,324 +226093,324 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $1583 + connect \Y $1677 end - process $group_629 - assign \wr_pick$1582 1'0 - assign \wr_pick$1582 $1583 + process $group_651 + assign \wr_pick$1676 1'0 + assign \wr_pick$1676 $1677 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1585 + wire width 1 \wr_pick_dly$1679 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1585$next - process $group_630 - assign \wr_pick_dly$1585$next \wr_pick_dly$1585 - assign \wr_pick_dly$1585$next \wr_pick$1582 + wire width 1 \wr_pick_dly$1679$next + process $group_652 + assign \wr_pick_dly$1679$next \wr_pick_dly$1679 + assign \wr_pick_dly$1679$next \wr_pick$1676 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1585$next 1'0 + assign \wr_pick_dly$1679$next 1'0 end sync init - update \wr_pick_dly$1585 1'0 + update \wr_pick_dly$1679 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1585 \wr_pick_dly$1585$next + update \wr_pick_dly$1679 \wr_pick_dly$1679$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1586 + wire width 1 $1680 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1587 + cell $not $1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1585 - connect \Y $1586 + connect \A \wr_pick_dly$1679 + connect \Y $1680 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1588 + wire width 1 $1682 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1589 + cell $and $1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1582 - connect \B $1586 - connect \Y $1588 + connect \A \wr_pick$1676 + connect \B $1680 + connect \Y $1682 end - process $group_631 - assign \wr_pick_rise$876 1'0 - assign \wr_pick_rise$876 $1588 + process $group_653 + assign \wr_pick_rise$993 1'0 + assign \wr_pick_rise$993 $1682 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1590 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1591 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1582 + connect \A \wr_pick$1676 connect \B \wrpick_FAST_fast1_en_o - connect \Y $1591 + connect \Y $1685 end - process $group_632 - assign \wp$1590 1'0 - assign \wp$1590 $1591 + process $group_654 + assign \wp$1684 1'0 + assign \wp$1684 $1685 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 3 \addr_en$1593 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 3 $1594 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 3 \addr_en$1687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 3 $1688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1689 parameter \WIDTH 3 connect \A 3'000 - connect \B \fasto2 - connect \S \wp$1590 - connect \Y $1594 + connect \B \core_fasto2 + connect \S \wp$1684 + connect \Y $1688 end - process $group_633 - assign \addr_en$1593 3'000 - assign \addr_en$1593 $1594 + process $group_655 + assign \addr_en$1687 3'000 + assign \addr_en$1687 $1688 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1596 + wire width 64 $1690 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1597 + cell $or $1691 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$143 - connect \B \fus_dest2_o$144 - connect \Y $1596 + connect \A \fus_dest1_o$144 + connect \B \fus_dest2_o$145 + connect \Y $1690 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1598 + wire width 64 $1692 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1599 + cell $or $1693 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest2_o$146 - connect \B \fus_dest3_o$147 - connect \Y $1598 + connect \A \fus_dest2_o$147 + connect \B \fus_dest3_o$148 + connect \Y $1692 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1600 + wire width 64 $1694 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1601 + cell $or $1695 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$145 - connect \B $1598 - connect \Y $1600 + connect \A \fus_dest3_o$146 + connect \B $1692 + connect \Y $1694 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1602 + wire width 64 $1696 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1603 + cell $or $1697 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $1596 - connect \B $1600 - connect \Y $1602 + connect \A $1690 + connect \B $1694 + connect \Y $1696 end - process $group_634 + process $group_656 assign \fast_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast_dest1__data_i $1602 + assign \fast_dest1__data_i $1696 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1604 + wire width 3 $1698 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1605 + cell $or $1699 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1529 - connect \B \addr_en$1545 - connect \Y $1604 + connect \A \addr_en$1623 + connect \B \addr_en$1639 + connect \Y $1698 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1606 + wire width 3 $1700 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1607 + cell $or $1701 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1577 - connect \B \addr_en$1593 - connect \Y $1606 + connect \A \addr_en$1671 + connect \B \addr_en$1687 + connect \Y $1700 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1608 + wire width 3 $1702 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1609 + cell $or $1703 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1561 - connect \B $1606 - connect \Y $1608 + connect \A \addr_en$1655 + connect \B $1700 + connect \Y $1702 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1610 + wire width 3 $1704 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1611 + cell $or $1705 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $1604 - connect \B $1608 - connect \Y $1610 + connect \A $1698 + connect \B $1702 + connect \Y $1704 end - process $group_635 + process $group_657 assign \fast_dest1__addr 3'000 - assign \fast_dest1__addr $1610 + assign \fast_dest1__addr $1704 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1612 + wire width 1 $1706 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1613 + cell $or $1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1526 - connect \B \wp$1542 - connect \Y $1612 + connect \A \wp$1620 + connect \B \wp$1636 + connect \Y $1706 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1614 + wire width 1 $1708 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1615 + cell $or $1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1574 - connect \B \wp$1590 - connect \Y $1614 + connect \A \wp$1668 + connect \B \wp$1684 + connect \Y $1708 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1616 + wire width 1 $1710 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1617 + cell $or $1711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1558 - connect \B $1614 - connect \Y $1616 + connect \A \wp$1652 + connect \B $1708 + connect \Y $1710 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1618 + wire width 1 $1712 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1619 + cell $or $1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1612 - connect \B $1616 - connect \Y $1618 + connect \A $1706 + connect \B $1710 + connect \Y $1712 end - process $group_636 + process $group_658 assign \fast_dest1__wen 1'0 - assign \fast_dest1__wen $1618 + assign \fast_dest1__wen $1712 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_nia_ok - connect \B \fus_cu_busy_o$7 - connect \Y $1620 + connect \B \fus_cu_busy_o$8 + connect \Y $1714 end - process $group_637 + process $group_659 assign \wrflag_branch0_nia_2 1'0 - assign \wrflag_branch0_nia_2 $1620 + assign \wrflag_branch0_nia_2 $1714 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1622 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$138 [2] + connect \A \fus_cu_wr__rel_o$139 [2] connect \B \fu_enable [2] - connect \Y $1622 + connect \Y $1716 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1624 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [3] + connect \A \fus_cu_wr__rel_o$87 [3] connect \B \fu_enable [3] - connect \Y $1624 + connect \Y $1718 end - process $group_638 + process $group_660 assign \wrpick_STATE_nia_i 2'00 - assign \wrpick_STATE_nia_i [0] $1622 - assign \wrpick_STATE_nia_i [1] $1624 + assign \wrpick_STATE_nia_i [0] $1716 + assign \wrpick_STATE_nia_i [1] $1718 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1626 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1627 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117868,121 +226418,121 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $1627 + connect \Y $1721 end - process $group_639 - assign \wr_pick$1626 1'0 - assign \wr_pick$1626 $1627 + process $group_661 + assign \wr_pick$1720 1'0 + assign \wr_pick$1720 $1721 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1629 + wire width 1 \wr_pick_dly$1723 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1629$next - process $group_640 - assign \wr_pick_dly$1629$next \wr_pick_dly$1629 - assign \wr_pick_dly$1629$next \wr_pick$1626 + wire width 1 \wr_pick_dly$1723$next + process $group_662 + assign \wr_pick_dly$1723$next \wr_pick_dly$1723 + assign \wr_pick_dly$1723$next \wr_pick$1720 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1629$next 1'0 + assign \wr_pick_dly$1723$next 1'0 end sync init - update \wr_pick_dly$1629 1'0 + update \wr_pick_dly$1723 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1629 \wr_pick_dly$1629$next + update \wr_pick_dly$1723 \wr_pick_dly$1723$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1630 + wire width 1 $1724 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1631 + cell $not $1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1629 - connect \Y $1630 + connect \A \wr_pick_dly$1723 + connect \Y $1724 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1632 + wire width 1 $1726 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1633 + cell $and $1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1626 - connect \B $1630 - connect \Y $1632 + connect \A \wr_pick$1720 + connect \B $1724 + connect \Y $1726 end - process $group_641 - assign \wr_pick_rise$1525 1'0 - assign \wr_pick_rise$1525 $1632 + process $group_663 + assign \wr_pick_rise$1619 1'0 + assign \wr_pick_rise$1619 $1726 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1634 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1635 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1626 + connect \A \wr_pick$1720 connect \B \wrpick_STATE_nia_en_o - connect \Y $1635 + connect \Y $1729 end - process $group_642 - assign \wp$1634 1'0 - assign \wp$1634 $1635 + process $group_664 + assign \wp$1728 1'0 + assign \wp$1728 $1729 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 1 \addr_en$1637 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 1 $1638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 1 \addr_en$1731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 1 $1732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1733 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1634 - connect \Y $1638 + connect \S \wp$1728 + connect \Y $1732 end - process $group_643 - assign \addr_en$1637 1'0 - assign \addr_en$1637 $1638 + process $group_665 + assign \addr_en$1731 1'0 + assign \addr_en$1731 $1732 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1640 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_nia_ok$148 - connect \B \fus_cu_busy_o$10 - connect \Y $1640 + connect \A \fus_nia_ok$149 + connect \B \fus_cu_busy_o$11 + connect \Y $1734 end - process $group_644 + process $group_666 assign \wrflag_trap0_nia_3 1'0 - assign \wrflag_trap0_nia_3 $1640 + assign \wrflag_trap0_nia_3 $1734 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1642 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -117990,185 +226540,185 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $1643 + connect \Y $1737 end - process $group_645 - assign \wr_pick$1642 1'0 - assign \wr_pick$1642 $1643 + process $group_667 + assign \wr_pick$1736 1'0 + assign \wr_pick$1736 $1737 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1645 + wire width 1 \wr_pick_dly$1739 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1645$next - process $group_646 - assign \wr_pick_dly$1645$next \wr_pick_dly$1645 - assign \wr_pick_dly$1645$next \wr_pick$1642 + wire width 1 \wr_pick_dly$1739$next + process $group_668 + assign \wr_pick_dly$1739$next \wr_pick_dly$1739 + assign \wr_pick_dly$1739$next \wr_pick$1736 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1645$next 1'0 + assign \wr_pick_dly$1739$next 1'0 end sync init - update \wr_pick_dly$1645 1'0 + update \wr_pick_dly$1739 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1645 \wr_pick_dly$1645$next + update \wr_pick_dly$1739 \wr_pick_dly$1739$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1646 + wire width 1 $1740 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1647 + cell $not $1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1645 - connect \Y $1646 + connect \A \wr_pick_dly$1739 + connect \Y $1740 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1648 + wire width 1 $1742 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1649 + cell $and $1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1642 - connect \B $1646 - connect \Y $1648 + connect \A \wr_pick$1736 + connect \B $1740 + connect \Y $1742 end - process $group_647 - assign \wr_pick_rise$877 1'0 - assign \wr_pick_rise$877 $1648 + process $group_669 + assign \wr_pick_rise$994 1'0 + assign \wr_pick_rise$994 $1742 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1650 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1651 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1642 + connect \A \wr_pick$1736 connect \B \wrpick_STATE_nia_en_o - connect \Y $1651 + connect \Y $1745 end - process $group_648 - assign \wp$1650 1'0 - assign \wp$1650 $1651 + process $group_670 + assign \wp$1744 1'0 + assign \wp$1744 $1745 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 1 \addr_en$1653 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 1 $1654 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 1 \addr_en$1747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 1 $1748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1749 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1650 - connect \Y $1654 + connect \S \wp$1744 + connect \Y $1748 end - process $group_649 - assign \addr_en$1653 1'0 - assign \addr_en$1653 $1654 + process $group_671 + assign \addr_en$1747 1'0 + assign \addr_en$1747 $1748 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1656 + wire width 64 $1750 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1657 + cell $or $1751 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$149 - connect \B \fus_dest4_o$150 - connect \Y $1656 + connect \A \fus_dest3_o$150 + connect \B \fus_dest4_o$151 + connect \Y $1750 end - process $group_650 + process $group_672 assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i $1656 + assign \state_data_i $1750 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1658 + wire width 4 $1752 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1659 + wire width 1 $1753 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1660 + cell $or $1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1637 - connect \B \addr_en$1653 - connect \Y $1659 + connect \A \addr_en$1731 + connect \B \addr_en$1747 + connect \Y $1753 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $1661 + cell $pos $1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A $1659 - connect \Y $1658 + parameter \Y_WIDTH 4 + connect \A $1753 + connect \Y $1752 end - process $group_651 - assign \state_nia_wen 2'00 - assign \state_nia_wen $1658 + process $group_673 + assign \state_nia_wen 4'0000 + assign \state_nia_wen $1752 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1662 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_msr_ok - connect \B \fus_cu_busy_o$10 - connect \Y $1662 + connect \B \fus_cu_busy_o$11 + connect \Y $1756 end - process $group_652 + process $group_674 assign \wrflag_trap0_msr_4 1'0 - assign \wrflag_trap0_msr_4 $1662 + assign \wrflag_trap0_msr_4 $1756 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1664 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [4] + connect \A \fus_cu_wr__rel_o$87 [4] connect \B \fu_enable [3] - connect \Y $1664 + connect \Y $1758 end - process $group_653 + process $group_675 assign \wrpick_STATE_msr_i 1'0 - assign \wrpick_STATE_msr_i $1664 + assign \wrpick_STATE_msr_i $1758 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1666 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1667 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -118176,149 +226726,159 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $1667 + connect \Y $1761 end - process $group_654 - assign \wr_pick$1666 1'0 - assign \wr_pick$1666 $1667 + process $group_676 + assign \wr_pick$1760 1'0 + assign \wr_pick$1760 $1761 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1669 + wire width 1 \wr_pick_dly$1763 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1669$next - process $group_655 - assign \wr_pick_dly$1669$next \wr_pick_dly$1669 - assign \wr_pick_dly$1669$next \wr_pick$1666 + wire width 1 \wr_pick_dly$1763$next + process $group_677 + assign \wr_pick_dly$1763$next \wr_pick_dly$1763 + assign \wr_pick_dly$1763$next \wr_pick$1760 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1669$next 1'0 + assign \wr_pick_dly$1763$next 1'0 end sync init - update \wr_pick_dly$1669 1'0 + update \wr_pick_dly$1763 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1669 \wr_pick_dly$1669$next + update \wr_pick_dly$1763 \wr_pick_dly$1763$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1670 + wire width 1 $1764 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1671 + cell $not $1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1669 - connect \Y $1670 + connect \A \wr_pick_dly$1763 + connect \Y $1764 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1672 + wire width 1 $1766 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1673 + cell $and $1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1666 - connect \B $1670 - connect \Y $1672 + connect \A \wr_pick$1760 + connect \B $1764 + connect \Y $1766 end - process $group_656 - assign \wr_pick_rise$878 1'0 - assign \wr_pick_rise$878 $1672 + process $group_678 + assign \wr_pick_rise$995 1'0 + assign \wr_pick_rise$995 $1766 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1674 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1666 + connect \A \wr_pick$1760 connect \B \wrpick_STATE_msr_en_o - connect \Y $1675 + connect \Y $1769 end - process $group_657 - assign \wp$1674 1'0 - assign \wp$1674 $1675 + process $group_679 + assign \wp$1768 1'0 + assign \wp$1768 $1769 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 2 \addr_en$1677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 2 $1678 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 2 \addr_en$1771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 2 $1772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1773 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1674 - connect \Y $1678 + connect \S \wp$1768 + connect \Y $1772 end - process $group_658 - assign \addr_en$1677 2'00 - assign \addr_en$1677 $1678 + process $group_680 + assign \addr_en$1771 2'00 + assign \addr_en$1771 $1772 sync init end - process $group_659 - assign \state_data_i$157 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i$157 \fus_dest5_o$151 + process $group_681 + assign \state_data_i$158 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \state_data_i$158 \fus_dest5_o$152 sync init end - process $group_660 - assign \state_wen 2'00 - assign \state_wen \addr_en$1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 4 $1774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + cell $pos $1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 4 + connect \A \addr_en$1771 + connect \Y $1774 + end + process $group_682 + assign \state_wen 4'0000 + assign \state_wen $1774 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" wire width 1 \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1680 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + wire width 1 $1776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" + cell $and $1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_spr1_ok - connect \B \fus_cu_busy_o$16 - connect \Y $1680 + connect \B \fus_cu_busy_o$17 + connect \Y $1776 end - process $group_661 + process $group_683 assign \wrflag_spr0_spr1_1 1'0 - assign \wrflag_spr0_spr1_1 $1680 + assign \wrflag_spr0_spr1_1 $1776 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1682 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + wire width 1 $1778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" + cell $and $1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [1] + connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [5] - connect \Y $1682 + connect \Y $1778 end - process $group_662 + process $group_684 assign \wrpick_SPR_spr1_i 1'0 - assign \wrpick_SPR_spr1_i $1682 + assign \wrpick_SPR_spr1_i $1778 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" - wire width 1 \wr_pick$1684 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - wire width 1 $1685 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" - cell $and $1686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire width 1 \wr_pick$1780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire width 1 $1781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + cell $and $1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -118326,111 +226886,111 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $1685 + connect \Y $1781 end - process $group_663 - assign \wr_pick$1684 1'0 - assign \wr_pick$1684 $1685 + process $group_685 + assign \wr_pick$1780 1'0 + assign \wr_pick$1780 $1781 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1687 + wire width 1 \wr_pick_dly$1783 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1687$next - process $group_664 - assign \wr_pick_dly$1687$next \wr_pick_dly$1687 - assign \wr_pick_dly$1687$next \wr_pick$1684 + wire width 1 \wr_pick_dly$1783$next + process $group_686 + assign \wr_pick_dly$1783$next \wr_pick_dly$1783 + assign \wr_pick_dly$1783$next \wr_pick$1780 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \wr_pick_dly$1687$next 1'0 + assign \wr_pick_dly$1783$next 1'0 end sync init - update \wr_pick_dly$1687 1'0 + update \wr_pick_dly$1783 1'0 sync posedge \coresync_clk - update \wr_pick_dly$1687 \wr_pick_dly$1687$next + update \wr_pick_dly$1783 \wr_pick_dly$1783$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1688 + wire width 1 $1784 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1689 + cell $not $1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1687 - connect \Y $1688 + connect \A \wr_pick_dly$1783 + connect \Y $1784 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1690 + wire width 1 $1786 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1691 + cell $and $1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1684 - connect \B $1688 - connect \Y $1690 + connect \A \wr_pick$1780 + connect \B $1784 + connect \Y $1786 end - process $group_665 - assign \wr_pick_rise$919 1'0 - assign \wr_pick_rise$919 $1690 + process $group_687 + assign \wr_pick_rise$1035 1'0 + assign \wr_pick_rise$1035 $1786 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" - wire width 1 \wp$1692 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - wire width 1 $1693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" - cell $and $1694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire width 1 \wp$1788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire width 1 $1789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + cell $and $1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1684 + connect \A \wr_pick$1780 connect \B \wrpick_SPR_spr1_en_o - connect \Y $1693 + connect \Y $1789 end - process $group_666 - assign \wp$1692 1'0 - assign \wp$1692 $1693 + process $group_688 + assign \wp$1788 1'0 + assign \wp$1788 $1789 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" - wire width 10 \addr_en$1695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - wire width 10 $1696 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" - cell $mux $1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + wire width 10 \addr_en$1791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire width 10 $1792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $1793 parameter \WIDTH 10 connect \A 10'0000000000 - connect \B \spro - connect \S \wp$1692 - connect \Y $1696 + connect \B \core_spro + connect \S \wp$1788 + connect \Y $1792 end - process $group_667 - assign \addr_en$1695 10'0000000000 - assign \addr_en$1695 $1696 + process $group_689 + assign \addr_en$1791 10'0000000000 + assign \addr_en$1791 $1792 sync init end - process $group_668 + process $group_690 assign \spr_spr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_spr1__data_i \fus_dest2_o$152 + assign \spr_spr1__data_i \fus_dest2_o$153 sync init end - process $group_669 - assign \spr_spr1__addr$158 7'0000000 - assign \spr_spr1__addr$158 \addr_en$1695 [6:0] + process $group_691 + assign \spr_spr1__addr$159 7'0000000 + assign \spr_spr1__addr$159 \addr_en$1791 [6:0] sync init end - process $group_670 + process $group_692 assign \spr_spr1__wen 1'0 - assign \spr_spr1__wen \wp$1692 + assign \spr_spr1__wen \wp$1788 sync init end - process $group_671 + process $group_693 assign \coresync_rst 1'0 assign \coresync_rst \core_reset_i sync init @@ -118441,7 +227001,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.imem" module \imem - attribute \src "simple/issuer.py:101" + attribute \src "simple/issuer.py:140" wire width 1 input 0 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 input 1 \a_pc_i @@ -118453,7 +227013,7 @@ module \imem wire width 1 output 4 \f_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" wire width 64 output 5 \f_instr_o - attribute \src "simple/issuer.py:101" + attribute \src "simple/issuer.py:140" wire width 1 input 6 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 1 output 7 \ibus__cyc @@ -119000,222 +227560,251 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dbg" module \dbg - attribute \src "simple/issuer.py:101" + attribute \src "simple/issuer.py:140" wire width 1 input 0 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:90" wire width 1 output 1 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:94" wire width 1 input 2 \terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 input 3 \core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" wire width 64 input 4 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:89" wire width 1 output 5 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" wire width 1 input 6 \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66" - wire width 1 output 7 \dbg_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 7 output 8 \dbg_gpr_addr + wire width 1 output 7 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:70" + wire width 7 output 8 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 input 9 \d_gpr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 64 input 9 \dbg_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67" - wire width 1 input 10 \dbg_gpr_ack - attribute \src "simple/issuer.py:101" - wire width 1 input 11 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire width 1 output 12 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55" - wire width 4 input 13 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 1 input 14 \dmi_req_i + wire width 1 input 10 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire width 1 output 11 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 input 12 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire width 1 input 13 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire width 1 output 14 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 input 15 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire width 1 input 16 \d_xer_ack + attribute \src "simple/issuer.py:140" + wire width 1 input 17 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 64 output 15 \dmi_dout + wire width 4 input 18 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire width 1 output 19 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire width 1 input 20 \dmi_req_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 1 input 16 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56" - wire width 64 input 17 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - cell $eq $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'101 - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - cell $mux $4 - parameter \WIDTH 1 - connect \A \dmi_req_i - connect \B \dbg_gpr_ack - connect \S $2 - connect \Y $1 - end + wire width 64 output 21 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire width 1 input 22 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 23 \dmi_din process $group_0 assign \dmi_ack_o 1'0 - assign \dmi_ack_o $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + case 4'0101 + assign \dmi_ack_o \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" + case 4'1000 + assign \dmi_ack_o \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" + case 4'1001 + assign \dmi_ack_o \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" + case + assign \dmi_ack_o \dmi_req_i + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - cell $eq $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'101 - connect \Y $6 + process $group_1 + assign \d_gpr_req 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + case 4'0101 + assign \d_gpr_req \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" + case + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - cell $mux $8 - parameter \WIDTH 1 - connect \A 1'0 - connect \B \dmi_req_i - connect \S $6 - connect \Y $5 + process $group_2 + assign \d_cr_req 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" + case 4'1000 + assign \d_cr_req \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" + case + end + sync init end - process $group_1 - assign \dbg_gpr_req 1'0 - assign \dbg_gpr_req $5 + process $group_3 + assign \d_xer_req 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" + case 4'1001 + assign \d_xer_req \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" + case + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:126" wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" wire width 1 \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" wire width 1 \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" wire width 1 \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" wire width 1 \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - cell $pos $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" + cell $pos $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 64 connect \A { \terminated \core_stopped_i \stopping } - connect \Y $9 + connect \Y $1 end - process $group_2 + process $group_4 assign \stat_reg 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \stat_reg $9 + assign \stat_reg $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:111" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" wire width 64 \log_dmi_data - process $group_3 + process $group_5 assign \dmi_dout 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:166" case 4'0001 assign \dmi_dout \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:168" case 4'0010 assign \dmi_dout \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" case 4'0011 assign \dmi_dout \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" case 4'0101 - assign \dmi_dout \dbg_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + assign \dmi_dout \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" case 4'0110 assign \dmi_dout { \log_write_addr_o \log_dmi_addr } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:176" case 4'0111 assign \dmi_dout \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:178" + case 4'1000 + assign \dmi_dout \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" + case 4'1001 + assign \dmi_dout \d_xer_data end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" wire width 1 \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" wire width 1 \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire width 1 \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire width 1 \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $11 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $11 - connect \Y $13 + connect \B $3 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire width 1 \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire width 1 \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" wire width 1 \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" wire width 1 \dmi_read_log_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $15 + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $15 - connect \Y $17 + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $12 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119223,12 +227812,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $19 + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $14 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119236,12 +227825,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $21 + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $16 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119249,38 +227838,38 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $23 + connect \Y $15 end - process $group_4 + process $group_6 assign \do_step$next \do_step assign \do_step$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $17 $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $9 $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $23 $21 $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $15 $13 $11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" switch { \dmi_din [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" case 1'1 assign \do_step$next 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -119293,60 +227882,60 @@ module \dbg sync posedge \clk update \do_step \do_step$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" wire width 1 \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" wire width 1 \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $25 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $25 - connect \Y $27 + connect \B $17 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $29 + connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $29 - connect \Y $31 + connect \B $21 + connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $26 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119354,12 +227943,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $33 + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119367,12 +227956,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $35 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $30 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119380,38 +227969,38 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $37 + connect \Y $29 end - process $group_5 + process $group_7 assign \do_reset$next \do_reset assign \do_reset$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $31 $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $23 $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $37 $35 $33 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $29 $27 $25 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" switch { \dmi_din [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" case 1'1 assign \do_reset$next 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -119424,60 +228013,60 @@ module \dbg sync posedge \clk update \do_reset \do_reset$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire width 1 \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire width 1 \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $39 + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $39 - connect \Y $41 + connect \B $31 + connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $43 + connect \Y $35 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $43 - connect \Y $45 + connect \B $35 + connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $40 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119485,12 +228074,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $47 + connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $42 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119498,12 +228087,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $49 + connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119511,38 +228100,38 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $51 + connect \Y $43 end - process $group_6 + process $group_8 assign \do_icreset$next \do_icreset assign \do_icreset$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $45 $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $37 $33 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $51 $49 $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $43 $41 $39 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" switch { \dmi_din [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" case 1'1 assign \do_icreset$next 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -119555,60 +228144,60 @@ module \dbg sync posedge \clk update \do_icreset \do_icreset$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" wire width 1 \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" wire width 1 \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $53 + connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $53 - connect \Y $55 + connect \B $45 + connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $57 + connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $57 - connect \Y $59 + connect \B $49 + connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $54 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119616,12 +228205,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $61 + connect \Y $53 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $56 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119629,12 +228218,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $63 + connect \Y $55 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $58 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119642,33 +228231,33 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $65 + connect \Y $57 end - process $group_7 + process $group_9 assign \do_dmi_log_rd$next \do_dmi_log_rd assign \do_dmi_log_rd$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $59 $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $51 $47 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $65 $63 $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $57 $55 $53 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- assign \do_dmi_log_rd$next 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- assign \do_dmi_log_rd$next 1'1 end @@ -119682,7 +228271,7 @@ module \dbg sync posedge \clk update \do_dmi_log_rd \do_dmi_log_rd$next end - process $group_8 + process $group_10 assign \dmi_req_i_1$next \dmi_req_i_1 assign \dmi_req_i_1$next \dmi_req_i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -119695,56 +228284,56 @@ module \dbg sync posedge \clk update \dmi_req_i_1 \dmi_req_i_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $67 + connect \Y $59 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $67 - connect \Y $69 + connect \B $59 + connect \Y $61 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $71 + connect \Y $63 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $71 - connect \Y $73 + connect \B $63 + connect \Y $65 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $68 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119752,12 +228341,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $75 + connect \Y $67 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $70 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119765,12 +228354,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $77 + connect \Y $69 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $72 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119778,54 +228367,54 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $79 + connect \Y $71 end - process $group_9 + process $group_11 assign \terminated$next \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $73 $69 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $65 $61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $79 $77 $75 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $71 $69 $67 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" switch { \dmi_din [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" case 1'1 assign \terminated$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" switch { \dmi_din [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" case 1'1 assign \terminated$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \dmi_din [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" case 1'1 assign \terminated$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" switch { \terminate_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" case 1'1 assign \terminated$next 1'1 end @@ -119839,56 +228428,56 @@ module \dbg sync posedge \clk update \terminated \terminated$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $81 + connect \Y $73 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $81 - connect \Y $83 + connect \B $73 + connect \Y $75 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $85 + connect \Y $77 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $85 - connect \Y $87 + connect \B $77 + connect \Y $79 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $82 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119896,12 +228485,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $89 + connect \Y $81 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $84 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119909,12 +228498,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $91 + connect \Y $83 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $86 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -119922,48 +228511,48 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $93 + connect \Y $85 end - process $group_10 + process $group_12 assign \stopping$next \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $87 $83 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $79 $75 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $93 $91 $89 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $85 $83 $81 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \dmi_din [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" case 1'1 assign \stopping$next 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \dmi_din [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" case 1'1 assign \stopping$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" switch { \terminate_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" case 1'1 assign \stopping$next 1'1 end @@ -119977,60 +228566,60 @@ module \dbg sync posedge \clk update \stopping \stopping$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $95 + connect \Y $87 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $95 - connect \Y $97 + connect \B $87 + connect \Y $89 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $99 + connect \Y $91 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $99 - connect \Y $101 + connect \B $91 + connect \Y $93 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $96 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120038,12 +228627,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $103 + connect \Y $95 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $98 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120051,12 +228640,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $105 + connect \Y $97 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120064,32 +228653,32 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $107 + connect \Y $99 end - process $group_11 + process $group_13 assign \gspr_index$next \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $101 $97 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $93 $89 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $107 $105 $103 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $99 $97 $95 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- assign \gspr_index$next \dmi_din [6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -120102,56 +228691,56 @@ module \dbg sync posedge \clk update \gspr_index \gspr_index$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $109 + connect \Y $101 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $109 - connect \Y $111 + connect \B $101 + connect \Y $103 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $113 + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 - connect \B $113 - connect \Y $115 + connect \B $105 + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $110 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120159,12 +228748,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $117 + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120172,12 +228761,12 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $119 + connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $114 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120185,14 +228774,14 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $121 + connect \Y $113 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - wire width 3 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - wire width 3 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - cell $add $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" + wire width 3 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" + wire width 3 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" + cell $add $117 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -120200,35 +228789,35 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $124 + connect \Y $116 end - connect $123 $124 - process $group_12 + connect $115 $116 + process $group_14 assign \log_dmi_addr$next \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $115 $111 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { $107 $103 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $121 $119 $117 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { $113 $111 $109 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" case 3'1-- assign \log_dmi_addr$next \dmi_din [31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" case 2'1- - assign \log_dmi_addr$next [1:0] $123 [1:0] + assign \log_dmi_addr$next [1:0] $115 [1:0] end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -120240,7 +228829,7 @@ module \dbg sync posedge \clk update \log_dmi_addr \log_dmi_addr$next end - process $group_13 + process $group_15 assign \dmi_read_log_data_1$next \dmi_read_log_data_1 assign \dmi_read_log_data_1$next \dmi_read_log_data attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -120253,10 +228842,10 @@ module \dbg sync posedge \clk update \dmi_read_log_data_1 \dmi_read_log_data_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - cell $eq $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire width 1 $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $eq $119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -120264,24 +228853,24 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $126 + connect \Y $118 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - cell $and $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire width 1 $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i - connect \B $126 - connect \Y $128 + connect \B $118 + connect \Y $120 end - process $group_14 + process $group_16 assign \dmi_read_log_data$next \dmi_read_log_data - assign \dmi_read_log_data$next $128 + assign \dmi_read_log_data$next $120 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -120292,54 +228881,54 @@ module \dbg sync posedge \clk update \dmi_read_log_data \dmi_read_log_data$next end - process $group_15 - assign \dbg_gpr_addr 7'0000000 - assign \dbg_gpr_addr \gspr_index + process $group_17 + assign \d_gpr_addr 7'0000000 + assign \d_gpr_addr \gspr_index sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - cell $not $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" + wire width 1 $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" + cell $not $123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $130 + connect \Y $122 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - cell $and $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" + wire width 1 $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" + cell $and $125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \stopping - connect \B $130 - connect \Y $132 + connect \B $122 + connect \Y $124 end - process $group_16 + process $group_18 assign \core_stop_o 1'0 - assign \core_stop_o $132 + assign \core_stop_o $124 sync init end - process $group_17 + process $group_19 assign \core_rst_o 1'0 assign \core_rst_o \do_reset sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:91" wire width 1 \icache_rst_o - process $group_18 + process $group_20 assign \icache_rst_o 1'0 assign \icache_rst_o \do_icreset sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" wire width 1 \terminated_o - process $group_19 + process $group_21 assign \terminated_o 1'0 assign \terminated_o \terminated sync init @@ -120350,7 +228939,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" module \dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -120364,40 +228953,8 @@ module \dec19 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -120471,16 +229028,50 @@ module \dec19 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -120496,21 +229087,21 @@ module \dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -120519,301 +229110,299 @@ module \dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 10 \opcode_switch process $group_0 assign \opcode_switch 10'0000000000 assign \opcode_switch \opcode_in [10:1] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch$1 process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \function_unit 11'00010000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00000000010 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 - assign \form 5'01001 + assign \internal_op 7'1000110 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'00111 + assign \internal_op 7'0000000 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 - assign \internal_op 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 - assign \internal_op 7'0100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 - assign \internal_op 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 - assign \internal_op 7'1000110 + assign \form 5'01001 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0000000 + assign \form 5'00111 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \in1_sel 3'011 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'000 end @@ -120821,57 +229410,57 @@ module \dec19 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \in2_sel 4'1100 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0000 end @@ -120879,57 +229468,57 @@ module \dec19 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \in3_sel 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 end @@ -120937,57 +229526,57 @@ module \dec19 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \out_sel 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'00 end @@ -120995,57 +229584,57 @@ module \dec19 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \cr_in 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \cr_in 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 end @@ -121053,57 +229642,57 @@ module \dec19 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \cr_out 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 end @@ -121111,57 +229700,57 @@ module \dec19 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \ldst_len 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 end @@ -121169,57 +229758,57 @@ module \dec19 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \upd 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 end @@ -121227,57 +229816,57 @@ module \dec19 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \rc_sel 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'10 end @@ -121285,57 +229874,57 @@ module \dec19 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \cry_in 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 end @@ -121343,51 +229932,51 @@ module \dec19 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 - assign \asmcode 8'01101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \asmcode 8'00100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \asmcode 8'00100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \asmcode 8'00100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \asmcode 8'00101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \asmcode 8'00101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \asmcode 8'00101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \asmcode 8'00101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \asmcode 8'00101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \asmcode 8'00010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \asmcode 8'00010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \asmcode 8'00011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \asmcode 8'01001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 - assign \asmcode 8'10010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \asmcode 8'01001000 end @@ -121395,57 +229984,57 @@ module \dec19 end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \inv_a 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 end @@ -121453,57 +230042,57 @@ module \dec19 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \inv_out 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 end @@ -121511,57 +230100,57 @@ module \dec19 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \cry_out 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 end @@ -121569,57 +230158,57 @@ module \dec19 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \br 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 end @@ -121627,57 +230216,57 @@ module \dec19 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \sgn_ext 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 end @@ -121685,57 +230274,57 @@ module \dec19 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \rsrv 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 end @@ -121743,57 +230332,57 @@ module \dec19 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \is_32b 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 end @@ -121801,57 +230390,57 @@ module \dec19 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \sgn 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 end @@ -121859,57 +230448,57 @@ module \dec19 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \lk 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 end @@ -121917,57 +230506,57 @@ module \dec19 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000000000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100000001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010000001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100100001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011100001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000100001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0111000001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0110100001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0011000001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000010000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'1000110000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0010010110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0000010010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 10'0100010010 assign \sgl_pipe 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 end @@ -121982,7 +230571,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" module \dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -121996,40 +230585,8 @@ module \dec30 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -122103,16 +230660,50 @@ module \dec30 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -122128,21 +230719,21 @@ module \dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -122151,66 +230742,64 @@ module \dec30 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 4 \opcode_switch process $group_0 assign \opcode_switch 4'0000 @@ -122219,147 +230808,147 @@ module \dec30 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \function_unit 11'00000001000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 - assign \form 5'10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 - assign \form 5'10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 - assign \form 5'10100 + assign \internal_op 7'0111010 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 - assign \internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 - assign \internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 - assign \internal_op 7'0111010 + assign \form 5'10100 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \in1_sel 3'000 end @@ -122367,36 +230956,36 @@ module \dec30 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \in2_sel 4'0001 end @@ -122404,36 +230993,36 @@ module \dec30 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \in3_sel 2'01 end @@ -122441,36 +231030,36 @@ module \dec30 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \out_sel 2'10 end @@ -122478,36 +231067,36 @@ module \dec30 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \cr_in 3'000 end @@ -122515,36 +231104,36 @@ module \dec30 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \cr_out 3'001 end @@ -122552,36 +231141,36 @@ module \dec30 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \ldst_len 4'0000 end @@ -122589,36 +231178,36 @@ module \dec30 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \upd 2'00 end @@ -122626,36 +231215,36 @@ module \dec30 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \rc_sel 2'10 end @@ -122663,36 +231252,36 @@ module \dec30 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \cry_in 2'00 end @@ -122700,73 +231289,73 @@ module \dec30 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 - assign \asmcode 8'10010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 - assign \asmcode 8'10010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 4'0000 assign \asmcode 8'10010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0000 + assign \asmcode 8'10010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 - assign \asmcode 8'10010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 4'0010 assign \asmcode 8'10010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0010 + assign \asmcode 8'10010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 - assign \asmcode 8'10010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 4'0110 assign \asmcode 8'10010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'0110 + assign \asmcode 8'10010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 - assign \asmcode 8'10010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 - assign \asmcode 8'10010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 4'1001 assign \asmcode 8'10010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 4'1001 + assign \asmcode 8'10010011 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \inv_a 1'0 end @@ -122774,36 +231363,36 @@ module \dec30 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \inv_out 1'0 end @@ -122811,36 +231400,36 @@ module \dec30 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \cry_out 1'0 end @@ -122848,36 +231437,36 @@ module \dec30 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \br 1'0 end @@ -122885,36 +231474,36 @@ module \dec30 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \sgn_ext 1'0 end @@ -122922,36 +231511,36 @@ module \dec30 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \rsrv 1'0 end @@ -122959,36 +231548,36 @@ module \dec30 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \is_32b 1'0 end @@ -122996,36 +231585,36 @@ module \dec30 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \sgn 1'0 end @@ -123033,36 +231622,36 @@ module \dec30 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \lk 1'0 end @@ -123070,36 +231659,36 @@ module \dec30 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'0111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 4'1001 assign \sgl_pipe 1'0 end @@ -123109,7 +231698,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub10" module \dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -123123,40 +231712,8 @@ module \dec_sub10 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -123230,16 +231787,50 @@ module \dec_sub10 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -123255,21 +231846,21 @@ module \dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -123278,66 +231869,64 @@ module \dec_sub10 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -123346,147 +231935,147 @@ module \dec_sub10 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \function_unit 11'00000000010 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \form 5'10001 + assign \internal_op 7'0000010 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \internal_op 7'0000010 + assign \form 5'10001 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in1_sel 3'001 end @@ -123494,36 +232083,36 @@ module \dec_sub10 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in2_sel 4'0000 end @@ -123531,36 +232120,36 @@ module \dec_sub10 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in3_sel 2'00 end @@ -123568,36 +232157,36 @@ module \dec_sub10 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \out_sel 2'01 end @@ -123605,36 +232194,36 @@ module \dec_sub10 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_in 3'000 end @@ -123642,36 +232231,36 @@ module \dec_sub10 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_out 3'001 end @@ -123679,36 +232268,36 @@ module \dec_sub10 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \ldst_len 4'0000 end @@ -123716,36 +232305,36 @@ module \dec_sub10 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \upd 2'00 end @@ -123753,36 +232342,36 @@ module \dec_sub10 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rc_sel 2'10 end @@ -123790,36 +232379,36 @@ module \dec_sub10 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_in 2'10 end @@ -123827,36 +232416,36 @@ module \dec_sub10 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \asmcode 8'00000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \asmcode 8'00001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'00000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \asmcode 8'00000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \asmcode 8'00000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \asmcode 8'00000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \asmcode 8'00001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \asmcode 8'00001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \asmcode 8'00001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \asmcode 8'00001110 end @@ -123864,36 +232453,36 @@ module \dec_sub10 end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_a 1'0 end @@ -123901,36 +232490,36 @@ module \dec_sub10 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_out 1'0 end @@ -123938,36 +232527,36 @@ module \dec_sub10 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_out 1'1 end @@ -123975,36 +232564,36 @@ module \dec_sub10 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \br 1'0 end @@ -124012,36 +232601,36 @@ module \dec_sub10 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn_ext 1'0 end @@ -124049,36 +232638,36 @@ module \dec_sub10 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rsrv 1'0 end @@ -124086,36 +232675,36 @@ module \dec_sub10 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \is_32b 1'0 end @@ -124123,36 +232712,36 @@ module \dec_sub10 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn 1'0 end @@ -124160,36 +232749,36 @@ module \dec_sub10 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \lk 1'0 end @@ -124197,36 +232786,36 @@ module \dec_sub10 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgl_pipe 1'0 end @@ -124236,7 +232825,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub28" module \dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -124250,40 +232839,8 @@ module \dec_sub28 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -124357,16 +232914,50 @@ module \dec_sub28 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -124382,21 +232973,21 @@ module \dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -124405,66 +232996,64 @@ module \dec_sub28 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -124473,147 +233062,147 @@ module \dec_sub28 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \function_unit 11'00000010000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 - assign \form 5'01000 + assign \internal_op 7'1000011 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \internal_op 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 - assign \internal_op 7'1000011 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in1_sel 3'100 end @@ -124621,36 +233210,36 @@ module \dec_sub28 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in2_sel 4'0001 end @@ -124658,36 +233247,36 @@ module \dec_sub28 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in3_sel 2'00 end @@ -124695,36 +233284,36 @@ module \dec_sub28 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \out_sel 2'10 end @@ -124732,36 +233321,36 @@ module \dec_sub28 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cr_in 3'000 end @@ -124769,36 +233358,36 @@ module \dec_sub28 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cr_out 3'001 end @@ -124806,36 +233395,36 @@ module \dec_sub28 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \ldst_len 4'0000 end @@ -124843,36 +233432,36 @@ module \dec_sub28 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \upd 2'00 end @@ -124880,36 +233469,36 @@ module \dec_sub28 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \rc_sel 2'10 end @@ -124917,36 +233506,36 @@ module \dec_sub28 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cry_in 2'00 end @@ -124954,73 +233543,73 @@ module \dec_sub28 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'00001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'00010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \asmcode 8'00011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \asmcode 8'00011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \asmcode 8'01000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \asmcode 8'10000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \asmcode 8'10000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01101 assign \asmcode 8'10000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 assign \asmcode 8'10001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \asmcode 8'10001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 - assign \asmcode 8'11001011 + assign \asmcode 8'11001101 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \inv_a 1'0 end @@ -125028,36 +233617,36 @@ module \dec_sub28 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \inv_out 1'0 end @@ -125065,36 +233654,36 @@ module \dec_sub28 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cry_out 1'0 end @@ -125102,36 +233691,36 @@ module \dec_sub28 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \br 1'0 end @@ -125139,36 +233728,36 @@ module \dec_sub28 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgn_ext 1'0 end @@ -125176,36 +233765,36 @@ module \dec_sub28 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \rsrv 1'0 end @@ -125213,36 +233802,36 @@ module \dec_sub28 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \is_32b 1'0 end @@ -125250,36 +233839,36 @@ module \dec_sub28 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgn 1'0 end @@ -125287,36 +233876,36 @@ module \dec_sub28 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \lk 1'0 end @@ -125324,36 +233913,36 @@ module \dec_sub28 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgl_pipe 1'0 end @@ -125363,7 +233952,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub0" module \dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -125377,40 +233966,8 @@ module \dec_sub0 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -125484,16 +234041,50 @@ module \dec_sub0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -125509,21 +234100,21 @@ module \dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -125532,66 +234123,64 @@ module \dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -125600,75 +234189,75 @@ module \dec_sub0 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00001000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'11000 + assign \internal_op 7'0111011 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0111011 + assign \form 5'11000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'000 end @@ -125676,18 +234265,18 @@ module \dec_sub0 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0000 end @@ -125695,18 +234284,18 @@ module \dec_sub0 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 end @@ -125714,18 +234303,18 @@ module \dec_sub0 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'01 end @@ -125733,18 +234322,18 @@ module \dec_sub0 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'011 end @@ -125752,18 +234341,18 @@ module \dec_sub0 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 end @@ -125771,18 +234360,18 @@ module \dec_sub0 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0000 end @@ -125790,18 +234379,18 @@ module \dec_sub0 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 end @@ -125809,18 +234398,18 @@ module \dec_sub0 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 end @@ -125828,18 +234417,18 @@ module \dec_sub0 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 end @@ -125847,37 +234436,37 @@ module \dec_sub0 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'00011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \asmcode 8'00011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'00011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'10011010 + assign \asmcode 8'10011011 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 end @@ -125885,18 +234474,18 @@ module \dec_sub0 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 end @@ -125904,18 +234493,18 @@ module \dec_sub0 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 end @@ -125923,18 +234512,18 @@ module \dec_sub0 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 end @@ -125942,18 +234531,18 @@ module \dec_sub0 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 end @@ -125961,18 +234550,18 @@ module \dec_sub0 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 end @@ -125980,18 +234569,18 @@ module \dec_sub0 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 end @@ -125999,18 +234588,18 @@ module \dec_sub0 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 end @@ -126018,18 +234607,18 @@ module \dec_sub0 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 end @@ -126037,18 +234626,18 @@ module \dec_sub0 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'0 end @@ -126058,7 +234647,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub26" module \dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -126072,40 +234661,8 @@ module \dec_sub26 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -126179,16 +234736,50 @@ module \dec_sub26 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -126204,21 +234795,21 @@ module \dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -126227,66 +234818,64 @@ module \dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -126295,207 +234884,207 @@ module \dec_sub26 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \function_unit 11'00000001000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \form 5'10000 + assign \internal_op 7'0111101 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \internal_op 7'0111101 + assign \form 5'10000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in1_sel 3'000 end @@ -126503,51 +235092,51 @@ module \dec_sub26 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in2_sel 4'1010 end @@ -126555,51 +235144,51 @@ module \dec_sub26 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in3_sel 2'01 end @@ -126607,51 +235196,51 @@ module \dec_sub26 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \out_sel 2'10 end @@ -126659,51 +235248,51 @@ module \dec_sub26 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_in 3'000 end @@ -126711,51 +235300,51 @@ module \dec_sub26 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_out 3'001 end @@ -126763,51 +235352,51 @@ module \dec_sub26 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \ldst_len 4'0000 end @@ -126815,51 +235404,51 @@ module \dec_sub26 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \upd 2'00 end @@ -126867,51 +235456,51 @@ module \dec_sub26 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rc_sel 2'10 end @@ -126919,51 +235508,51 @@ module \dec_sub26 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_in 2'00 end @@ -126971,103 +235560,103 @@ module \dec_sub26 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'00100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'00100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \asmcode 8'00100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \asmcode 8'00100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \asmcode 8'01000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \asmcode 8'01000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \asmcode 8'01000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \asmcode 8'01000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \asmcode 8'10001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01111 assign \asmcode 8'10001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01111 assign \asmcode 8'10001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 assign \asmcode 8'10001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 assign \asmcode 8'10001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \asmcode 8'10010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \asmcode 8'10011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'11001 assign \asmcode 8'10011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \asmcode 8'10100000 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_a 1'0 end @@ -127075,51 +235664,51 @@ module \dec_sub26 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_out 1'0 end @@ -127127,51 +235716,51 @@ module \dec_sub26 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_out 1'1 end @@ -127179,51 +235768,51 @@ module \dec_sub26 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \br 1'0 end @@ -127231,51 +235820,51 @@ module \dec_sub26 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn_ext 1'0 end @@ -127283,51 +235872,51 @@ module \dec_sub26 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rsrv 1'0 end @@ -127335,51 +235924,51 @@ module \dec_sub26 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \is_32b 1'0 end @@ -127387,51 +235976,51 @@ module \dec_sub26 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn 1'1 end @@ -127439,51 +236028,51 @@ module \dec_sub26 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \lk 1'0 end @@ -127491,51 +236080,51 @@ module \dec_sub26 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgl_pipe 1'0 end @@ -127545,7 +236134,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub19" module \dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -127559,40 +236148,8 @@ module \dec_sub19 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127666,16 +236223,50 @@ module \dec_sub19 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -127691,21 +236282,21 @@ module \dec_sub19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -127714,66 +236305,64 @@ module \dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -127782,75 +236371,75 @@ module \dec_sub19 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \function_unit 11'10000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \function_unit 11'10000000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 - assign \form 5'01010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \form 5'01010 + assign \internal_op 7'0110001 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 - assign \internal_op 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \internal_op 7'0110001 + assign \form 5'01010 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in1_sel 3'100 end @@ -127858,18 +236447,18 @@ module \dec_sub19 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in2_sel 4'0000 end @@ -127877,18 +236466,18 @@ module \dec_sub19 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in3_sel 2'00 end @@ -127896,18 +236485,18 @@ module \dec_sub19 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \out_sel 2'11 end @@ -127915,18 +236504,18 @@ module \dec_sub19 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_in 3'000 end @@ -127934,18 +236523,18 @@ module \dec_sub19 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_out 3'000 end @@ -127953,18 +236542,18 @@ module \dec_sub19 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \ldst_len 4'0000 end @@ -127972,18 +236561,18 @@ module \dec_sub19 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \upd 2'00 end @@ -127991,18 +236580,18 @@ module \dec_sub19 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rc_sel 2'00 end @@ -128010,18 +236599,18 @@ module \dec_sub19 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_in 2'00 end @@ -128029,37 +236618,37 @@ module \dec_sub19 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \asmcode 8'01101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00010 assign \asmcode 8'01101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 assign \asmcode 8'01110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \asmcode 8'01110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \asmcode 8'01111000 + assign \asmcode 8'01111001 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_a 1'0 end @@ -128067,18 +236656,18 @@ module \dec_sub19 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_out 1'0 end @@ -128086,18 +236675,18 @@ module \dec_sub19 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_out 1'0 end @@ -128105,18 +236694,18 @@ module \dec_sub19 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \br 1'0 end @@ -128124,18 +236713,18 @@ module \dec_sub19 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn_ext 1'0 end @@ -128143,18 +236732,18 @@ module \dec_sub19 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rsrv 1'0 end @@ -128162,18 +236751,18 @@ module \dec_sub19 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \is_32b 1'0 end @@ -128181,18 +236770,18 @@ module \dec_sub19 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn 1'0 end @@ -128200,18 +236789,18 @@ module \dec_sub19 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \lk 1'0 end @@ -128219,18 +236808,18 @@ module \dec_sub19 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgl_pipe 1'0 end @@ -128240,7 +236829,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub22" module \dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -128254,40 +236843,8 @@ module \dec_sub22 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -128361,16 +236918,50 @@ module \dec_sub22 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -128386,21 +236977,21 @@ module \dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128409,66 +237000,64 @@ module \dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -128477,207 +237066,207 @@ module \dec_sub22 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \function_unit 11'00000000010 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \form 5'01000 + assign \internal_op 7'0000001 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \internal_op 7'0100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \internal_op 7'0000001 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in1_sel 3'000 end @@ -128685,51 +237274,51 @@ module \dec_sub22 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in2_sel 4'0000 end @@ -128737,51 +237326,51 @@ module \dec_sub22 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in3_sel 2'00 end @@ -128789,51 +237378,51 @@ module \dec_sub22 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \out_sel 2'00 end @@ -128841,51 +237430,51 @@ module \dec_sub22 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_in 3'000 end @@ -128893,51 +237482,51 @@ module \dec_sub22 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_out 3'000 end @@ -128945,51 +237534,51 @@ module \dec_sub22 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \ldst_len 4'0000 end @@ -128997,51 +237586,51 @@ module \dec_sub22 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \upd 2'00 end @@ -129049,51 +237638,51 @@ module \dec_sub22 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rc_sel 2'00 end @@ -129101,51 +237690,51 @@ module \dec_sub22 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_in 2'00 end @@ -129153,103 +237742,103 @@ module \dec_sub22 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \asmcode 8'00101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'00101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \asmcode 8'00110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \asmcode 8'00110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \asmcode 8'01001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \asmcode 8'01011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \asmcode 8'01100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 - assign \asmcode 8'10100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \asmcode 8'10101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \asmcode 8'10110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \asmcode 8'10110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \asmcode 8'10110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'10110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \asmcode 8'11000110 + assign \asmcode 8'11001000 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_a 1'0 end @@ -129257,51 +237846,51 @@ module \dec_sub22 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_out 1'0 end @@ -129309,51 +237898,51 @@ module \dec_sub22 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_out 1'0 end @@ -129361,51 +237950,51 @@ module \dec_sub22 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \br 1'0 end @@ -129413,51 +238002,51 @@ module \dec_sub22 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn_ext 1'0 end @@ -129465,51 +238054,51 @@ module \dec_sub22 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rsrv 1'0 end @@ -129517,51 +238106,51 @@ module \dec_sub22 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \is_32b 1'0 end @@ -129569,51 +238158,51 @@ module \dec_sub22 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn 1'0 end @@ -129621,51 +238210,51 @@ module \dec_sub22 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \lk 1'0 end @@ -129673,51 +238262,51 @@ module \dec_sub22 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgl_pipe 1'1 end @@ -129727,7 +238316,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub9" module \dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -129741,40 +238330,8 @@ module \dec_sub9 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -129848,16 +238405,50 @@ module \dec_sub9 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -129873,21 +238464,21 @@ module \dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -129896,66 +238487,64 @@ module \dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -129964,219 +238553,219 @@ module \dec_sub9 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \function_unit 11'00100000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \form 5'10001 + assign \internal_op 7'0110010 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \internal_op 7'0110010 + assign \form 5'10001 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in1_sel 3'001 end @@ -130184,54 +238773,54 @@ module \dec_sub9 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in2_sel 4'0001 end @@ -130239,54 +238828,54 @@ module \dec_sub9 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in3_sel 2'00 end @@ -130294,54 +238883,54 @@ module \dec_sub9 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \out_sel 2'01 end @@ -130349,54 +238938,54 @@ module \dec_sub9 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_in 3'000 end @@ -130404,54 +238993,54 @@ module \dec_sub9 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_out 3'001 end @@ -130459,54 +239048,54 @@ module \dec_sub9 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \ldst_len 4'0000 end @@ -130514,54 +239103,54 @@ module \dec_sub9 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \upd 2'00 end @@ -130569,54 +239158,54 @@ module \dec_sub9 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rc_sel 2'10 end @@ -130624,54 +239213,54 @@ module \dec_sub9 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_in 2'00 end @@ -130679,109 +239268,109 @@ module \dec_sub9 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \asmcode 8'00110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \asmcode 8'00110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \asmcode 8'00110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \asmcode 8'00110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \asmcode 8'00111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \asmcode 8'00111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \asmcode 8'00110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \asmcode 8'00111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \asmcode 8'01110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \asmcode 8'01110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \asmcode 8'01111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00000 assign \asmcode 8'01111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \asmcode 8'01111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \asmcode 8'01111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'10000 assign \asmcode 8'01111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \asmcode 8'01111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \asmcode 8'01111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'10111 assign \asmcode 8'01111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \asmcode 8'01111111 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_a 1'0 end @@ -130789,54 +239378,54 @@ module \dec_sub9 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_out 1'0 end @@ -130844,54 +239433,54 @@ module \dec_sub9 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_out 1'0 end @@ -130899,54 +239488,54 @@ module \dec_sub9 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \br 1'0 end @@ -130954,54 +239543,54 @@ module \dec_sub9 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn_ext 1'0 end @@ -131009,54 +239598,54 @@ module \dec_sub9 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rsrv 1'0 end @@ -131064,54 +239653,54 @@ module \dec_sub9 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \is_32b 1'0 end @@ -131119,54 +239708,54 @@ module \dec_sub9 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn 1'1 end @@ -131174,54 +239763,54 @@ module \dec_sub9 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \lk 1'0 end @@ -131229,54 +239818,54 @@ module \dec_sub9 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgl_pipe 1'0 end @@ -131286,7 +239875,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub11" module \dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -131300,40 +239889,8 @@ module \dec_sub11 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -131407,16 +239964,50 @@ module \dec_sub11 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -131432,21 +240023,21 @@ module \dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -131455,66 +240046,64 @@ module \dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -131523,219 +240112,219 @@ module \dec_sub11 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \function_unit 11'00100000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \form 5'10001 + assign \internal_op 7'0110010 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \internal_op 7'0110010 + assign \form 5'10001 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in1_sel 3'001 end @@ -131743,54 +240332,54 @@ module \dec_sub11 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in2_sel 4'0001 end @@ -131798,54 +240387,54 @@ module \dec_sub11 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in3_sel 2'00 end @@ -131853,54 +240442,54 @@ module \dec_sub11 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \out_sel 2'01 end @@ -131908,54 +240497,54 @@ module \dec_sub11 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_in 3'000 end @@ -131963,54 +240552,54 @@ module \dec_sub11 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_out 3'001 end @@ -132018,54 +240607,54 @@ module \dec_sub11 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \ldst_len 4'0000 end @@ -132073,54 +240662,54 @@ module \dec_sub11 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \upd 2'00 end @@ -132128,54 +240717,54 @@ module \dec_sub11 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rc_sel 2'10 end @@ -132183,54 +240772,54 @@ module \dec_sub11 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_in 2'00 end @@ -132238,109 +240827,109 @@ module \dec_sub11 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \asmcode 8'00111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \asmcode 8'00111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \asmcode 8'00111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \asmcode 8'00111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \asmcode 8'01000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \asmcode 8'01000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \asmcode 8'00111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \asmcode 8'01000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \asmcode 8'01110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \asmcode 8'01110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \asmcode 8'01111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00000 assign \asmcode 8'01111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \asmcode 8'01111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \asmcode 8'01111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'10000 assign \asmcode 8'01111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10000 + assign \asmcode 8'01111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \asmcode 8'10000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'10111 assign \asmcode 8'10000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10111 + assign \asmcode 8'10000010 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_a 1'0 end @@ -132348,54 +240937,54 @@ module \dec_sub11 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_out 1'0 end @@ -132403,54 +240992,54 @@ module \dec_sub11 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_out 1'0 end @@ -132458,54 +241047,54 @@ module \dec_sub11 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \br 1'0 end @@ -132513,54 +241102,54 @@ module \dec_sub11 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn_ext 1'0 end @@ -132568,54 +241157,54 @@ module \dec_sub11 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rsrv 1'0 end @@ -132623,54 +241212,54 @@ module \dec_sub11 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \is_32b 1'1 end @@ -132678,54 +241267,54 @@ module \dec_sub11 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn 1'1 end @@ -132733,54 +241322,54 @@ module \dec_sub11 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \lk 1'0 end @@ -132788,54 +241377,54 @@ module \dec_sub11 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgl_pipe 1'0 end @@ -132845,7 +241434,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub27" module \dec_sub27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -132859,40 +241448,8 @@ module \dec_sub27 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -132966,16 +241523,50 @@ module \dec_sub27 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -132991,21 +241582,21 @@ module \dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -133014,66 +241605,64 @@ module \dec_sub27 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -133082,75 +241671,75 @@ module \dec_sub27 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000001000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'01000 + assign \internal_op 7'0111101 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0111101 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'000 end @@ -133158,18 +241747,18 @@ module \dec_sub27 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 end @@ -133177,18 +241766,18 @@ module \dec_sub27 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'01 end @@ -133196,18 +241785,18 @@ module \dec_sub27 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'10 end @@ -133215,18 +241804,18 @@ module \dec_sub27 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 end @@ -133234,18 +241823,18 @@ module \dec_sub27 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 end @@ -133253,18 +241842,18 @@ module \dec_sub27 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 end @@ -133272,18 +241861,18 @@ module \dec_sub27 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 end @@ -133291,18 +241880,18 @@ module \dec_sub27 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 end @@ -133310,18 +241899,18 @@ module \dec_sub27 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 end @@ -133329,37 +241918,37 @@ module \dec_sub27 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \asmcode 8'01000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \asmcode 8'10011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \asmcode 8'10011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \asmcode 8'10100010 + assign \asmcode 8'10100011 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 end @@ -133367,18 +241956,18 @@ module \dec_sub27 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 end @@ -133386,18 +241975,18 @@ module \dec_sub27 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 end @@ -133405,18 +241994,18 @@ module \dec_sub27 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 end @@ -133424,18 +242013,18 @@ module \dec_sub27 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 end @@ -133443,18 +242032,18 @@ module \dec_sub27 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 end @@ -133462,18 +242051,18 @@ module \dec_sub27 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 end @@ -133481,18 +242070,18 @@ module \dec_sub27 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 end @@ -133500,18 +242089,18 @@ module \dec_sub27 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 end @@ -133519,18 +242108,18 @@ module \dec_sub27 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 end @@ -133540,7 +242129,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub15" module \dec_sub15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -133554,40 +242143,8 @@ module \dec_sub15 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -133661,16 +242218,50 @@ module \dec_sub15 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -133686,21 +242277,21 @@ module \dec_sub15 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -133709,66 +242300,64 @@ module \dec_sub15 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -133777,411 +242366,411 @@ module \dec_sub15 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \function_unit 11'00001000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \form 5'10010 + assign \internal_op 7'0100011 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \internal_op 7'0100011 + assign \form 5'10010 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in1_sel 3'010 end @@ -134189,102 +242778,102 @@ module \dec_sub15 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in2_sel 4'0001 end @@ -134292,102 +242881,102 @@ module \dec_sub15 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in3_sel 2'00 end @@ -134395,102 +242984,102 @@ module \dec_sub15 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \out_sel 2'01 end @@ -134498,102 +243087,102 @@ module \dec_sub15 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_in 3'101 end @@ -134601,102 +243190,102 @@ module \dec_sub15 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_out 3'000 end @@ -134704,102 +243293,102 @@ module \dec_sub15 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \ldst_len 4'0000 end @@ -134807,102 +243396,102 @@ module \dec_sub15 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \upd 2'00 end @@ -134910,102 +243499,102 @@ module \dec_sub15 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rc_sel 2'00 end @@ -135013,102 +243602,102 @@ module \dec_sub15 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_in 2'00 end @@ -135116,102 +243705,102 @@ module \dec_sub15 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \asmcode 8'01001011 end @@ -135219,102 +243808,102 @@ module \dec_sub15 end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_a 1'0 end @@ -135322,102 +243911,102 @@ module \dec_sub15 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_out 1'0 end @@ -135425,102 +244014,102 @@ module \dec_sub15 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_out 1'0 end @@ -135528,102 +244117,102 @@ module \dec_sub15 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \br 1'0 end @@ -135631,102 +244220,102 @@ module \dec_sub15 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn_ext 1'0 end @@ -135734,102 +244323,102 @@ module \dec_sub15 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rsrv 1'0 end @@ -135837,102 +244426,102 @@ module \dec_sub15 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \is_32b 1'0 end @@ -135940,102 +244529,102 @@ module \dec_sub15 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn 1'0 end @@ -136043,102 +244632,102 @@ module \dec_sub15 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \lk 1'0 end @@ -136146,102 +244735,102 @@ module \dec_sub15 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgl_pipe 1'1 end @@ -136251,7 +244840,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub20" module \dec_sub20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -136265,40 +244854,8 @@ module \dec_sub20 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -136372,16 +244929,50 @@ module \dec_sub20 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -136397,21 +244988,21 @@ module \dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -136420,66 +245011,64 @@ module \dec_sub20 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -136488,99 +245077,99 @@ module \dec_sub20 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \function_unit 11'00000000100 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \form 5'01000 + assign \internal_op 7'0100110 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \internal_op 7'0100110 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in1_sel 3'010 end @@ -136588,24 +245177,24 @@ module \dec_sub20 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in2_sel 4'0001 end @@ -136613,24 +245202,24 @@ module \dec_sub20 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in3_sel 2'01 end @@ -136638,24 +245227,24 @@ module \dec_sub20 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \out_sel 2'00 end @@ -136663,24 +245252,24 @@ module \dec_sub20 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_in 3'000 end @@ -136688,24 +245277,24 @@ module \dec_sub20 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_out 3'000 end @@ -136713,24 +245302,24 @@ module \dec_sub20 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \ldst_len 4'1000 end @@ -136738,24 +245327,24 @@ module \dec_sub20 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \upd 2'00 end @@ -136763,24 +245352,24 @@ module \dec_sub20 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rc_sel 2'00 end @@ -136788,24 +245377,24 @@ module \dec_sub20 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_in 2'00 end @@ -136813,49 +245402,49 @@ module \dec_sub20 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'01001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \asmcode 8'01010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \asmcode 8'01010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \asmcode 8'01011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'01100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \asmcode 8'10101010 + assign \asmcode 8'10101100 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_a 1'0 end @@ -136863,24 +245452,24 @@ module \dec_sub20 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_out 1'0 end @@ -136888,24 +245477,24 @@ module \dec_sub20 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_out 1'0 end @@ -136913,24 +245502,24 @@ module \dec_sub20 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \br 1'1 end @@ -136938,24 +245527,24 @@ module \dec_sub20 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn_ext 1'0 end @@ -136963,24 +245552,24 @@ module \dec_sub20 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rsrv 1'0 end @@ -136988,24 +245577,24 @@ module \dec_sub20 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \is_32b 1'0 end @@ -137013,24 +245602,24 @@ module \dec_sub20 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn 1'0 end @@ -137038,24 +245627,24 @@ module \dec_sub20 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \lk 1'0 end @@ -137063,24 +245652,24 @@ module \dec_sub20 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgl_pipe 1'1 end @@ -137090,7 +245679,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub21" module \dec_sub21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -137104,40 +245693,8 @@ module \dec_sub21 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -137211,16 +245768,50 @@ module \dec_sub21 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -137236,21 +245827,21 @@ module \dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -137259,66 +245850,64 @@ module \dec_sub21 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -137327,183 +245916,195 @@ module \dec_sub21 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \function_unit 11'00000000100 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \form 5'01000 + assign \internal_op 7'0100110 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 - assign \internal_op 7'0100110 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in1_sel 3'010 end @@ -137511,45 +246112,48 @@ module \dec_sub21 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in2_sel 4'0001 end @@ -137557,45 +246161,48 @@ module \dec_sub21 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \in3_sel 2'01 end @@ -137603,45 +246210,48 @@ module \dec_sub21 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \out_sel 2'00 end @@ -137649,45 +246259,48 @@ module \dec_sub21 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_in 3'000 end @@ -137695,45 +246308,48 @@ module \dec_sub21 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cr_out 3'000 end @@ -137741,45 +246357,48 @@ module \dec_sub21 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \ldst_len 4'0100 end @@ -137787,45 +246406,48 @@ module \dec_sub21 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \upd 2'10 end @@ -137833,45 +246455,48 @@ module \dec_sub21 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rc_sel 2'00 end @@ -137879,45 +246504,48 @@ module \dec_sub21 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_in 2'00 end @@ -137925,45 +246553,48 @@ module \dec_sub21 end process $group_14 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_a 1'0 end @@ -137971,45 +246602,48 @@ module \dec_sub21 end process $group_15 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \inv_out 1'0 end @@ -138017,45 +246651,48 @@ module \dec_sub21 end process $group_16 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \cry_out 1'0 end @@ -138063,45 +246700,48 @@ module \dec_sub21 end process $group_17 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \br 1'0 end @@ -138109,45 +246749,48 @@ module \dec_sub21 end process $group_18 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn_ext 1'0 end @@ -138155,45 +246798,48 @@ module \dec_sub21 end process $group_19 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \rsrv 1'0 end @@ -138201,45 +246847,48 @@ module \dec_sub21 end process $group_20 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \is_32b 1'0 end @@ -138247,45 +246896,48 @@ module \dec_sub21 end process $group_21 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgn 1'0 end @@ -138293,45 +246945,48 @@ module \dec_sub21 end process $group_22 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \lk 1'0 end @@ -138339,45 +246994,48 @@ module \dec_sub21 end process $group_23 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 assign \sgl_pipe 1'1 end @@ -138385,39 +247043,43 @@ module \dec_sub21 end process $group_24 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \asmcode 8'01010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \asmcode 8'01010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \asmcode 8'01100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \asmcode 8'01100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11000 + assign \asmcode 8'01101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \asmcode 8'10101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'10101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11100 end sync init @@ -138426,7 +247088,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub23" module \dec_sub23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -138440,40 +247102,8 @@ module \dec_sub23 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -138547,16 +247177,50 @@ module \dec_sub23 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -138572,21 +247236,21 @@ module \dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -138595,66 +247259,64 @@ module \dec_sub23 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -138663,195 +247325,195 @@ module \dec_sub23 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00000000100 end sync init end process $group_2 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'01100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00100 + assign \internal_op 7'0100110 + end + sync init + end + process $group_3 assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \form 5'01000 end sync init end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'01100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00100 - assign \internal_op 7'0100110 - end - sync init - end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'010 end @@ -138859,48 +247521,48 @@ module \dec_sub23 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0001 end @@ -138908,48 +247570,48 @@ module \dec_sub23 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'01 end @@ -138957,48 +247619,48 @@ module \dec_sub23 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'00 end @@ -139006,48 +247668,48 @@ module \dec_sub23 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 end @@ -139055,48 +247717,48 @@ module \dec_sub23 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 end @@ -139104,48 +247766,48 @@ module \dec_sub23 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0100 end @@ -139153,48 +247815,48 @@ module \dec_sub23 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 end @@ -139202,48 +247864,48 @@ module \dec_sub23 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 end @@ -139251,48 +247913,48 @@ module \dec_sub23 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 end @@ -139300,97 +247962,97 @@ module \dec_sub23 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \asmcode 8'01010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \asmcode 8'01010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \asmcode 8'01011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \asmcode 8'01011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \asmcode 8'01100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \asmcode 8'01100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \asmcode 8'01101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00000 assign \asmcode 8'01101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \asmcode 8'01101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \asmcode 8'10100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \asmcode 8'10101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 - assign \asmcode 8'10110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 - assign \asmcode 8'10110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \asmcode 8'10111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'10111010 + assign \asmcode 8'10111100 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 end @@ -139398,48 +248060,48 @@ module \dec_sub23 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 end @@ -139447,48 +248109,48 @@ module \dec_sub23 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 end @@ -139496,48 +248158,48 @@ module \dec_sub23 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 end @@ -139545,48 +248207,48 @@ module \dec_sub23 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 end @@ -139594,48 +248256,48 @@ module \dec_sub23 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 end @@ -139643,48 +248305,48 @@ module \dec_sub23 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 end @@ -139692,48 +248354,48 @@ module \dec_sub23 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 end @@ -139741,48 +248403,48 @@ module \dec_sub23 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 end @@ -139790,48 +248452,48 @@ module \dec_sub23 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'01100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'1 end @@ -139841,7 +248503,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub16" module \dec_sub16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -139855,40 +248517,8 @@ module \dec_sub16 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -139962,16 +248592,50 @@ module \dec_sub16 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -139987,21 +248651,21 @@ module \dec_sub16 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -140010,66 +248674,64 @@ module \dec_sub16 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -140078,39 +248740,39 @@ module \dec_sub16 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00001000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'01010 + assign \internal_op 7'0110000 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0110000 + assign \form 5'01010 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'100 end @@ -140118,9 +248780,9 @@ module \dec_sub16 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0000 end @@ -140128,9 +248790,9 @@ module \dec_sub16 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 end @@ -140138,9 +248800,9 @@ module \dec_sub16 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'00 end @@ -140148,9 +248810,9 @@ module \dec_sub16 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'110 end @@ -140158,9 +248820,9 @@ module \dec_sub16 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'100 end @@ -140168,9 +248830,9 @@ module \dec_sub16 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0000 end @@ -140178,9 +248840,9 @@ module \dec_sub16 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 end @@ -140188,9 +248850,9 @@ module \dec_sub16 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 end @@ -140198,9 +248860,9 @@ module \dec_sub16 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 end @@ -140208,19 +248870,19 @@ module \dec_sub16 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'01110101 + assign \asmcode 8'01110110 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 end @@ -140228,9 +248890,9 @@ module \dec_sub16 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 end @@ -140238,9 +248900,9 @@ module \dec_sub16 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 end @@ -140248,9 +248910,9 @@ module \dec_sub16 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 end @@ -140258,9 +248920,9 @@ module \dec_sub16 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 end @@ -140268,9 +248930,9 @@ module \dec_sub16 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 end @@ -140278,9 +248940,9 @@ module \dec_sub16 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 end @@ -140288,9 +248950,9 @@ module \dec_sub16 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 end @@ -140298,9 +248960,9 @@ module \dec_sub16 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 end @@ -140308,9 +248970,9 @@ module \dec_sub16 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'0 end @@ -140320,7 +248982,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub18" module \dec_sub18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -140334,40 +248996,8 @@ module \dec_sub18 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -140441,16 +249071,50 @@ module \dec_sub18 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -140466,21 +249130,21 @@ module \dec_sub18 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -140489,66 +249153,64 @@ module \dec_sub18 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -140557,51 +249219,51 @@ module \dec_sub18 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00010000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'1001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'01000 + assign \internal_op 7'1001010 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \internal_op 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'1001010 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'100 end @@ -140609,12 +249271,12 @@ module \dec_sub18 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0000 end @@ -140622,12 +249284,12 @@ module \dec_sub18 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 end @@ -140635,12 +249297,12 @@ module \dec_sub18 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'00 end @@ -140648,12 +249310,12 @@ module \dec_sub18 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 end @@ -140661,12 +249323,12 @@ module \dec_sub18 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'000 end @@ -140674,12 +249336,12 @@ module \dec_sub18 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0000 end @@ -140687,12 +249349,12 @@ module \dec_sub18 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 end @@ -140700,12 +249362,12 @@ module \dec_sub18 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'00 end @@ -140713,12 +249375,12 @@ module \dec_sub18 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'00 end @@ -140726,25 +249388,25 @@ module \dec_sub18 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 - assign \asmcode 8'01110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'01110110 + assign \asmcode 8'01110111 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'0 end @@ -140752,12 +249414,12 @@ module \dec_sub18 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 end @@ -140765,12 +249427,12 @@ module \dec_sub18 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'0 end @@ -140778,12 +249440,12 @@ module \dec_sub18 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 end @@ -140791,12 +249453,12 @@ module \dec_sub18 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 end @@ -140804,12 +249466,12 @@ module \dec_sub18 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 end @@ -140817,12 +249479,12 @@ module \dec_sub18 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 end @@ -140830,12 +249492,12 @@ module \dec_sub18 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 end @@ -140843,12 +249505,12 @@ module \dec_sub18 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 end @@ -140856,12 +249518,12 @@ module \dec_sub18 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'1 end @@ -140871,7 +249533,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub8" module \dec_sub8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -140885,40 +249547,8 @@ module \dec_sub8 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -140992,16 +249622,50 @@ module \dec_sub8 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -141017,21 +249681,21 @@ module \dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -141040,66 +249704,64 @@ module \dec_sub8 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -141108,171 +249770,171 @@ module \dec_sub8 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \function_unit 11'00000000010 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \form 5'10001 + assign \internal_op 7'0000010 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \internal_op 7'0000010 + assign \form 5'10001 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in1_sel 3'001 end @@ -141280,42 +249942,42 @@ module \dec_sub8 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in2_sel 4'0000 end @@ -141323,42 +249985,42 @@ module \dec_sub8 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \in3_sel 2'00 end @@ -141366,42 +250028,42 @@ module \dec_sub8 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \out_sel 2'01 end @@ -141409,42 +250071,42 @@ module \dec_sub8 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_in 3'000 end @@ -141452,42 +250114,42 @@ module \dec_sub8 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cr_out 3'001 end @@ -141495,42 +250157,42 @@ module \dec_sub8 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \ldst_len 4'0000 end @@ -141538,42 +250200,42 @@ module \dec_sub8 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \upd 2'00 end @@ -141581,42 +250243,42 @@ module \dec_sub8 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rc_sel 2'10 end @@ -141624,42 +250286,42 @@ module \dec_sub8 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_in 2'10 end @@ -141667,85 +250329,85 @@ module \dec_sub8 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 - assign \asmcode 8'10000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'10011 assign \asmcode 8'10000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'10011 + assign \asmcode 8'10000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 - assign \asmcode 8'10111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 - assign \asmcode 8'11000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'11000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \asmcode 8'10111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \asmcode 8'10111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 - assign \asmcode 8'10111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'11000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 - assign \asmcode 8'10111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00111 assign \asmcode 8'11000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00111 + assign \asmcode 8'11000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 - assign \asmcode 8'11000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00110 assign \asmcode 8'11000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00110 + assign \asmcode 8'11000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 - assign \asmcode 8'11000101 + assign \asmcode 8'11000111 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_a 1'1 end @@ -141753,42 +250415,42 @@ module \dec_sub8 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \inv_out 1'0 end @@ -141796,42 +250458,42 @@ module \dec_sub8 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \cry_out 1'1 end @@ -141839,42 +250501,42 @@ module \dec_sub8 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \br 1'0 end @@ -141882,42 +250544,42 @@ module \dec_sub8 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn_ext 1'0 end @@ -141925,42 +250587,42 @@ module \dec_sub8 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \rsrv 1'0 end @@ -141968,42 +250630,42 @@ module \dec_sub8 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \is_32b 1'0 end @@ -142011,42 +250673,42 @@ module \dec_sub8 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgn 1'0 end @@ -142054,42 +250716,42 @@ module \dec_sub8 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \lk 1'0 end @@ -142097,42 +250759,42 @@ module \dec_sub8 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10110 assign \sgl_pipe 1'0 end @@ -142142,7 +250804,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub24" module \dec_sub24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -142156,40 +250818,8 @@ module \dec_sub24 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -142263,16 +250893,50 @@ module \dec_sub24 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -142288,21 +250952,21 @@ module \dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -142311,66 +250975,64 @@ module \dec_sub24 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -142379,75 +251041,75 @@ module \dec_sub24 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \function_unit 11'00000001000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \form 5'01000 + assign \internal_op 7'0111101 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \internal_op 7'0111101 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in1_sel 3'000 end @@ -142455,18 +251117,18 @@ module \dec_sub24 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in2_sel 4'0001 end @@ -142474,18 +251136,18 @@ module \dec_sub24 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \in3_sel 2'01 end @@ -142493,18 +251155,18 @@ module \dec_sub24 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \out_sel 2'10 end @@ -142512,18 +251174,18 @@ module \dec_sub24 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_in 3'000 end @@ -142531,18 +251193,18 @@ module \dec_sub24 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cr_out 3'001 end @@ -142550,18 +251212,18 @@ module \dec_sub24 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \ldst_len 4'0000 end @@ -142569,18 +251231,18 @@ module \dec_sub24 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \upd 2'00 end @@ -142588,18 +251250,18 @@ module \dec_sub24 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rc_sel 2'10 end @@ -142607,18 +251269,18 @@ module \dec_sub24 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_in 2'00 end @@ -142626,37 +251288,37 @@ module \dec_sub24 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \asmcode 8'10011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 - assign \asmcode 8'10100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'11001 assign \asmcode 8'10100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'11001 + assign \asmcode 8'10100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 - assign \asmcode 8'10100011 + assign \asmcode 8'10100100 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_a 1'0 end @@ -142664,18 +251326,18 @@ module \dec_sub24 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \inv_out 1'0 end @@ -142683,18 +251345,18 @@ module \dec_sub24 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \cry_out 1'0 end @@ -142702,18 +251364,18 @@ module \dec_sub24 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \br 1'0 end @@ -142721,18 +251383,18 @@ module \dec_sub24 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn_ext 1'0 end @@ -142740,18 +251402,18 @@ module \dec_sub24 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \rsrv 1'0 end @@ -142759,18 +251421,18 @@ module \dec_sub24 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \is_32b 1'1 end @@ -142778,18 +251440,18 @@ module \dec_sub24 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgn 1'0 end @@ -142797,18 +251459,18 @@ module \dec_sub24 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \lk 1'0 end @@ -142816,18 +251478,18 @@ module \dec_sub24 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'11001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'10000 assign \sgl_pipe 1'0 end @@ -142837,7 +251499,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub4" module \dec_sub4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -142851,40 +251513,8 @@ module \dec_sub4 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -142958,16 +251588,50 @@ module \dec_sub4 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -142983,21 +251647,21 @@ module \dec_sub4 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -143006,66 +251670,64 @@ module \dec_sub4 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 5 \opcode_switch process $group_0 assign \opcode_switch 5'00000 @@ -143074,51 +251736,51 @@ module \dec_sub4 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \function_unit 11'00010000000 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \form 5'01000 + assign \internal_op 7'0111111 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 - assign \internal_op 7'0111111 + assign \form 5'01000 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in1_sel 3'001 end @@ -143126,12 +251788,12 @@ module \dec_sub4 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in2_sel 4'0001 end @@ -143139,12 +251801,12 @@ module \dec_sub4 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \in3_sel 2'00 end @@ -143152,12 +251814,12 @@ module \dec_sub4 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \out_sel 2'00 end @@ -143165,12 +251827,12 @@ module \dec_sub4 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_in 3'000 end @@ -143178,12 +251840,12 @@ module \dec_sub4 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cr_out 3'000 end @@ -143191,12 +251853,12 @@ module \dec_sub4 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \ldst_len 4'0000 end @@ -143204,12 +251866,12 @@ module \dec_sub4 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \upd 2'00 end @@ -143217,12 +251879,12 @@ module \dec_sub4 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rc_sel 2'00 end @@ -143230,12 +251892,12 @@ module \dec_sub4 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_in 2'00 end @@ -143243,25 +251905,25 @@ module \dec_sub4 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 - assign \asmcode 8'11000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 5'00000 assign \asmcode 8'11001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 5'00000 + assign \asmcode 8'11001011 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_a 1'0 end @@ -143269,12 +251931,12 @@ module \dec_sub4 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \inv_out 1'0 end @@ -143282,12 +251944,12 @@ module \dec_sub4 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \cry_out 1'0 end @@ -143295,12 +251957,12 @@ module \dec_sub4 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \br 1'0 end @@ -143308,12 +251970,12 @@ module \dec_sub4 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn_ext 1'0 end @@ -143321,12 +251983,12 @@ module \dec_sub4 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \rsrv 1'0 end @@ -143334,12 +251996,12 @@ module \dec_sub4 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \is_32b 1'1 end @@ -143347,12 +252009,12 @@ module \dec_sub4 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgn 1'0 end @@ -143360,12 +252022,12 @@ module \dec_sub4 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \lk 1'0 end @@ -143373,12 +252035,12 @@ module \dec_sub4 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 5'00000 assign \sgl_pipe 1'1 end @@ -143388,7 +252050,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" module \dec31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -143402,40 +252064,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -143509,16 +252139,50 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -143534,21 +252198,21 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -143557,66 +252221,64 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub10_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -143630,40 +252292,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub10_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub10_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -143737,15 +252367,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub10_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub10_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub10_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -143762,20 +252426,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub10_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub10_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -143785,7 +252449,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -143793,71 +252457,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub10_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub10_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub10_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub10_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub10_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub10_asmcode cell \dec_sub10 \dec_sub10 connect \opcode_in \dec_sub10_opcode_in connect \function_unit \dec_sub10_function_unit - connect \form \dec_sub10_form connect \internal_op \dec_sub10_internal_op + connect \form \dec_sub10_form + connect \asmcode \dec_sub10_asmcode connect \in1_sel \dec_sub10_in1_sel connect \in2_sel \dec_sub10_in2_sel connect \in3_sel \dec_sub10_in3_sel connect \out_sel \dec_sub10_out_sel connect \cr_in \dec_sub10_cr_in connect \cr_out \dec_sub10_cr_out - connect \rc_sel \dec_sub10_rc_sel connect \ldst_len \dec_sub10_ldst_len connect \upd \dec_sub10_upd + connect \rc_sel \dec_sub10_rc_sel connect \cry_in \dec_sub10_cry_in connect \inv_a \dec_sub10_inv_a connect \inv_out \dec_sub10_inv_out @@ -143869,9 +252532,8 @@ module \dec31 connect \sgn \dec_sub10_sgn connect \lk \dec_sub10_lk connect \sgl_pipe \dec_sub10_sgl_pipe - connect \asmcode \dec_sub10_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub28_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -143885,40 +252547,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub28_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub28_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -143992,15 +252622,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub28_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub28_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub28_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -144017,20 +252681,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub28_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub28_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -144040,7 +252704,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -144048,71 +252712,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub28_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub28_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub28_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub28_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub28_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub28_asmcode cell \dec_sub28 \dec_sub28 connect \opcode_in \dec_sub28_opcode_in connect \function_unit \dec_sub28_function_unit - connect \form \dec_sub28_form connect \internal_op \dec_sub28_internal_op + connect \form \dec_sub28_form + connect \asmcode \dec_sub28_asmcode connect \in1_sel \dec_sub28_in1_sel connect \in2_sel \dec_sub28_in2_sel connect \in3_sel \dec_sub28_in3_sel connect \out_sel \dec_sub28_out_sel connect \cr_in \dec_sub28_cr_in connect \cr_out \dec_sub28_cr_out - connect \rc_sel \dec_sub28_rc_sel connect \ldst_len \dec_sub28_ldst_len connect \upd \dec_sub28_upd + connect \rc_sel \dec_sub28_rc_sel connect \cry_in \dec_sub28_cry_in connect \inv_a \dec_sub28_inv_a connect \inv_out \dec_sub28_inv_out @@ -144124,9 +252787,8 @@ module \dec31 connect \sgn \dec_sub28_sgn connect \lk \dec_sub28_lk connect \sgl_pipe \dec_sub28_sgl_pipe - connect \asmcode \dec_sub28_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub0_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -144140,40 +252802,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub0_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub0_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -144247,15 +252877,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub0_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub0_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub0_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -144272,20 +252936,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub0_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub0_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -144295,7 +252959,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -144303,71 +252967,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub0_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub0_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub0_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub0_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub0_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub0_asmcode cell \dec_sub0 \dec_sub0 connect \opcode_in \dec_sub0_opcode_in connect \function_unit \dec_sub0_function_unit - connect \form \dec_sub0_form connect \internal_op \dec_sub0_internal_op + connect \form \dec_sub0_form + connect \asmcode \dec_sub0_asmcode connect \in1_sel \dec_sub0_in1_sel connect \in2_sel \dec_sub0_in2_sel connect \in3_sel \dec_sub0_in3_sel connect \out_sel \dec_sub0_out_sel connect \cr_in \dec_sub0_cr_in connect \cr_out \dec_sub0_cr_out - connect \rc_sel \dec_sub0_rc_sel connect \ldst_len \dec_sub0_ldst_len connect \upd \dec_sub0_upd + connect \rc_sel \dec_sub0_rc_sel connect \cry_in \dec_sub0_cry_in connect \inv_a \dec_sub0_inv_a connect \inv_out \dec_sub0_inv_out @@ -144379,9 +253042,8 @@ module \dec31 connect \sgn \dec_sub0_sgn connect \lk \dec_sub0_lk connect \sgl_pipe \dec_sub0_sgl_pipe - connect \asmcode \dec_sub0_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub26_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -144395,40 +253057,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub26_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub26_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -144502,15 +253132,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub26_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub26_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub26_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -144527,20 +253191,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub26_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub26_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -144550,7 +253214,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -144558,71 +253222,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub26_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub26_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub26_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub26_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub26_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub26_asmcode cell \dec_sub26 \dec_sub26 connect \opcode_in \dec_sub26_opcode_in connect \function_unit \dec_sub26_function_unit - connect \form \dec_sub26_form connect \internal_op \dec_sub26_internal_op + connect \form \dec_sub26_form + connect \asmcode \dec_sub26_asmcode connect \in1_sel \dec_sub26_in1_sel connect \in2_sel \dec_sub26_in2_sel connect \in3_sel \dec_sub26_in3_sel connect \out_sel \dec_sub26_out_sel connect \cr_in \dec_sub26_cr_in connect \cr_out \dec_sub26_cr_out - connect \rc_sel \dec_sub26_rc_sel connect \ldst_len \dec_sub26_ldst_len connect \upd \dec_sub26_upd + connect \rc_sel \dec_sub26_rc_sel connect \cry_in \dec_sub26_cry_in connect \inv_a \dec_sub26_inv_a connect \inv_out \dec_sub26_inv_out @@ -144634,9 +253297,8 @@ module \dec31 connect \sgn \dec_sub26_sgn connect \lk \dec_sub26_lk connect \sgl_pipe \dec_sub26_sgl_pipe - connect \asmcode \dec_sub26_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -144650,40 +253312,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub19_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub19_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -144757,15 +253387,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub19_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub19_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub19_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -144782,20 +253446,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub19_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub19_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -144805,7 +253469,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -144813,71 +253477,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub19_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub19_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub19_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub19_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub19_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub19_asmcode cell \dec_sub19 \dec_sub19 connect \opcode_in \dec_sub19_opcode_in connect \function_unit \dec_sub19_function_unit - connect \form \dec_sub19_form connect \internal_op \dec_sub19_internal_op + connect \form \dec_sub19_form + connect \asmcode \dec_sub19_asmcode connect \in1_sel \dec_sub19_in1_sel connect \in2_sel \dec_sub19_in2_sel connect \in3_sel \dec_sub19_in3_sel connect \out_sel \dec_sub19_out_sel connect \cr_in \dec_sub19_cr_in connect \cr_out \dec_sub19_cr_out - connect \rc_sel \dec_sub19_rc_sel connect \ldst_len \dec_sub19_ldst_len connect \upd \dec_sub19_upd + connect \rc_sel \dec_sub19_rc_sel connect \cry_in \dec_sub19_cry_in connect \inv_a \dec_sub19_inv_a connect \inv_out \dec_sub19_inv_out @@ -144889,9 +253552,8 @@ module \dec31 connect \sgn \dec_sub19_sgn connect \lk \dec_sub19_lk connect \sgl_pipe \dec_sub19_sgl_pipe - connect \asmcode \dec_sub19_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub22_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -144905,8 +253567,83 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub22_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_sub22_internal_op attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -144937,90 +253674,17 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 5 \dec_sub22_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 \dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub22_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -145037,20 +253701,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub22_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub22_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -145060,7 +253724,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -145068,71 +253732,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub22_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub22_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub22_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub22_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub22_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub22_asmcode cell \dec_sub22 \dec_sub22 connect \opcode_in \dec_sub22_opcode_in connect \function_unit \dec_sub22_function_unit - connect \form \dec_sub22_form connect \internal_op \dec_sub22_internal_op + connect \form \dec_sub22_form + connect \asmcode \dec_sub22_asmcode connect \in1_sel \dec_sub22_in1_sel connect \in2_sel \dec_sub22_in2_sel connect \in3_sel \dec_sub22_in3_sel connect \out_sel \dec_sub22_out_sel connect \cr_in \dec_sub22_cr_in connect \cr_out \dec_sub22_cr_out - connect \rc_sel \dec_sub22_rc_sel connect \ldst_len \dec_sub22_ldst_len connect \upd \dec_sub22_upd + connect \rc_sel \dec_sub22_rc_sel connect \cry_in \dec_sub22_cry_in connect \inv_a \dec_sub22_inv_a connect \inv_out \dec_sub22_inv_out @@ -145144,9 +253807,8 @@ module \dec31 connect \sgn \dec_sub22_sgn connect \lk \dec_sub22_lk connect \sgl_pipe \dec_sub22_sgl_pipe - connect \asmcode \dec_sub22_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -145160,40 +253822,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub9_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub9_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -145267,15 +253897,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub9_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub9_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub9_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -145292,20 +253956,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub9_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub9_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -145315,7 +253979,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -145323,71 +253987,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub9_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub9_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub9_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub9_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub9_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub9_asmcode cell \dec_sub9 \dec_sub9 connect \opcode_in \dec_sub9_opcode_in connect \function_unit \dec_sub9_function_unit - connect \form \dec_sub9_form connect \internal_op \dec_sub9_internal_op + connect \form \dec_sub9_form + connect \asmcode \dec_sub9_asmcode connect \in1_sel \dec_sub9_in1_sel connect \in2_sel \dec_sub9_in2_sel connect \in3_sel \dec_sub9_in3_sel connect \out_sel \dec_sub9_out_sel connect \cr_in \dec_sub9_cr_in connect \cr_out \dec_sub9_cr_out - connect \rc_sel \dec_sub9_rc_sel connect \ldst_len \dec_sub9_ldst_len connect \upd \dec_sub9_upd + connect \rc_sel \dec_sub9_rc_sel connect \cry_in \dec_sub9_cry_in connect \inv_a \dec_sub9_inv_a connect \inv_out \dec_sub9_inv_out @@ -145399,9 +254062,8 @@ module \dec31 connect \sgn \dec_sub9_sgn connect \lk \dec_sub9_lk connect \sgl_pipe \dec_sub9_sgl_pipe - connect \asmcode \dec_sub9_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub11_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -145415,40 +254077,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub11_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub11_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -145522,15 +254152,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub11_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub11_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub11_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -145547,20 +254211,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub11_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub11_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -145570,7 +254234,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -145578,71 +254242,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub11_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub11_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub11_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub11_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub11_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub11_asmcode cell \dec_sub11 \dec_sub11 connect \opcode_in \dec_sub11_opcode_in connect \function_unit \dec_sub11_function_unit - connect \form \dec_sub11_form connect \internal_op \dec_sub11_internal_op + connect \form \dec_sub11_form + connect \asmcode \dec_sub11_asmcode connect \in1_sel \dec_sub11_in1_sel connect \in2_sel \dec_sub11_in2_sel connect \in3_sel \dec_sub11_in3_sel connect \out_sel \dec_sub11_out_sel connect \cr_in \dec_sub11_cr_in connect \cr_out \dec_sub11_cr_out - connect \rc_sel \dec_sub11_rc_sel connect \ldst_len \dec_sub11_ldst_len connect \upd \dec_sub11_upd + connect \rc_sel \dec_sub11_rc_sel connect \cry_in \dec_sub11_cry_in connect \inv_a \dec_sub11_inv_a connect \inv_out \dec_sub11_inv_out @@ -145654,9 +254317,8 @@ module \dec31 connect \sgn \dec_sub11_sgn connect \lk \dec_sub11_lk connect \sgl_pipe \dec_sub11_sgl_pipe - connect \asmcode \dec_sub11_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub27_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -145670,40 +254332,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub27_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub27_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -145777,15 +254407,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub27_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub27_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub27_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -145802,20 +254466,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub27_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub27_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -145825,7 +254489,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -145833,71 +254497,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub27_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub27_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub27_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub27_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub27_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub27_asmcode cell \dec_sub27 \dec_sub27 connect \opcode_in \dec_sub27_opcode_in connect \function_unit \dec_sub27_function_unit - connect \form \dec_sub27_form connect \internal_op \dec_sub27_internal_op + connect \form \dec_sub27_form + connect \asmcode \dec_sub27_asmcode connect \in1_sel \dec_sub27_in1_sel connect \in2_sel \dec_sub27_in2_sel connect \in3_sel \dec_sub27_in3_sel connect \out_sel \dec_sub27_out_sel connect \cr_in \dec_sub27_cr_in connect \cr_out \dec_sub27_cr_out - connect \rc_sel \dec_sub27_rc_sel connect \ldst_len \dec_sub27_ldst_len connect \upd \dec_sub27_upd + connect \rc_sel \dec_sub27_rc_sel connect \cry_in \dec_sub27_cry_in connect \inv_a \dec_sub27_inv_a connect \inv_out \dec_sub27_inv_out @@ -145909,9 +254572,8 @@ module \dec31 connect \sgn \dec_sub27_sgn connect \lk \dec_sub27_lk connect \sgl_pipe \dec_sub27_sgl_pipe - connect \asmcode \dec_sub27_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub15_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -145925,40 +254587,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub15_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub15_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -146032,15 +254662,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub15_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub15_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub15_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -146057,20 +254721,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub15_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub15_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -146080,7 +254744,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -146088,71 +254752,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub15_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub15_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub15_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub15_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub15_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub15_asmcode cell \dec_sub15 \dec_sub15 connect \opcode_in \dec_sub15_opcode_in connect \function_unit \dec_sub15_function_unit - connect \form \dec_sub15_form connect \internal_op \dec_sub15_internal_op + connect \form \dec_sub15_form + connect \asmcode \dec_sub15_asmcode connect \in1_sel \dec_sub15_in1_sel connect \in2_sel \dec_sub15_in2_sel connect \in3_sel \dec_sub15_in3_sel connect \out_sel \dec_sub15_out_sel connect \cr_in \dec_sub15_cr_in connect \cr_out \dec_sub15_cr_out - connect \rc_sel \dec_sub15_rc_sel connect \ldst_len \dec_sub15_ldst_len connect \upd \dec_sub15_upd + connect \rc_sel \dec_sub15_rc_sel connect \cry_in \dec_sub15_cry_in connect \inv_a \dec_sub15_inv_a connect \inv_out \dec_sub15_inv_out @@ -146164,9 +254827,8 @@ module \dec31 connect \sgn \dec_sub15_sgn connect \lk \dec_sub15_lk connect \sgl_pipe \dec_sub15_sgl_pipe - connect \asmcode \dec_sub15_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub20_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -146180,40 +254842,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub20_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub20_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -146287,15 +254917,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub20_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub20_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub20_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -146312,20 +254976,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub20_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub20_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -146335,7 +254999,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -146343,71 +255007,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub20_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub20_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub20_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub20_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub20_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub20_asmcode cell \dec_sub20 \dec_sub20 connect \opcode_in \dec_sub20_opcode_in connect \function_unit \dec_sub20_function_unit - connect \form \dec_sub20_form connect \internal_op \dec_sub20_internal_op + connect \form \dec_sub20_form + connect \asmcode \dec_sub20_asmcode connect \in1_sel \dec_sub20_in1_sel connect \in2_sel \dec_sub20_in2_sel connect \in3_sel \dec_sub20_in3_sel connect \out_sel \dec_sub20_out_sel connect \cr_in \dec_sub20_cr_in connect \cr_out \dec_sub20_cr_out - connect \rc_sel \dec_sub20_rc_sel connect \ldst_len \dec_sub20_ldst_len connect \upd \dec_sub20_upd + connect \rc_sel \dec_sub20_rc_sel connect \cry_in \dec_sub20_cry_in connect \inv_a \dec_sub20_inv_a connect \inv_out \dec_sub20_inv_out @@ -146419,9 +255082,8 @@ module \dec31 connect \sgn \dec_sub20_sgn connect \lk \dec_sub20_lk connect \sgl_pipe \dec_sub20_sgl_pipe - connect \asmcode \dec_sub20_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub21_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -146435,8 +255097,83 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub21_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec_sub21_internal_op attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -146467,90 +255204,17 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 5 \dec_sub21_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 \dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub21_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -146567,20 +255231,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub21_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub21_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -146590,7 +255254,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -146598,71 +255262,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub21_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub21_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub21_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub21_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub21_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub21_asmcode cell \dec_sub21 \dec_sub21 connect \opcode_in \dec_sub21_opcode_in connect \function_unit \dec_sub21_function_unit - connect \form \dec_sub21_form connect \internal_op \dec_sub21_internal_op + connect \form \dec_sub21_form + connect \asmcode \dec_sub21_asmcode connect \in1_sel \dec_sub21_in1_sel connect \in2_sel \dec_sub21_in2_sel connect \in3_sel \dec_sub21_in3_sel connect \out_sel \dec_sub21_out_sel connect \cr_in \dec_sub21_cr_in connect \cr_out \dec_sub21_cr_out - connect \rc_sel \dec_sub21_rc_sel connect \ldst_len \dec_sub21_ldst_len connect \upd \dec_sub21_upd + connect \rc_sel \dec_sub21_rc_sel connect \cry_in \dec_sub21_cry_in connect \inv_a \dec_sub21_inv_a connect \inv_out \dec_sub21_inv_out @@ -146674,9 +255337,8 @@ module \dec31 connect \sgn \dec_sub21_sgn connect \lk \dec_sub21_lk connect \sgl_pipe \dec_sub21_sgl_pipe - connect \asmcode \dec_sub21_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub23_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -146690,40 +255352,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub23_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub23_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -146797,15 +255427,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub23_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub23_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub23_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -146822,20 +255486,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub23_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub23_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -146845,7 +255509,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -146853,71 +255517,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub23_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub23_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub23_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub23_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub23_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub23_asmcode cell \dec_sub23 \dec_sub23 connect \opcode_in \dec_sub23_opcode_in connect \function_unit \dec_sub23_function_unit - connect \form \dec_sub23_form connect \internal_op \dec_sub23_internal_op + connect \form \dec_sub23_form + connect \asmcode \dec_sub23_asmcode connect \in1_sel \dec_sub23_in1_sel connect \in2_sel \dec_sub23_in2_sel connect \in3_sel \dec_sub23_in3_sel connect \out_sel \dec_sub23_out_sel connect \cr_in \dec_sub23_cr_in connect \cr_out \dec_sub23_cr_out - connect \rc_sel \dec_sub23_rc_sel connect \ldst_len \dec_sub23_ldst_len connect \upd \dec_sub23_upd + connect \rc_sel \dec_sub23_rc_sel connect \cry_in \dec_sub23_cry_in connect \inv_a \dec_sub23_inv_a connect \inv_out \dec_sub23_inv_out @@ -146929,9 +255592,8 @@ module \dec31 connect \sgn \dec_sub23_sgn connect \lk \dec_sub23_lk connect \sgl_pipe \dec_sub23_sgl_pipe - connect \asmcode \dec_sub23_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub16_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -146945,40 +255607,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub16_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub16_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -147052,15 +255682,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub16_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub16_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub16_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -147077,20 +255741,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub16_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub16_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -147100,7 +255764,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -147108,71 +255772,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub16_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub16_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub16_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub16_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub16_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub16_asmcode cell \dec_sub16 \dec_sub16 connect \opcode_in \dec_sub16_opcode_in connect \function_unit \dec_sub16_function_unit - connect \form \dec_sub16_form connect \internal_op \dec_sub16_internal_op + connect \form \dec_sub16_form + connect \asmcode \dec_sub16_asmcode connect \in1_sel \dec_sub16_in1_sel connect \in2_sel \dec_sub16_in2_sel connect \in3_sel \dec_sub16_in3_sel connect \out_sel \dec_sub16_out_sel connect \cr_in \dec_sub16_cr_in connect \cr_out \dec_sub16_cr_out - connect \rc_sel \dec_sub16_rc_sel connect \ldst_len \dec_sub16_ldst_len connect \upd \dec_sub16_upd + connect \rc_sel \dec_sub16_rc_sel connect \cry_in \dec_sub16_cry_in connect \inv_a \dec_sub16_inv_a connect \inv_out \dec_sub16_inv_out @@ -147184,9 +255847,8 @@ module \dec31 connect \sgn \dec_sub16_sgn connect \lk \dec_sub16_lk connect \sgl_pipe \dec_sub16_sgl_pipe - connect \asmcode \dec_sub16_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub18_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -147200,40 +255862,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub18_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub18_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -147307,15 +255937,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub18_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub18_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub18_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -147332,20 +255996,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub18_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub18_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -147355,7 +256019,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -147363,71 +256027,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub18_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub18_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub18_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub18_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub18_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub18_asmcode cell \dec_sub18 \dec_sub18 connect \opcode_in \dec_sub18_opcode_in connect \function_unit \dec_sub18_function_unit - connect \form \dec_sub18_form connect \internal_op \dec_sub18_internal_op + connect \form \dec_sub18_form + connect \asmcode \dec_sub18_asmcode connect \in1_sel \dec_sub18_in1_sel connect \in2_sel \dec_sub18_in2_sel connect \in3_sel \dec_sub18_in3_sel connect \out_sel \dec_sub18_out_sel connect \cr_in \dec_sub18_cr_in connect \cr_out \dec_sub18_cr_out - connect \rc_sel \dec_sub18_rc_sel connect \ldst_len \dec_sub18_ldst_len connect \upd \dec_sub18_upd + connect \rc_sel \dec_sub18_rc_sel connect \cry_in \dec_sub18_cry_in connect \inv_a \dec_sub18_inv_a connect \inv_out \dec_sub18_inv_out @@ -147439,9 +256102,8 @@ module \dec31 connect \sgn \dec_sub18_sgn connect \lk \dec_sub18_lk connect \sgl_pipe \dec_sub18_sgl_pipe - connect \asmcode \dec_sub18_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub8_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -147455,40 +256117,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub8_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub8_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -147562,15 +256192,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub8_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub8_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub8_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -147587,20 +256251,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub8_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub8_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -147610,7 +256274,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -147618,71 +256282,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub8_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub8_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub8_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub8_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub8_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub8_asmcode cell \dec_sub8 \dec_sub8 connect \opcode_in \dec_sub8_opcode_in connect \function_unit \dec_sub8_function_unit - connect \form \dec_sub8_form connect \internal_op \dec_sub8_internal_op + connect \form \dec_sub8_form + connect \asmcode \dec_sub8_asmcode connect \in1_sel \dec_sub8_in1_sel connect \in2_sel \dec_sub8_in2_sel connect \in3_sel \dec_sub8_in3_sel connect \out_sel \dec_sub8_out_sel connect \cr_in \dec_sub8_cr_in connect \cr_out \dec_sub8_cr_out - connect \rc_sel \dec_sub8_rc_sel connect \ldst_len \dec_sub8_ldst_len connect \upd \dec_sub8_upd + connect \rc_sel \dec_sub8_rc_sel connect \cry_in \dec_sub8_cry_in connect \inv_a \dec_sub8_inv_a connect \inv_out \dec_sub8_inv_out @@ -147694,9 +256357,8 @@ module \dec31 connect \sgn \dec_sub8_sgn connect \lk \dec_sub8_lk connect \sgl_pipe \dec_sub8_sgl_pipe - connect \asmcode \dec_sub8_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub24_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -147710,40 +256372,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub24_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub24_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -147817,15 +256447,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub24_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub24_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub24_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -147842,20 +256506,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub24_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub24_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -147865,7 +256529,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -147873,71 +256537,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub24_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub24_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub24_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub24_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub24_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub24_asmcode cell \dec_sub24 \dec_sub24 connect \opcode_in \dec_sub24_opcode_in connect \function_unit \dec_sub24_function_unit - connect \form \dec_sub24_form connect \internal_op \dec_sub24_internal_op + connect \form \dec_sub24_form + connect \asmcode \dec_sub24_asmcode connect \in1_sel \dec_sub24_in1_sel connect \in2_sel \dec_sub24_in2_sel connect \in3_sel \dec_sub24_in3_sel connect \out_sel \dec_sub24_out_sel connect \cr_in \dec_sub24_cr_in connect \cr_out \dec_sub24_cr_out - connect \rc_sel \dec_sub24_rc_sel connect \ldst_len \dec_sub24_ldst_len connect \upd \dec_sub24_upd + connect \rc_sel \dec_sub24_rc_sel connect \cry_in \dec_sub24_cry_in connect \inv_a \dec_sub24_inv_a connect \inv_out \dec_sub24_inv_out @@ -147949,9 +256612,8 @@ module \dec31 connect \sgn \dec_sub24_sgn connect \lk \dec_sub24_lk connect \sgl_pipe \dec_sub24_sgl_pipe - connect \asmcode \dec_sub24_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_sub4_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -147965,40 +256627,8 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_sub4_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec_sub4_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -148072,15 +256702,49 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_sub4_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec_sub4_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec_sub4_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -148097,20 +256761,20 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub4_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub4_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -148120,7 +256784,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -148128,71 +256792,70 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_sub4_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec_sub4_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec_sub4_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub4_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_sub4_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec_sub4_asmcode cell \dec_sub4 \dec_sub4 connect \opcode_in \dec_sub4_opcode_in connect \function_unit \dec_sub4_function_unit - connect \form \dec_sub4_form connect \internal_op \dec_sub4_internal_op + connect \form \dec_sub4_form + connect \asmcode \dec_sub4_asmcode connect \in1_sel \dec_sub4_in1_sel connect \in2_sel \dec_sub4_in2_sel connect \in3_sel \dec_sub4_in3_sel connect \out_sel \dec_sub4_out_sel connect \cr_in \dec_sub4_cr_in connect \cr_out \dec_sub4_cr_out - connect \rc_sel \dec_sub4_rc_sel connect \ldst_len \dec_sub4_ldst_len connect \upd \dec_sub4_upd + connect \rc_sel \dec_sub4_rc_sel connect \cry_in \dec_sub4_cry_in connect \inv_a \dec_sub4_inv_a connect \inv_out \dec_sub4_inv_out @@ -148204,16 +256867,15 @@ module \dec31 connect \sgn \dec_sub4_sgn connect \lk \dec_sub4_lk connect \sgl_pipe \dec_sub4_sgl_pipe - connect \asmcode \dec_sub4_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 10 \opcode_switch process $group_0 assign \opcode_switch 10'0000000000 assign \opcode_switch \opcode_in [10:1] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" wire width 5 \opc_in process $group_1 assign \opc_in 5'00000 @@ -148312,670 +256974,670 @@ module \dec31 end process $group_20 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \function_unit \dec_sub10_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \function_unit \dec_sub28_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \function_unit \dec_sub0_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \function_unit \dec_sub26_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \function_unit \dec_sub19_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \function_unit \dec_sub22_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \function_unit \dec_sub9_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \function_unit \dec_sub11_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \function_unit \dec_sub27_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \function_unit \dec_sub15_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \function_unit \dec_sub20_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \function_unit \dec_sub21_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \function_unit \dec_sub23_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \function_unit \dec_sub16_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \function_unit \dec_sub18_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \function_unit \dec_sub8_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \function_unit \dec_sub24_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \function_unit \dec_sub4_function_unit end sync init end process $group_21 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \internal_op \dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \internal_op \dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \internal_op \dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \internal_op \dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \internal_op \dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \internal_op \dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \internal_op \dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \internal_op \dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \internal_op \dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \internal_op \dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \internal_op \dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \internal_op \dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \internal_op \dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \internal_op \dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \internal_op \dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \internal_op \dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \internal_op \dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \internal_op \dec_sub4_internal_op + end + sync init + end + process $group_22 assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \form \dec_sub10_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \form \dec_sub28_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \form \dec_sub0_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \form \dec_sub26_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \form \dec_sub19_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \form \dec_sub22_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \form \dec_sub9_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \form \dec_sub11_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \form \dec_sub27_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \form \dec_sub15_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \form \dec_sub20_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \form \dec_sub21_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \form \dec_sub23_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \form \dec_sub16_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \form \dec_sub18_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \form \dec_sub8_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \form \dec_sub24_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \form \dec_sub4_form end sync init end - process $group_22 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + process $group_23 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 - assign \internal_op \dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 - assign \internal_op \dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 - assign \internal_op \dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 - assign \internal_op \dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 - assign \internal_op \dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 - assign \internal_op \dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 - assign \internal_op \dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 - assign \internal_op \dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 - assign \internal_op \dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 - assign \internal_op \dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 - assign \internal_op \dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 - assign \internal_op \dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 - assign \internal_op \dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 - assign \internal_op \dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 - assign \internal_op \dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 - assign \internal_op \dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 - assign \internal_op \dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + assign \asmcode \dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 - assign \internal_op \dec_sub4_internal_op + assign \asmcode \dec_sub4_asmcode end sync init end - process $group_23 + process $group_24 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \in1_sel \dec_sub10_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \in1_sel \dec_sub28_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \in1_sel \dec_sub0_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \in1_sel \dec_sub26_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \in1_sel \dec_sub19_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \in1_sel \dec_sub22_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \in1_sel \dec_sub9_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \in1_sel \dec_sub11_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \in1_sel \dec_sub27_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \in1_sel \dec_sub15_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \in1_sel \dec_sub20_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \in1_sel \dec_sub21_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \in1_sel \dec_sub23_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \in1_sel \dec_sub16_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \in1_sel \dec_sub18_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \in1_sel \dec_sub8_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \in1_sel \dec_sub24_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \in1_sel \dec_sub4_in1_sel end sync init end - process $group_24 + process $group_25 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \in2_sel \dec_sub10_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \in2_sel \dec_sub28_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \in2_sel \dec_sub0_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \in2_sel \dec_sub26_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \in2_sel \dec_sub19_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \in2_sel \dec_sub22_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \in2_sel \dec_sub9_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \in2_sel \dec_sub11_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \in2_sel \dec_sub27_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \in2_sel \dec_sub15_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \in2_sel \dec_sub20_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \in2_sel \dec_sub21_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \in2_sel \dec_sub23_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \in2_sel \dec_sub16_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \in2_sel \dec_sub18_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \in2_sel \dec_sub8_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \in2_sel \dec_sub24_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \in2_sel \dec_sub4_in2_sel end sync init end - process $group_25 + process $group_26 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \in3_sel \dec_sub10_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \in3_sel \dec_sub28_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \in3_sel \dec_sub0_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \in3_sel \dec_sub26_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \in3_sel \dec_sub19_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \in3_sel \dec_sub22_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \in3_sel \dec_sub9_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \in3_sel \dec_sub11_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \in3_sel \dec_sub27_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \in3_sel \dec_sub15_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \in3_sel \dec_sub20_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \in3_sel \dec_sub21_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \in3_sel \dec_sub23_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \in3_sel \dec_sub16_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \in3_sel \dec_sub18_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \in3_sel \dec_sub8_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \in3_sel \dec_sub24_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \in3_sel \dec_sub4_in3_sel end sync init end - process $group_26 + process $group_27 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \out_sel \dec_sub10_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \out_sel \dec_sub28_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \out_sel \dec_sub0_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \out_sel \dec_sub26_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \out_sel \dec_sub19_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \out_sel \dec_sub22_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \out_sel \dec_sub9_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \out_sel \dec_sub11_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \out_sel \dec_sub27_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \out_sel \dec_sub15_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \out_sel \dec_sub20_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \out_sel \dec_sub21_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \out_sel \dec_sub23_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \out_sel \dec_sub16_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \out_sel \dec_sub18_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \out_sel \dec_sub8_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \out_sel \dec_sub24_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \out_sel \dec_sub4_out_sel end sync init end - process $group_27 + process $group_28 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \cr_in \dec_sub10_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \cr_in \dec_sub28_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \cr_in \dec_sub0_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \cr_in \dec_sub26_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \cr_in \dec_sub19_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \cr_in \dec_sub22_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \cr_in \dec_sub9_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \cr_in \dec_sub11_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \cr_in \dec_sub27_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \cr_in \dec_sub15_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \cr_in \dec_sub20_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \cr_in \dec_sub21_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \cr_in \dec_sub23_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \cr_in \dec_sub16_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \cr_in \dec_sub18_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \cr_in \dec_sub8_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \cr_in \dec_sub24_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \cr_in \dec_sub4_cr_in end sync init end - process $group_28 + process $group_29 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \cr_out \dec_sub10_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \cr_out \dec_sub28_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \cr_out \dec_sub0_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \cr_out \dec_sub26_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \cr_out \dec_sub19_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \cr_out \dec_sub22_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \cr_out \dec_sub9_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \cr_out \dec_sub11_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \cr_out \dec_sub27_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \cr_out \dec_sub15_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \cr_out \dec_sub20_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \cr_out \dec_sub21_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \cr_out \dec_sub23_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \cr_out \dec_sub16_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \cr_out \dec_sub18_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \cr_out \dec_sub8_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \cr_out \dec_sub24_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \cr_out \dec_sub4_cr_out end sync init end - process $group_29 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01010 - assign \rc_sel \dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11100 - assign \rc_sel \dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'00000 - assign \rc_sel \dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11010 - assign \rc_sel \dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10011 - assign \rc_sel \dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10110 - assign \rc_sel \dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01001 - assign \rc_sel \dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01011 - assign \rc_sel \dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11011 - assign \rc_sel \dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01111 - assign \rc_sel \dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10100 - assign \rc_sel \dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10101 - assign \rc_sel \dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10111 - assign \rc_sel \dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10000 - assign \rc_sel \dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10010 - assign \rc_sel \dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01000 - assign \rc_sel \dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11000 - assign \rc_sel \dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'00100 - assign \rc_sel \dec_sub4_rc_sel - end - sync init - end process $group_30 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \ldst_len \dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \ldst_len \dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \ldst_len \dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \ldst_len \dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \ldst_len \dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \ldst_len \dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \ldst_len \dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \ldst_len \dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \ldst_len \dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \ldst_len \dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \ldst_len \dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \ldst_len \dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \ldst_len \dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \ldst_len \dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \ldst_len \dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \ldst_len \dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \ldst_len \dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \ldst_len \dec_sub4_ldst_len end @@ -148983,802 +257645,802 @@ module \dec31 end process $group_31 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \upd \dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \upd \dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \upd \dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \upd \dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \upd \dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \upd \dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \upd \dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \upd \dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \upd \dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \upd \dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \upd \dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \upd \dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \upd \dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \upd \dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \upd \dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \upd \dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \upd \dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \upd \dec_sub4_upd end sync init end process $group_32 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01010 + assign \rc_sel \dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11100 + assign \rc_sel \dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00000 + assign \rc_sel \dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11010 + assign \rc_sel \dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10011 + assign \rc_sel \dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10110 + assign \rc_sel \dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01001 + assign \rc_sel \dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01011 + assign \rc_sel \dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11011 + assign \rc_sel \dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01111 + assign \rc_sel \dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10100 + assign \rc_sel \dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10101 + assign \rc_sel \dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10111 + assign \rc_sel \dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10000 + assign \rc_sel \dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'10010 + assign \rc_sel \dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'01000 + assign \rc_sel \dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'11000 + assign \rc_sel \dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" + case 5'00100 + assign \rc_sel \dec_sub4_rc_sel + end + sync init + end + process $group_33 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \cry_in \dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \cry_in \dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \cry_in \dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \cry_in \dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \cry_in \dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \cry_in \dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \cry_in \dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \cry_in \dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \cry_in \dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \cry_in \dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \cry_in \dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \cry_in \dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \cry_in \dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \cry_in \dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \cry_in \dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \cry_in \dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \cry_in \dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \cry_in \dec_sub4_cry_in end sync init end - process $group_33 + process $group_34 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \inv_a \dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \inv_a \dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \inv_a \dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \inv_a \dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \inv_a \dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \inv_a \dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \inv_a \dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \inv_a \dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \inv_a \dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \inv_a \dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \inv_a \dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \inv_a \dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \inv_a \dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \inv_a \dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \inv_a \dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \inv_a \dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \inv_a \dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \inv_a \dec_sub4_inv_a end sync init end - process $group_34 + process $group_35 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \inv_out \dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \inv_out \dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \inv_out \dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \inv_out \dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \inv_out \dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \inv_out \dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \inv_out \dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \inv_out \dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \inv_out \dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \inv_out \dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \inv_out \dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \inv_out \dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \inv_out \dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \inv_out \dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \inv_out \dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \inv_out \dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \inv_out \dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \inv_out \dec_sub4_inv_out end sync init end - process $group_35 + process $group_36 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \cry_out \dec_sub10_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \cry_out \dec_sub28_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \cry_out \dec_sub0_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \cry_out \dec_sub26_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \cry_out \dec_sub19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \cry_out \dec_sub22_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \cry_out \dec_sub9_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \cry_out \dec_sub11_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \cry_out \dec_sub27_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \cry_out \dec_sub15_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \cry_out \dec_sub20_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \cry_out \dec_sub21_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \cry_out \dec_sub23_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \cry_out \dec_sub16_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \cry_out \dec_sub18_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \cry_out \dec_sub8_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \cry_out \dec_sub24_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \cry_out \dec_sub4_cry_out end sync init end - process $group_36 + process $group_37 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \br \dec_sub10_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \br \dec_sub28_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \br \dec_sub0_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \br \dec_sub26_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \br \dec_sub19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \br \dec_sub22_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \br \dec_sub9_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \br \dec_sub11_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \br \dec_sub27_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \br \dec_sub15_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \br \dec_sub20_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \br \dec_sub21_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \br \dec_sub23_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \br \dec_sub16_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \br \dec_sub18_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \br \dec_sub8_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \br \dec_sub24_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \br \dec_sub4_br end sync init end - process $group_37 + process $group_38 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \sgn_ext \dec_sub10_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \sgn_ext \dec_sub28_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \sgn_ext \dec_sub0_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \sgn_ext \dec_sub26_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \sgn_ext \dec_sub19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \sgn_ext \dec_sub22_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \sgn_ext \dec_sub9_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \sgn_ext \dec_sub11_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \sgn_ext \dec_sub27_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \sgn_ext \dec_sub15_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \sgn_ext \dec_sub20_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \sgn_ext \dec_sub21_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \sgn_ext \dec_sub23_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \sgn_ext \dec_sub16_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \sgn_ext \dec_sub18_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \sgn_ext \dec_sub8_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \sgn_ext \dec_sub24_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \sgn_ext \dec_sub4_sgn_ext end sync init end - process $group_38 + process $group_39 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \rsrv \dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \rsrv \dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \rsrv \dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \rsrv \dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \rsrv \dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \rsrv \dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \rsrv \dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \rsrv \dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \rsrv \dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \rsrv \dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \rsrv \dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \rsrv \dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \rsrv \dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \rsrv \dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \rsrv \dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \rsrv \dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \rsrv \dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \rsrv \dec_sub4_rsrv end sync init end - process $group_39 + process $group_40 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \is_32b \dec_sub10_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \is_32b \dec_sub28_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \is_32b \dec_sub0_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \is_32b \dec_sub26_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \is_32b \dec_sub19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \is_32b \dec_sub22_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \is_32b \dec_sub9_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \is_32b \dec_sub11_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \is_32b \dec_sub27_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \is_32b \dec_sub15_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \is_32b \dec_sub20_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \is_32b \dec_sub21_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \is_32b \dec_sub23_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \is_32b \dec_sub16_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \is_32b \dec_sub18_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \is_32b \dec_sub8_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \is_32b \dec_sub24_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \is_32b \dec_sub4_is_32b end sync init end - process $group_40 + process $group_41 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \sgn \dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \sgn \dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \sgn \dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \sgn \dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \sgn \dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \sgn \dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \sgn \dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \sgn \dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \sgn \dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \sgn \dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \sgn \dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \sgn \dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \sgn \dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \sgn \dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \sgn \dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \sgn \dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \sgn \dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \sgn \dec_sub4_sgn end sync init end - process $group_41 + process $group_42 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \lk \dec_sub10_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \lk \dec_sub28_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \lk \dec_sub0_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \lk \dec_sub26_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \lk \dec_sub19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \lk \dec_sub22_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \lk \dec_sub9_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \lk \dec_sub11_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \lk \dec_sub27_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \lk \dec_sub15_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \lk \dec_sub20_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \lk \dec_sub21_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \lk \dec_sub23_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \lk \dec_sub16_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \lk \dec_sub18_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \lk \dec_sub8_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \lk \dec_sub24_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \lk \dec_sub4_lk end sync init end - process $group_42 + process $group_43 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01010 assign \sgl_pipe \dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11100 assign \sgl_pipe \dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00000 assign \sgl_pipe \dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11010 assign \sgl_pipe \dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10011 assign \sgl_pipe \dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10110 assign \sgl_pipe \dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01001 assign \sgl_pipe \dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01011 assign \sgl_pipe \dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11011 assign \sgl_pipe \dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01111 assign \sgl_pipe \dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10100 assign \sgl_pipe \dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10101 assign \sgl_pipe \dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10111 assign \sgl_pipe \dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10000 assign \sgl_pipe \dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'10010 assign \sgl_pipe \dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'01000 assign \sgl_pipe \dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'11000 assign \sgl_pipe \dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" case 5'00100 assign \sgl_pipe \dec_sub4_sgl_pipe end sync init end - process $group_43 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01010 - assign \asmcode \dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11100 - assign \asmcode \dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'00000 - assign \asmcode \dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11010 - assign \asmcode \dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10011 - assign \asmcode \dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10110 - assign \asmcode \dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01001 - assign \asmcode \dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01011 - assign \asmcode \dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11011 - assign \asmcode \dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01111 - assign \asmcode \dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10100 - assign \asmcode \dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10101 - assign \asmcode \dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10111 - assign \asmcode \dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10000 - assign \asmcode \dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'10010 - assign \asmcode \dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'01000 - assign \asmcode \dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'11000 - assign \asmcode \dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" - case 5'00100 - assign \asmcode \dec_sub4_asmcode - end - sync init - end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" module \dec58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -149792,40 +258454,8 @@ module \dec58 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -149899,16 +258529,50 @@ module \dec58 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -149924,21 +258588,21 @@ module \dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -149947,66 +258611,64 @@ module \dec58 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 2 \opcode_switch process $group_0 assign \opcode_switch 2'00 @@ -150015,63 +258677,63 @@ module \dec58 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \function_unit 11'00000000100 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 - assign \form 5'00101 + assign \internal_op 7'0100101 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 - assign \internal_op 7'0100101 + assign \form 5'00101 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \in1_sel 3'010 end @@ -150079,15 +258741,15 @@ module \dec58 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \in2_sel 4'1000 end @@ -150095,15 +258757,15 @@ module \dec58 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \in3_sel 2'00 end @@ -150111,15 +258773,15 @@ module \dec58 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \out_sel 2'01 end @@ -150127,15 +258789,15 @@ module \dec58 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \cr_in 3'000 end @@ -150143,15 +258805,15 @@ module \dec58 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \cr_out 3'000 end @@ -150159,15 +258821,15 @@ module \dec58 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \ldst_len 4'0100 end @@ -150175,15 +258837,15 @@ module \dec58 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \upd 2'00 end @@ -150191,15 +258853,15 @@ module \dec58 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \rc_sel 2'00 end @@ -150207,15 +258869,15 @@ module \dec58 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \cry_in 2'00 end @@ -150223,15 +258885,15 @@ module \dec58 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \asmcode 8'01010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \asmcode 8'01010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \asmcode 8'01100010 end @@ -150239,15 +258901,15 @@ module \dec58 end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \inv_a 1'0 end @@ -150255,15 +258917,15 @@ module \dec58 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \inv_out 1'0 end @@ -150271,15 +258933,15 @@ module \dec58 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \cry_out 1'0 end @@ -150287,15 +258949,15 @@ module \dec58 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \br 1'0 end @@ -150303,15 +258965,15 @@ module \dec58 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \sgn_ext 1'1 end @@ -150319,15 +258981,15 @@ module \dec58 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \rsrv 1'0 end @@ -150335,15 +258997,15 @@ module \dec58 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \is_32b 1'0 end @@ -150351,15 +259013,15 @@ module \dec58 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \sgn 1'0 end @@ -150367,15 +259029,15 @@ module \dec58 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \lk 1'0 end @@ -150383,15 +259045,15 @@ module \dec58 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'10 assign \sgl_pipe 1'1 end @@ -150401,7 +259063,7 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" module \dec62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -150415,40 +259077,8 @@ module \dec62 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -150522,16 +259152,50 @@ module \dec62 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 2 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 output 3 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 output 4 \asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 4 \in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -150547,21 +259211,21 @@ module \dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 5 \in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 6 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 6 \in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 7 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 7 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -150570,66 +259234,64 @@ module \dec62 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 9 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 10 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 10 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 output 11 \ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 output 12 \upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 13 \rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 15 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 16 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 17 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 18 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 19 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 20 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 21 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 22 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 23 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 24 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 2 \opcode_switch process $group_0 assign \opcode_switch 2'00 @@ -150638,51 +259300,51 @@ module \dec62 end process $group_1 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \function_unit 11'00000000100 end sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 - assign \form 5'00101 + assign \internal_op 7'0100110 end sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 - assign \internal_op 7'0100110 + assign \form 5'00101 end sync init end process $group_4 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \in1_sel 3'010 end @@ -150690,12 +259352,12 @@ module \dec62 end process $group_5 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \in2_sel 4'1000 end @@ -150703,12 +259365,12 @@ module \dec62 end process $group_6 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \in3_sel 2'01 end @@ -150716,12 +259378,12 @@ module \dec62 end process $group_7 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \out_sel 2'00 end @@ -150729,12 +259391,12 @@ module \dec62 end process $group_8 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cr_in 3'000 end @@ -150742,12 +259404,12 @@ module \dec62 end process $group_9 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cr_out 3'000 end @@ -150755,12 +259417,12 @@ module \dec62 end process $group_10 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \ldst_len 4'1000 end @@ -150768,12 +259430,12 @@ module \dec62 end process $group_11 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \upd 2'01 end @@ -150781,12 +259443,12 @@ module \dec62 end process $group_12 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \rc_sel 2'00 end @@ -150794,12 +259456,12 @@ module \dec62 end process $group_13 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cry_in 2'00 end @@ -150807,25 +259469,25 @@ module \dec62 end process $group_14 assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 - assign \asmcode 8'10101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 - assign \asmcode 8'10101100 + assign \asmcode 8'10101110 end sync init end process $group_15 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \inv_a 1'0 end @@ -150833,12 +259495,12 @@ module \dec62 end process $group_16 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \inv_out 1'0 end @@ -150846,12 +259508,12 @@ module \dec62 end process $group_17 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \cry_out 1'0 end @@ -150859,12 +259521,12 @@ module \dec62 end process $group_18 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \br 1'0 end @@ -150872,12 +259534,12 @@ module \dec62 end process $group_19 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \sgn_ext 1'0 end @@ -150885,12 +259547,12 @@ module \dec62 end process $group_20 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \rsrv 1'0 end @@ -150898,12 +259560,12 @@ module \dec62 end process $group_21 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \is_32b 1'0 end @@ -150911,12 +259573,12 @@ module \dec62 end process $group_22 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \sgn 1'0 end @@ -150924,12 +259586,12 @@ module \dec62 end process $group_23 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \lk 1'0 end @@ -150937,12 +259599,12 @@ module \dec62 end process $group_24 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'00 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 2'01 assign \sgl_pipe 1'1 end @@ -150951,57 +259613,19 @@ module \dec62 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec" -module \dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" +module \dec$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" wire width 1 input 0 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 output 2 \opcode_in - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 output 3 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 output 4 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 5 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 6 \out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 output 7 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 3 \rc_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -151010,16 +259634,16 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 3 output 8 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 4 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" - wire width 3 output 9 \cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 5 \cr_out attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -151093,8 +259717,8 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 output 10 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 output 6 \internal_op attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -151107,96 +259731,102 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 11 output 11 \function_unit - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 4 output 12 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 13 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 14 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 11 output 7 \function_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" - wire width 2 output 15 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 17 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 18 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 19 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 1 output 20 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 21 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 output 22 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 9 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 11 \LK + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 14 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 15 \out_sel attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" - wire width 2 output 23 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 24 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 25 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 26 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 27 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 16 output 28 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 16 output 29 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 30 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 6 output 31 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 24 output 32 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 1 output 33 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 1 output 34 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 14 output 35 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 36 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 37 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 38 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 39 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 40 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 14 output 41 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 output 42 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 10 output 43 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 3 output 44 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 3 output 45 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 output 46 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 10 output 47 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 output 16 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 17 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 18 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 19 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 20 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 21 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 output 22 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 23 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 24 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 25 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 output 26 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 27 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 28 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 output 29 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 output 30 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 31 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 output 32 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 output 33 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 output 34 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -151210,40 +259840,8 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec19_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec19_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -151317,15 +259915,49 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec19_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec19_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec19_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -151342,20 +259974,20 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec19_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec19_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -151365,7 +259997,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -151373,71 +260005,70 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec19_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec19_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec19_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec19_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec19_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec19_asmcode cell \dec19 \dec19 connect \opcode_in \dec19_opcode_in connect \function_unit \dec19_function_unit - connect \form \dec19_form connect \internal_op \dec19_internal_op + connect \form \dec19_form + connect \asmcode \dec19_asmcode connect \in1_sel \dec19_in1_sel connect \in2_sel \dec19_in2_sel connect \in3_sel \dec19_in3_sel connect \out_sel \dec19_out_sel connect \cr_in \dec19_cr_in connect \cr_out \dec19_cr_out - connect \rc_sel \dec19_rc_sel connect \ldst_len \dec19_ldst_len connect \upd \dec19_upd + connect \rc_sel \dec19_rc_sel connect \cry_in \dec19_cry_in connect \inv_a \dec19_inv_a connect \inv_out \dec19_inv_out @@ -151449,9 +260080,8 @@ module \dec connect \sgn \dec19_sgn connect \lk \dec19_lk connect \sgl_pipe \dec19_sgl_pipe - connect \asmcode \dec19_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec30_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -151465,40 +260095,8 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec30_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec30_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -151572,15 +260170,49 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec30_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec30_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec30_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -151597,20 +260229,20 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec30_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec30_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -151620,7 +260252,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -151628,71 +260260,70 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec30_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec30_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec30_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec30_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec30_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec30_asmcode cell \dec30 \dec30 connect \opcode_in \dec30_opcode_in connect \function_unit \dec30_function_unit - connect \form \dec30_form connect \internal_op \dec30_internal_op + connect \form \dec30_form + connect \asmcode \dec30_asmcode connect \in1_sel \dec30_in1_sel connect \in2_sel \dec30_in2_sel connect \in3_sel \dec30_in3_sel connect \out_sel \dec30_out_sel connect \cr_in \dec30_cr_in connect \cr_out \dec30_cr_out - connect \rc_sel \dec30_rc_sel connect \ldst_len \dec30_ldst_len connect \upd \dec30_upd + connect \rc_sel \dec30_rc_sel connect \cry_in \dec30_cry_in connect \inv_a \dec30_inv_a connect \inv_out \dec30_inv_out @@ -151704,9 +260335,8 @@ module \dec connect \sgn \dec30_sgn connect \lk \dec30_lk connect \sgl_pipe \dec30_sgl_pipe - connect \asmcode \dec30_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -151720,40 +260350,8 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec31_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec31_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -151827,15 +260425,49 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec31_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec31_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec31_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -151852,20 +260484,20 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec31_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec31_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -151875,7 +260507,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -151883,71 +260515,70 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec31_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec31_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec31_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec31_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec31_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec31_asmcode cell \dec31 \dec31 connect \opcode_in \dec31_opcode_in connect \function_unit \dec31_function_unit - connect \form \dec31_form connect \internal_op \dec31_internal_op + connect \form \dec31_form + connect \asmcode \dec31_asmcode connect \in1_sel \dec31_in1_sel connect \in2_sel \dec31_in2_sel connect \in3_sel \dec31_in3_sel connect \out_sel \dec31_out_sel connect \cr_in \dec31_cr_in connect \cr_out \dec31_cr_out - connect \rc_sel \dec31_rc_sel connect \ldst_len \dec31_ldst_len connect \upd \dec31_upd + connect \rc_sel \dec31_rc_sel connect \cry_in \dec31_cry_in connect \inv_a \dec31_inv_a connect \inv_out \dec31_inv_out @@ -151959,9 +260590,8 @@ module \dec connect \sgn \dec31_sgn connect \lk \dec31_lk connect \sgl_pipe \dec31_sgl_pipe - connect \asmcode \dec31_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec58_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -151975,8 +260605,83 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec58_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 \dec58_internal_op attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -152007,90 +260712,17 @@ module \dec attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 5 \dec58_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec58_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -152107,20 +260739,20 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec58_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec58_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -152130,7 +260762,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -152138,71 +260770,70 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec58_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec58_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec58_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec58_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec58_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec58_asmcode cell \dec58 \dec58 connect \opcode_in \dec58_opcode_in connect \function_unit \dec58_function_unit - connect \form \dec58_form connect \internal_op \dec58_internal_op + connect \form \dec58_form + connect \asmcode \dec58_asmcode connect \in1_sel \dec58_in1_sel connect \in2_sel \dec58_in2_sel connect \in3_sel \dec58_in3_sel connect \out_sel \dec58_out_sel connect \cr_in \dec58_cr_in connect \cr_out \dec58_cr_out - connect \rc_sel \dec58_rc_sel connect \ldst_len \dec58_ldst_len connect \upd \dec58_upd + connect \rc_sel \dec58_rc_sel connect \cry_in \dec58_cry_in connect \inv_a \dec58_inv_a connect \inv_out \dec58_inv_out @@ -152214,9 +260845,8 @@ module \dec connect \sgn \dec58_sgn connect \lk \dec58_lk connect \sgl_pipe \dec58_sgl_pipe - connect \asmcode \dec58_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec62_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -152230,40 +260860,8 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec62_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 5 \dec62_form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -152337,15 +260935,49 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec62_internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 5 \dec62_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \dec62_asmcode attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -152362,20 +260994,20 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec62_in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec62_out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -152385,7 +261017,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -152393,71 +261025,70 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec62_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" - wire width 2 \dec62_rc_sel attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 4 \dec62_ldst_len attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec62_upd + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec62_rc_sel attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \dec62_asmcode cell \dec62 \dec62 connect \opcode_in \dec62_opcode_in connect \function_unit \dec62_function_unit - connect \form \dec62_form connect \internal_op \dec62_internal_op + connect \form \dec62_form + connect \asmcode \dec62_asmcode connect \in1_sel \dec62_in1_sel connect \in2_sel \dec62_in2_sel connect \in3_sel \dec62_in3_sel connect \out_sel \dec62_out_sel connect \cr_in \dec62_cr_in connect \cr_out \dec62_cr_out - connect \rc_sel \dec62_rc_sel connect \ldst_len \dec62_ldst_len connect \upd \dec62_upd + connect \rc_sel \dec62_rc_sel connect \cry_in \dec62_cry_in connect \inv_a \dec62_inv_a connect \inv_out \dec62_inv_out @@ -152469,9 +261100,8 @@ module \dec connect \sgn \dec62_sgn connect \lk \dec62_lk connect \sgl_pipe \dec62_sgl_pipe - connect \asmcode \dec62_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 6 \opcode_switch process $group_0 assign \opcode_switch 6'000000 @@ -152503,150 +261133,292 @@ module \dec assign \dec62_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" wire width 32 \opcode_switch$1 process $group_6 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \function_unit \dec19_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \function_unit \dec30_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \function_unit \dec31_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \function_unit \dec58_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \function_unit \dec62_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \function_unit 11'00000010000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \function_unit 11'00000000000 end sync init end + process $group_7 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \internal_op \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \internal_op \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \internal_op \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \internal_op \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \internal_op \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010001 + assign \internal_op 7'1001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \internal_op 7'0000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \internal_op 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000010 + assign \internal_op 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000011 + assign \internal_op 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \internal_op 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \internal_op 7'1000011 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 32'000000---------------0100000000- + assign \internal_op 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 32'01100000000000000000000000000000 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 32'000001---------------0000000011- + assign \internal_op 7'1000100 + end + sync init + end attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -152677,1423 +261449,1290 @@ module \dec attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 5 \form - process $group_7 + process $group_8 assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \form \dec19_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \form \dec30_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \form \dec31_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \form \dec58_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \form \dec62_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \form 5'00011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \form 5'00001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \form 5'00100 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \form 5'00000 end sync init end - process $group_8 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 8 \asmcode + process $group_9 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 - assign \internal_op \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + assign \asmcode \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 - assign \internal_op \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + assign \asmcode \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 - assign \internal_op \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + assign \asmcode \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 - assign \internal_op \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + assign \asmcode \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 - assign \internal_op \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 - assign \internal_op 7'1001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 - assign \internal_op 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 - assign \internal_op 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'01101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'11000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'11001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'11001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 - assign \internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'11001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 - assign \internal_op 7'1000011 + assign \asmcode 8'11001111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- - assign \internal_op 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'00010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + assign \asmcode 8'10000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- - assign \internal_op 7'1000100 + assign \asmcode 8'10011100 end sync init end - process $group_9 + process $group_10 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \in1_sel \dec19_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \in1_sel \dec30_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \in1_sel \dec31_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \in1_sel \dec58_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \in1_sel \dec62_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \in1_sel 3'100 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \in1_sel 3'000 end sync init end - process $group_10 + process $group_11 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \in2_sel \dec19_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \in2_sel \dec30_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \in2_sel \dec31_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \in2_sel \dec58_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \in2_sel \dec62_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \in2_sel 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \in2_sel 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \in2_sel 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \in2_sel 4'0100 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \in2_sel 4'0000 end sync init end - process $group_11 + process $group_12 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \in3_sel \dec19_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \in3_sel \dec30_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \in3_sel \dec31_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \in3_sel \dec58_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \in3_sel \dec62_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \in3_sel 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \in3_sel 2'00 end sync init end - process $group_12 + process $group_13 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \out_sel \dec19_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \out_sel \dec30_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \out_sel \dec31_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \out_sel \dec58_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \out_sel \dec62_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \out_sel 2'10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \out_sel 2'01 end sync init end - process $group_13 + process $group_14 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \cr_in \dec19_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \cr_in \dec30_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \cr_in \dec31_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \cr_in \dec58_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \cr_in \dec62_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \cr_in 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \cr_in 3'000 end sync init end - process $group_14 + process $group_15 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \cr_out \dec19_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \cr_out \dec30_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \cr_out \dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \cr_out \dec58_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \cr_out \dec62_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \cr_out 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \cr_out 3'000 end sync init end - process $group_15 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'010011 - assign \rc_sel \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'011110 - assign \rc_sel \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'011111 - assign \rc_sel \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'111010 - assign \rc_sel \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'111110 - assign \rc_sel \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001101 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011100 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011101 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'000111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'000010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'000011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011011 - assign \rc_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 32'000000---------------0100000000- - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 32'01100000000000000000000000000000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 32'000001---------------0000000011- - assign \rc_sel 2'00 - end - sync init - end + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \ldst_len process $group_16 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \ldst_len \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \ldst_len \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \ldst_len \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \ldst_len \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \ldst_len \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \ldst_len 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \ldst_len 4'0000 end @@ -154101,1863 +262740,1874 @@ module \dec end process $group_17 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \upd \dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \upd \dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \upd \dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \upd \dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \upd \dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \upd 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \upd 2'00 end sync init end process $group_18 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'010011 + assign \rc_sel \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011110 + assign \rc_sel \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'011111 + assign \rc_sel \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111010 + assign \rc_sel \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" + case 6'111110 + assign \rc_sel \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001101 + assign \rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011100 + assign \rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011101 + assign \rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'010111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'101101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'100101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'001000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'000011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 6'011011 + assign \rc_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 32'000000---------------0100000000- + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 32'01100000000000000000000000000000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" + case 32'000001---------------0000000011- + assign \rc_sel 2'00 + end + sync init + end + process $group_19 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \cry_in \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \cry_in \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \cry_in \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \cry_in \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \cry_in \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \cry_in 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \cry_in 2'00 end sync init end - process $group_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \inv_a + process $group_20 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \inv_a \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \inv_a \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \inv_a \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \inv_a \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \inv_a \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \inv_a 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \inv_a 1'0 end sync init end - process $group_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \inv_out + process $group_21 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \inv_out \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \inv_out \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \inv_out \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \inv_out \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \inv_out \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \inv_out 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \inv_out 1'0 end sync init end - process $group_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \cry_out + process $group_22 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \cry_out \dec19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \cry_out \dec30_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \cry_out \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \cry_out \dec58_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \cry_out \dec62_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \cry_out 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \cry_out 1'0 end sync init end - process $group_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \br + process $group_23 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \br \dec19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \br \dec30_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \br \dec31_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \br \dec58_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \br \dec62_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \br 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \br 1'0 end sync init end - process $group_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \sgn_ext + process $group_24 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \sgn_ext \dec19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \sgn_ext \dec30_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \sgn_ext \dec31_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \sgn_ext \dec58_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \sgn_ext \dec62_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \sgn_ext 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \sgn_ext 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \rsrv - process $group_24 + process $group_25 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \rsrv \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \rsrv \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \rsrv \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \rsrv \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \rsrv \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \rsrv 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \rsrv 1'0 end sync init end - process $group_25 + process $group_26 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \is_32b \dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \is_32b \dec30_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \is_32b \dec31_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \is_32b \dec58_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \is_32b \dec62_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \is_32b 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \is_32b 1'0 end sync init end - process $group_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" + wire width 1 \sgn + process $group_27 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \sgn \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \sgn \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \sgn \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \sgn \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \sgn \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \sgn 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \sgn 1'0 end sync init end - process $group_27 + process $group_28 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \lk \dec19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \lk \dec30_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \lk \dec31_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \lk \dec58_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \lk \dec62_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \lk 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \lk 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \sgl_pipe - process $group_28 + process $group_29 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'010011 assign \sgl_pipe \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011110 assign \sgl_pipe \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'011111 assign \sgl_pipe \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111010 assign \sgl_pipe \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" case 6'111110 assign \sgl_pipe \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001110 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001011 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100000 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100001 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011001 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010100 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010101 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'010111 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100110 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100111 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'101101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100100 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'100101 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'001000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000010 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'000011 assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011010 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 6'011011 assign \sgl_pipe 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000000---------------0100000000- assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'01100000000000000000000000000000 assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" case 32'000001---------------0000000011- assign \sgl_pipe 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 8 \asmcode - process $group_29 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'010011 - assign \asmcode \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'011110 - assign \asmcode \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'011111 - assign \asmcode \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'111010 - assign \asmcode \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - case 6'111110 - assign \asmcode \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001100 - assign \asmcode 8'00000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001101 - assign \asmcode 8'00001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001110 - assign \asmcode 8'00000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001111 - assign \asmcode 8'00001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011100 - assign \asmcode 8'00010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011101 - assign \asmcode 8'00010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010010 - assign \asmcode 8'00010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010000 - assign \asmcode 8'00010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001011 - assign \asmcode 8'00011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001010 - assign \asmcode 8'00011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100010 - assign \asmcode 8'01001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100011 - assign \asmcode 8'01001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101010 - assign \asmcode 8'01011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101011 - assign \asmcode 8'01011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101000 - assign \asmcode 8'01011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101001 - assign \asmcode 8'01011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100000 - assign \asmcode 8'01100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100001 - assign \asmcode 8'01101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'000111 - assign \asmcode 8'01111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011000 - assign \asmcode 8'10001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011001 - assign \asmcode 8'10001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010100 - assign \asmcode 8'10010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010101 - assign \asmcode 8'10011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'010111 - assign \asmcode 8'10011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100110 - assign \asmcode 8'10100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100111 - assign \asmcode 8'10100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101100 - assign \asmcode 8'10101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'101101 - assign \asmcode 8'10110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100100 - assign \asmcode 8'10110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'100101 - assign \asmcode 8'10111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'001000 - assign \asmcode 8'11000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'000010 - assign \asmcode 8'11001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'000011 - assign \asmcode 8'11001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011010 - assign \asmcode 8'11001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 6'011011 - assign \asmcode 8'11001101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 32'000000---------------0100000000- - assign \asmcode 8'00010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 32'01100000000000000000000000000000 - assign \asmcode 8'10000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" - case 32'000001---------------0000000011- - assign \asmcode 8'10011011 - end - sync init - end process $group_30 assign \opcode_switch$1 32'00000000000000000000000000000000 assign \opcode_switch$1 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:370" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" wire width 32 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:370" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" cell $mux $3 parameter \WIDTH 32 connect \A \raw_opcode_in @@ -155990,47 +264640,57 @@ module \dec assign \RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \SI process $group_36 assign \SI 16'0000000000000000 assign \SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 16 \UI process $group_37 assign \UI 16'0000000000000000 assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 1 \L process $group_38 assign \L 1'0 assign \L { \opcode_in [21] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 \SH32 process $group_39 assign \SH32 5'00000 assign \SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 6 \sh process $group_40 assign \sh 6'000000 assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \MB32 process $group_41 assign \MB32 5'00000 assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \ME32 process $group_42 assign \ME32 5'00000 assign \ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 24 \LI process $group_43 assign \LI 24'000000000000000000000000 assign \LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } @@ -156041,7 +264701,7 @@ module \dec assign \LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 1 \AA process $group_45 assign \AA 1'0 @@ -156058,19 +264718,21 @@ module \dec assign \OE { \opcode_in [10] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \BD process $group_48 assign \BD 14'00000000000000 assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 3 \BF process $group_49 assign \BF 3'000 assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 10 \CR process $group_50 assign \CR 10'0000000000 @@ -156092,8 +264754,6 @@ module \dec assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 8 \FXM process $group_54 assign \FXM 8'00000000 assign \FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } @@ -156109,26 +264769,28 @@ module \dec assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 2 \BH process $group_57 assign \BH 2'00 assign \BH { \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 16 \D process $group_58 assign \D 16'0000000000000000 assign \D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 14 \DS process $group_59 assign \DS 14'00000000000000 assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \TO process $group_60 assign \TO 5'00000 @@ -156140,21 +264802,21 @@ module \dec assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \SH process $group_62 assign \SH 5'00000 assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \ME process $group_63 assign \ME 5'00000 assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \MB process $group_64 assign \MB 5'00000 @@ -156166,7 +264828,7 @@ module \dec assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_A process $group_66 assign \X_A 1'0 @@ -156183,735 +264845,735 @@ module \dec assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_BO process $group_69 assign \X_BO 5'00000 assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \X_CT process $group_70 assign \X_CT 4'0000 assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 7 \X_DCMX process $group_71 assign \X_DCMX 7'0000000 assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \X_DRM process $group_72 assign \X_DRM 3'000 assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_E process $group_73 assign \X_E 1'0 assign \X_E { \opcode_in [15] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \X_E_1 process $group_74 assign \X_E_1 4'0000 assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \X_EO process $group_75 assign \X_EO 2'00 assign \X_EO { \opcode_in [20] \opcode_in [19] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_EO_1 process $group_76 assign \X_EO_1 5'00000 assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_EX process $group_77 assign \X_EX 1'0 assign \X_EX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FC process $group_78 assign \X_FC 5'00000 assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRA process $group_79 assign \X_FRA 5'00000 assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRAp process $group_80 assign \X_FRAp 5'00000 assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRB process $group_81 assign \X_FRB 5'00000 assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRBp process $group_82 assign \X_FRBp 5'00000 assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRS process $group_83 assign \X_FRS 5'00000 assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRSp process $group_84 assign \X_FRSp 5'00000 assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRT process $group_85 assign \X_FRT 5'00000 assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_FRTp process $group_86 assign \X_FRTp 5'00000 assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \X_IH process $group_87 assign \X_IH 3'000 assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 8 \X_IMM8 process $group_88 assign \X_IMM8 8'00000000 assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 2 \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L2 process $group_89 - assign \X_L 2'00 - assign \X_L { \opcode_in [22] \opcode_in [21] } + assign \X_L2 2'00 + assign \X_L2 { \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 1 \X_L_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L process $group_90 - assign \X_L_1 1'0 - assign \X_L_1 { \opcode_in [21] } + assign \X_L 1'0 + assign \X_L { \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 1 \X_L_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \X_L1 process $group_91 - assign \X_L_2 1'0 - assign \X_L_2 { \opcode_in [16] } + assign \X_L1 1'0 + assign \X_L1 { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 2 \X_L_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \X_L3 process $group_92 - assign \X_L_3 2'00 - assign \X_L_3 { \opcode_in [17] \opcode_in [16] } + assign \X_L3 2'00 + assign \X_L3 { \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_MO process $group_93 assign \X_MO 5'00000 assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_NB process $group_94 assign \X_NB 5'00000 assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_PRS process $group_95 assign \X_PRS 1'0 assign \X_PRS { \opcode_in [17] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_R process $group_96 assign \X_R 1'0 assign \X_R { \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_R_1 process $group_97 assign \X_R_1 1'0 assign \X_R_1 { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_RA process $group_98 assign \X_RA 5'00000 assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_RB process $group_99 assign \X_RB 5'00000 assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_Rc process $group_100 assign \X_Rc 1'0 assign \X_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \X_RIC process $group_101 assign \X_RIC 2'00 assign \X_RIC { \opcode_in [19] \opcode_in [18] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \X_RM process $group_102 assign \X_RM 2'00 assign \X_RM { \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_RO process $group_103 assign \X_RO 1'0 assign \X_RO { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_RS process $group_104 assign \X_RS 5'00000 assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_RSp process $group_105 assign \X_RSp 5'00000 assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_RT process $group_106 assign \X_RT 5'00000 assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_RTp process $group_107 assign \X_RTp 5'00000 assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_S process $group_108 assign \X_S 5'00000 assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_SH process $group_109 assign \X_SH 5'00000 assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_SI process $group_110 assign \X_SI 5'00000 assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \X_SP process $group_111 assign \X_SP 2'00 assign \X_SP { \opcode_in [20] \opcode_in [19] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \X_SR process $group_112 assign \X_SR 4'0000 assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_SX process $group_113 assign \X_SX 1'0 assign \X_SX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \X_SX_S process $group_114 assign \X_SX_S 6'000000 assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_T process $group_115 assign \X_T 5'00000 assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \X_TBR process $group_116 assign \X_TBR 10'0000000000 assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_TH process $group_117 assign \X_TH 5'00000 assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_TO process $group_118 assign \X_TO 5'00000 assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_TX process $group_119 assign \X_TX 1'0 assign \X_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \X_TX_T process $group_120 assign \X_TX_T 6'000000 assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \X_U process $group_121 assign \X_U 4'0000 assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_UIM process $group_122 assign \X_UIM 5'00000 assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_VRS process $group_123 assign \X_VRS 5'00000 assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \X_VRT process $group_124 assign \X_VRT 5'00000 assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \X_W process $group_125 assign \X_W 1'0 assign \X_W { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \X_WC process $group_126 assign \X_WC 2'00 assign \X_WC { \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \X_XO process $group_127 assign \X_XO 10'0000000000 assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 8 \X_XO_1 process $group_128 assign \X_XO_1 8'00000000 assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \B_AA process $group_129 assign \B_AA 1'0 assign \B_AA { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 14 \B_BD process $group_130 assign \B_BD 14'00000000000000 assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \B_BI process $group_131 assign \B_BI 5'00000 assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \B_BO process $group_132 assign \B_BO 5'00000 assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \B_LK process $group_133 assign \B_LK 1'0 assign \B_LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \I_AA process $group_134 assign \I_AA 1'0 assign \I_AA { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 24 \I_LI process $group_135 assign \I_LI 24'000000000000000000000000 assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \I_LK process $group_136 assign \I_LK 1'0 assign \I_LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX3_AX process $group_137 assign \XX3_AX 1'0 assign \XX3_AX { \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX3_A process $group_138 assign \XX3_A 5'00000 assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX3_AX_A process $group_139 assign \XX3_AX_A 6'000000 assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \XX3_BF process $group_140 assign \XX3_BF 3'000 assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX3_BX process $group_141 assign \XX3_BX 1'0 assign \XX3_BX { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX3_B process $group_142 assign \XX3_B 5'00000 assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX3_BX_B process $group_143 assign \XX3_BX_B 6'000000 assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \XX3_DM process $group_144 assign \XX3_DM 2'00 assign \XX3_DM { \opcode_in [9] \opcode_in [8] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX3_Rc process $group_145 assign \XX3_Rc 1'0 assign \XX3_Rc { \opcode_in [10] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \XX3_SHW process $group_146 assign \XX3_SHW 2'00 assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX3_TX process $group_147 assign \XX3_TX 1'0 assign \XX3_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX3_T process $group_148 assign \XX3_T 5'00000 assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX3_TX_T process $group_149 assign \XX3_TX_T 6'000000 assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \XX3_XO process $group_150 assign \XX3_XO 4'0000 assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 8 \XX3_XO_1 process $group_151 assign \XX3_XO_1 8'00000000 assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 9 \XX3_XO_2 process $group_152 assign \XX3_XO_2 9'000000000 assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX4_AX process $group_153 assign \XX4_AX 1'0 assign \XX4_AX { \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX4_A process $group_154 assign \XX4_A 5'00000 assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX4_AX_A process $group_155 assign \XX4_AX_A 6'000000 assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX4_BX process $group_156 assign \XX4_BX 1'0 assign \XX4_BX { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX4_B process $group_157 assign \XX4_B 5'00000 assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX4_BX_B process $group_158 assign \XX4_BX_B 6'000000 assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX4_CX process $group_159 assign \XX4_CX 1'0 assign \XX4_CX { \opcode_in [3] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX4_C process $group_160 assign \XX4_C 5'00000 assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX4_CX_C process $group_161 assign \XX4_CX_C 6'000000 assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX4_TX process $group_162 assign \XX4_TX 1'0 assign \XX4_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX4_T process $group_163 assign \XX4_T 5'00000 assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX4_TX_T process $group_164 assign \XX4_TX_T 6'000000 assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \XX4_XO process $group_165 assign \XX4_XO 2'00 assign \XX4_XO { \opcode_in [5] \opcode_in [4] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XL_BA process $group_166 assign \XL_BA 5'00000 assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XL_BB process $group_167 assign \XL_BB 5'00000 assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \XL_BF process $group_168 assign \XL_BF 3'000 assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \XL_BFA process $group_169 assign \XL_BFA 3'000 assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \XL_BH process $group_170 assign \XL_BH 2'00 assign \XL_BH { \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XL_BI process $group_171 assign \XL_BI 5'00000 assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XL_BO process $group_172 assign \XL_BO 5'00000 assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XL_BO_1 process $group_173 assign \XL_BO_1 5'00000 @@ -156923,21 +265585,21 @@ module \dec assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XL_LK process $group_175 assign \XL_LK 1'0 assign \XL_LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 15 \XL_OC process $group_176 assign \XL_OC 15'000000000000000 assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XL_S process $group_177 assign \XL_S 1'0 @@ -156949,1264 +265611,2760 @@ module \dec assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_BC process $group_179 assign \A_BC 5'00000 assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_FRA process $group_180 assign \A_FRA 5'00000 assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_FRB process $group_181 assign \A_FRB 5'00000 assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_FRC process $group_182 assign \A_FRC 5'00000 assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_FRT process $group_183 assign \A_FRT 5'00000 assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_RA process $group_184 assign \A_RA 5'00000 assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_RB process $group_185 assign \A_RB 5'00000 assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \A_Rc process $group_186 assign \A_Rc 1'0 assign \A_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_RT process $group_187 assign \A_RT 5'00000 assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \A_XO process $group_188 assign \A_XO 5'00000 assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \D_BF process $group_189 assign \D_BF 3'000 assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 16 \D_D process $group_190 assign \D_D 16'0000000000000000 assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \D_FRS process $group_191 assign \D_FRS 5'00000 assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \D_FRT process $group_192 assign \D_FRT 5'00000 assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \D_L process $group_193 assign \D_L 1'0 assign \D_L { \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \D_RA process $group_194 assign \D_RA 5'00000 assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \D_RS process $group_195 assign \D_RS 5'00000 assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \D_RT process $group_196 assign \D_RT 5'00000 assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 16 \D_SI process $group_197 assign \D_SI 16'0000000000000000 assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \D_TO process $group_198 assign \D_TO 5'00000 assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 16 \D_UI process $group_199 assign \D_UI 16'0000000000000000 assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \XX2_BF process $group_200 assign \XX2_BF 3'000 assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX2_BX process $group_201 assign \XX2_BX 1'0 assign \XX2_BX { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX2_B process $group_202 assign \XX2_B 5'00000 assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX2_BX_B process $group_203 assign \XX2_BX_B 6'000000 assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX2_dc process $group_204 assign \XX2_dc 1'0 assign \XX2_dc { \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX2_dm process $group_205 assign \XX2_dm 1'0 assign \XX2_dm { \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX2_dx process $group_206 assign \XX2_dx 5'00000 assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 7 \XX2_dc_dm_dx process $group_207 assign \XX2_dc_dm_dx 7'0000000 assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 7 \XX2_DCMX process $group_208 assign \XX2_DCMX 7'0000000 assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX2_EO process $group_209 assign \XX2_EO 5'00000 assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX2_RT process $group_210 assign \XX2_RT 5'00000 assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XX2_TX process $group_211 assign \XX2_TX 1'0 assign \XX2_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XX2_T process $group_212 assign \XX2_T 5'00000 assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \XX2_TX_T process $group_213 assign \XX2_TX_T 6'000000 assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \XX2_UIM process $group_214 assign \XX2_UIM 4'0000 assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \XX2_UIM_1 process $group_215 assign \XX2_UIM_1 2'00 assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 7 \XX2_XO process $group_216 assign \XX2_XO 7'0000000 assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 9 \XX2_XO_1 process $group_217 assign \XX2_XO_1 9'000000000 assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \Z22_BF process $group_218 assign \Z22_BF 3'000 assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \Z22_DCM process $group_219 assign \Z22_DCM 6'000000 assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \Z22_DGM process $group_220 assign \Z22_DGM 6'000000 assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z22_FRA process $group_221 assign \Z22_FRA 5'00000 assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z22_FRAp process $group_222 assign \Z22_FRAp 5'00000 assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z22_FRT process $group_223 assign \Z22_FRT 5'00000 assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z22_FRTp process $group_224 assign \Z22_FRTp 5'00000 assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \Z22_Rc process $group_225 assign \Z22_Rc 1'0 assign \Z22_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \Z22_SH process $group_226 assign \Z22_SH 6'000000 assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 9 \Z22_XO process $group_227 assign \Z22_XO 9'000000000 assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \EVS_BFA process $group_228 assign \EVS_BFA 3'000 assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \XFX_BHRBE process $group_229 assign \XFX_BHRBE 10'0000000000 assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XFX_DUI process $group_230 assign \XFX_DUI 5'00000 assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \XFX_DUIS process $group_231 assign \XFX_DUIS 10'0000000000 assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 8 \XFX_FXM process $group_232 assign \XFX_FXM 8'00000000 assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XFX_RS process $group_233 assign \XFX_RS 5'00000 assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XFX_RT process $group_234 assign \XFX_RT 5'00000 assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \XFX_SPR process $group_235 assign \XFX_SPR 10'0000000000 assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \XFX_XO process $group_236 assign \XFX_XO 10'0000000000 assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \DX_d0 process $group_237 assign \DX_d0 10'0000000000 assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DX_d1 process $group_238 assign \DX_d1 5'00000 assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \DX_d2 process $group_239 assign \DX_d2 1'0 assign \DX_d2 { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 16 \DX_d0_d1_d2 process $group_240 assign \DX_d0_d1_d2 16'0000000000000000 assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DX_RT process $group_241 assign \DX_RT 5'00000 assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DX_XO process $group_242 assign \DX_XO 5'00000 assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 12 \DQ_DQ process $group_243 assign \DQ_DQ 12'000000000000 assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \DQ_PT process $group_244 assign \DQ_PT 4'0000 assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DQ_RA process $group_245 assign \DQ_RA 5'00000 assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DQ_RTp process $group_246 assign \DQ_RTp 5'00000 assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \DQ_SX process $group_247 assign \DQ_SX 1'0 assign \DQ_SX { \opcode_in [3] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DQ_S process $group_248 assign \DQ_S 5'00000 assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \DQ_SX_S process $group_249 assign \DQ_SX_S 6'000000 assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \DQ_TX process $group_250 assign \DQ_TX 1'0 assign \DQ_TX { \opcode_in [3] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DQ_T process $group_251 assign \DQ_T 5'00000 assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \DQ_TX_T process $group_252 assign \DQ_TX_T 6'000000 assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \DQ_XO process $group_253 assign \DQ_XO 3'000 assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 14 \DS_DS process $group_254 assign \DS_DS 14'00000000000000 assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_FRSp process $group_255 assign \DS_FRSp 5'00000 assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_FRTp process $group_256 assign \DS_FRTp 5'00000 assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_RA process $group_257 assign \DS_RA 5'00000 assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_RS process $group_258 assign \DS_RS 5'00000 assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_RSp process $group_259 assign \DS_RSp 5'00000 assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_RT process $group_260 assign \DS_RT 5'00000 assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_VRS process $group_261 assign \DS_VRS 5'00000 assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \DS_VRT process $group_262 assign \DS_VRT 5'00000 assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \DS_XO process $group_263 assign \DS_XO 2'00 assign \DS_XO { \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_EO process $group_264 assign \VX_EO 5'00000 assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \VX_PS process $group_265 assign \VX_PS 1'0 assign \VX_PS { \opcode_in [9] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_RA process $group_266 assign \VX_RA 5'00000 assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_RT process $group_267 assign \VX_RT 5'00000 assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_SIM process $group_268 assign \VX_SIM 5'00000 assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_UIM process $group_269 assign \VX_UIM 5'00000 assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \VX_UIM_1 process $group_270 assign \VX_UIM_1 4'0000 assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \VX_UIM_2 process $group_271 assign \VX_UIM_2 3'000 assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \VX_UIM_3 process $group_272 assign \VX_UIM_3 2'00 assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_VRA process $group_273 assign \VX_VRA 5'00000 assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_VRB process $group_274 assign \VX_VRB 5'00000 assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \VX_VRT process $group_275 assign \VX_VRT 5'00000 assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \VX_XO process $group_276 assign \VX_XO 10'0000000000 assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 11 \VX_XO_1 process $group_277 assign \VX_XO_1 11'00000000000 assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 8 \XFL_FLM process $group_278 assign \XFL_FLM 8'00000000 assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \XFL_FRB process $group_279 assign \XFL_FRB 5'00000 assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XFL_L process $group_280 assign \XFL_L 1'0 assign \XFL_L { \opcode_in [25] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XFL_Rc process $group_281 assign \XFL_Rc 1'0 assign \XFL_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \XFL_W process $group_282 assign \XFL_W 1'0 assign \XFL_W { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \XFL_XO process $group_283 assign \XFL_XO 10'0000000000 assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_FRA process $group_284 assign \Z23_FRA 5'00000 assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_FRAp process $group_285 assign \Z23_FRAp 5'00000 assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_FRB process $group_286 assign \Z23_FRB 5'00000 assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_FRBp process $group_287 assign \Z23_FRBp 5'00000 assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_FRT process $group_288 assign \Z23_FRT 5'00000 assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_FRTp process $group_289 assign \Z23_FRTp 5'00000 assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \Z23_R process $group_290 assign \Z23_R 1'0 assign \Z23_R { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \Z23_Rc process $group_291 assign \Z23_Rc 1'0 assign \Z23_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \Z23_RMC process $group_292 assign \Z23_RMC 2'00 assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \Z23_TE process $group_293 assign \Z23_TE 5'00000 assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 8 \Z23_XO process $group_294 assign \Z23_XO 8'00000000 assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \MDS_IB process $group_295 assign \MDS_IB 5'00000 assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \MDS_IS process $group_296 assign \MDS_IS 5'00000 assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \MDS_mb process $group_297 assign \MDS_mb 6'000000 assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \MDS_me process $group_298 assign \MDS_me 6'000000 assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \MDS_RA process $group_299 assign \MDS_RA 5'00000 assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \MDS_RB process $group_300 assign \MDS_RB 5'00000 assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \MDS_Rc process $group_301 assign \MDS_Rc 1'0 assign \MDS_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \MDS_RS process $group_302 assign \MDS_RS 5'00000 assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \MDS_XBI process $group_303 assign \MDS_XBI 4'0000 assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \MDS_XBI_1 process $group_304 assign \MDS_XBI_1 4'0000 assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 4 \MDS_XO process $group_305 assign \MDS_XO 4'0000 assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 7 \SC_LEV process $group_306 assign \SC_LEV 7'0000000 assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \SC_XO process $group_307 assign \SC_XO 1'0 assign \SC_XO { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 2 \SC_XO_1 process $group_308 assign \SC_XO_1 2'00 assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \M_MB process $group_309 assign \M_MB 5'00000 assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \M_ME process $group_310 assign \M_ME 5'00000 assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \M_RA process $group_311 assign \M_RA 5'00000 assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \M_RB process $group_312 assign \M_RB 5'00000 assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \M_Rc process $group_313 assign \M_Rc 1'0 assign \M_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \M_RS process $group_314 assign \M_RS 5'00000 assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \M_SH process $group_315 assign \M_SH 5'00000 assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \MD_mb process $group_316 assign \MD_mb 6'000000 assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 6 \MD_me process $group_317 assign \MD_me 6'000000 assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \MD_RA process $group_318 assign \MD_RA 5'00000 assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 1 \MD_Rc process $group_319 assign \MD_Rc 1'0 assign \MD_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \MD_RS - process $group_320 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \MD_RS + process $group_320 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \MD_sh + process $group_321 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 \MD_XO + process $group_322 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_OPCD + process $group_323 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \all_PO + process $group_324 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_OE + process $group_325 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RA + process $group_326 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RB + process $group_327 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XO_Rc + process $group_328 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XO_RT + process $group_329 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XO_XO + process $group_330 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RA + process $group_331 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \DQE_RT + process $group_332 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 2 \DQE_XO + process $group_333 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_RA + process $group_334 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \TX_UI + process $group_335 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \TX_XBI + process $group_336 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \TX_XO + process $group_337 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RA + process $group_338 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RB + process $group_339 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RC + process $group_340 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_RT + process $group_341 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 4 \VA_SHB + process $group_342 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRA + process $group_343 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRB + process $group_344 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRC + process $group_345 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VA_VRT + process $group_346 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \VA_XO + process $group_347 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RA + process $group_348 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \XS_Rc + process $group_349 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \XS_RS + process $group_350 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 6 \XS_sh + process $group_351 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 9 \XS_XO + process $group_352 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 1 \VC_Rc + process $group_353 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRA + process $group_354 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRB + process $group_355 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 \VC_VRT + process $group_356 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 \VC_XO + process $group_357 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" +module \dec_rc$203 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 3 \Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end + sync init + end + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" +module \dec_oe$204 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 1 input 4 \OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \OE + end + end + sync init + end + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" + case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" +module \ppick$206 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" +module \dec_cr_in$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 2 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$206 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + process $group_2 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \cr_fxm_ok 1'1 + end + sync init + end + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire width 1 \move_one + process $group_7 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \move_one \insn_in [20] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \move_one + connect \Y $3 + end + process $group_8 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \ppick_i \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 6 \MD_sh - process $group_321 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B \move_one + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 3 \MD_XO - process $group_322 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + process $group_9 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + case + assign \cr_fxm 8'11111111 + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 6 \all_OPCD - process $group_323 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" +module \ppick$208 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 6 \all_PO - process $group_324 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + process $group_0 + assign \ni 8'00000000 + assign \ni $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 1 \XO_OE - process $group_325 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [7] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \XO_RA - process $group_326 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \XO_RB - process $group_327 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 1 \XO_Rc - process $group_328 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } + process $group_2 + assign \t1 1'0 + assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \XO_RT - process $group_329 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 9 \XO_XO - process $group_330 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \DQE_RA - process $group_331 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_3 + assign \t2 1'0 + assign \t2 $7 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \DQE_RT - process $group_332 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 2 \DQE_XO - process $group_333 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \TX_RA - process $group_334 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_4 + assign \t3 1'0 + assign \t3 $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \TX_UI - process $group_335 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $16 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 4 \TX_XBI - process $group_336 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 6 \TX_XO - process $group_337 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + process $group_5 + assign \t4 1'0 + assign \t4 $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_RA - process $group_338 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $20 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_RB - process $group_339 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_RC - process $group_340 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + process $group_6 + assign \t5 1'0 + assign \t5 $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_RT - process $group_341 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 4 \VA_SHB - process $group_342 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_VRA - process $group_343 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_7 + assign \t6 1'0 + assign \t6 $23 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_VRB - process $group_344 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_VRC - process $group_345 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VA_VRT - process $group_346 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_8 + assign \t7 1'0 + assign \t7 $27 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 6 \VA_XO - process $group_347 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_9 + assign \o 8'00000000 + assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \XS_RA - process $group_348 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 1 \XS_Rc - process $group_349 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } + process $group_10 + assign \en_o 1'0 + assign \en_o $31 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \XS_RS - process $group_350 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" +module \dec_cr_out$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 0 \insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 input 2 \rc_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 5 \cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + cell \ppick$208 \ppick + connect \i \ppick_i + connect \en_o \ppick_en_o + connect \o \ppick_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 6 \XS_sh - process $group_351 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 9 \XS_XO - process $group_352 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + process $group_1 + assign \cr_fxm_ok 1'0 + assign \cr_fxm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \cr_fxm_ok 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 1 \VC_Rc - process $group_353 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VC_VRA - process $group_354 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire width 1 \move_one + process $group_3 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \move_one \insn_in [20] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VC_VRB - process $group_355 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 \VC_VRT - process $group_356 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_4 + assign \ppick_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + assign \ppick_i \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 10 \VC_XO - process $group_357 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $3 + end + process $group_5 + assign \cr_fxm 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch { \ppick_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + case 1'1 + assign \cr_fxm \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" + case + assign \cr_fxm 8'00000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + case + assign \cr_fxm \FXM + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" + case + assign \cr_fxm 8'11111111 + end + end sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" module \sprmap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" wire width 10 input 0 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -158319,342 +268477,1139 @@ module \sprmap attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \fast_o_ok process $group_0 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000000001 + assign \fast_o 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001000 + assign \fast_o 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001001 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000010110 + assign \fast_o 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011010 + assign \fast_o 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011011 + assign \fast_o 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0100001100 + assign \fast_o 3'111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0110111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0111010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'1100101111 + assign \fast_o 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1111111111 + end + sync init + end + process $group_1 + assign \fast_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000000001 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001000 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001001 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000010110 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011010 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011011 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0100001100 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0110111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0111010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'1100101111 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1111111111 + end + sync init + end + process $group_2 assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000000001 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000000011 assign \spr_o 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000001000 - assign \spr_o 10'0000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000001001 - assign \spr_o 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000001101 assign \spr_o 10'0000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000010001 assign \spr_o 10'0000000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000010010 assign \spr_o 10'0000000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000010011 assign \spr_o 10'0000000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000010110 - assign \spr_o 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000011010 - assign \spr_o 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000011011 - assign \spr_o 10'0000001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000011100 assign \spr_o 10'0000001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000011101 assign \spr_o 10'0000001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000110000 assign \spr_o 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000111101 assign \spr_o 10'0000001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000000 assign \spr_o 10'0000001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000001 assign \spr_o 10'0000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000010 assign \spr_o 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000011 assign \spr_o 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010001000 assign \spr_o 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010010000 assign \spr_o 10'0000010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011000 assign \spr_o 10'0000010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011001 assign \spr_o 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011101 assign \spr_o 10'0000010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011110 + assign \spr_o 10'0000011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011111 + assign \spr_o 10'0000011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110000 + assign \spr_o 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110100 + assign \spr_o 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111010 + assign \spr_o 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111011 + assign \spr_o 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111100 + assign \spr_o 10'0000011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111110 + assign \spr_o 10'0000011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000000 + assign \spr_o 10'0000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000011 + assign \spr_o 10'0000100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0100001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100001101 + assign \spr_o 10'0000100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010000 + assign \spr_o 10'0000100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010001 + assign \spr_o 10'0000100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010010 + assign \spr_o 10'0000100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010011 + assign \spr_o 10'0000100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011011 + assign \spr_o 10'0000101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011100 + assign \spr_o 10'0000101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011101 + assign \spr_o 10'0000101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011110 + assign \spr_o 10'0000101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011111 + assign \spr_o 10'0000101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110000 + assign \spr_o 10'0000101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110001 + assign \spr_o 10'0000101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110010 + assign \spr_o 10'0000101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110011 + assign \spr_o 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110100 + assign \spr_o 10'0000110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110101 + assign \spr_o 10'0000110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110110 + assign \spr_o 10'0000110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111001 + assign \spr_o 10'0000110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111010 + assign \spr_o 10'0000110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111011 + assign \spr_o 10'0000110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111110 + assign \spr_o 10'0000110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111111 + assign \spr_o 10'0000111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010000 + assign \spr_o 10'0000111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010001 + assign \spr_o 10'0000111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010010 + assign \spr_o 10'0000111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010011 + assign \spr_o 10'0000111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101011101 + assign \spr_o 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0110111110 + assign \spr_o 10'0000111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0111010000 + assign \spr_o 10'0000111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000000 + assign \spr_o 10'0001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000001 + assign \spr_o 10'0001000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000010 + assign \spr_o 10'0001000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000011 + assign \spr_o 10'0001000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000100 + assign \spr_o 10'0001000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000101 + assign \spr_o 10'0001000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000110 + assign \spr_o 10'0001000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000111 + assign \spr_o 10'0001000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001000 + assign \spr_o 10'0001001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001011 + assign \spr_o 10'0001001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001100 + assign \spr_o 10'0001001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001101 + assign \spr_o 10'0001001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001110 + assign \spr_o 10'0001001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010000 + assign \spr_o 10'0001001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010001 + assign \spr_o 10'0001001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010010 + assign \spr_o 10'0001001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010011 + assign \spr_o 10'0001010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010100 + assign \spr_o 10'0001010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010101 + assign \spr_o 10'0001010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010110 + assign \spr_o 10'0001010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010111 + assign \spr_o 10'0001010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011000 + assign \spr_o 10'0001010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011011 + assign \spr_o 10'0001010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011100 + assign \spr_o 10'0001010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011101 + assign \spr_o 10'0001011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011110 + assign \spr_o 10'0001011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100000 + assign \spr_o 10'0001011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100001 + assign \spr_o 10'0001011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100010 + assign \spr_o 10'0001011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100011 + assign \spr_o 10'0001011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100100 + assign \spr_o 10'0001011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100101 + assign \spr_o 10'0001011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100110 + assign \spr_o 10'0001100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101000 + assign \spr_o 10'0001100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101001 + assign \spr_o 10'0001100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101010 + assign \spr_o 10'0001100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101011 + assign \spr_o 10'0001100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110000 + assign \spr_o 10'0001100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110111 + assign \spr_o 10'0001100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010000 + assign \spr_o 10'0001101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010001 + assign \spr_o 10'0001101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010111 + assign \spr_o 10'0001101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000000 + assign \spr_o 10'0001101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000010 + assign \spr_o 10'0001101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1111111111 + assign \spr_o 10'0001101101 + end + sync init + end + process $group_3 + assign \spr_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000000011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000001101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000110000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000111101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010001000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011110 - assign \spr_o 10'0000011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011111 - assign \spr_o 10'0000011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010110000 - assign \spr_o 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010110100 - assign \spr_o 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111010 - assign \spr_o 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111011 - assign \spr_o 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111100 - assign \spr_o 10'0000011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111110 - assign \spr_o 10'0000011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100000000 - assign \spr_o 10'0000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100000011 - assign \spr_o 10'0000100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0100001100 - assign \spr_o 10'0000100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100001101 - assign \spr_o 10'0000100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010000 - assign \spr_o 10'0000100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010001 - assign \spr_o 10'0000100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010010 - assign \spr_o 10'0000100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010011 - assign \spr_o 10'0000100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011011 - assign \spr_o 10'0000101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011100 - assign \spr_o 10'0000101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011101 - assign \spr_o 10'0000101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011110 - assign \spr_o 10'0000101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011111 - assign \spr_o 10'0000101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110000 - assign \spr_o 10'0000101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110001 - assign \spr_o 10'0000101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110010 - assign \spr_o 10'0000101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110011 - assign \spr_o 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110100 - assign \spr_o 10'0000110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110101 - assign \spr_o 10'0000110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110110 - assign \spr_o 10'0000110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111001 - assign \spr_o 10'0000110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111010 - assign \spr_o 10'0000110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111011 - assign \spr_o 10'0000110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111110 - assign \spr_o 10'0000110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111111 - assign \spr_o 10'0000111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010000 - assign \spr_o 10'0000111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010001 - assign \spr_o 10'0000111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010010 - assign \spr_o 10'0000111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010011 - assign \spr_o 10'0000111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101011101 - assign \spr_o 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0110111110 - assign \spr_o 10'0000111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0111010000 - assign \spr_o 10'0000111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000000 - assign \spr_o 10'0001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000001 - assign \spr_o 10'0001000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000010 - assign \spr_o 10'0001000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000011 - assign \spr_o 10'0001000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000100 - assign \spr_o 10'0001000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000101 - assign \spr_o 10'0001000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000110 - assign \spr_o 10'0001000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000111 - assign \spr_o 10'0001000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001000 - assign \spr_o 10'0001001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001011 - assign \spr_o 10'0001001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001100 - assign \spr_o 10'0001001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001101 - assign \spr_o 10'0001001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001110 - assign \spr_o 10'0001001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010000 - assign \spr_o 10'0001001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010001 - assign \spr_o 10'0001001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010010 - assign \spr_o 10'0001001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010011 - assign \spr_o 10'0001010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010100 - assign \spr_o 10'0001010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010101 - assign \spr_o 10'0001010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010110 - assign \spr_o 10'0001010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010111 - assign \spr_o 10'0001010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011000 - assign \spr_o 10'0001010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011011 - assign \spr_o 10'0001010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011100 - assign \spr_o 10'0001010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011101 - assign \spr_o 10'0001011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011110 - assign \spr_o 10'0001011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100000 - assign \spr_o 10'0001011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100001 - assign \spr_o 10'0001011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100010 - assign \spr_o 10'0001011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100011 - assign \spr_o 10'0001011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100100 - assign \spr_o 10'0001011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100101 - assign \spr_o 10'0001011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100110 - assign \spr_o 10'0001100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101000 - assign \spr_o 10'0001100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101001 - assign \spr_o 10'0001100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101010 - assign \spr_o 10'0001100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101011 - assign \spr_o 10'0001100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'1100101111 - assign \spr_o 10'0001100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100110000 - assign \spr_o 10'0001100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100110111 - assign \spr_o 10'0001100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1101010000 - assign \spr_o 10'0001101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1101010001 - assign \spr_o 10'0001101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1101010111 - assign \spr_o 10'0001101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1110000000 - assign \spr_o 10'0001101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1110000010 - assign \spr_o 10'0001101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1111111111 - assign \spr_o 10'0001101101 + assign \spr_o_ok 1'1 end sync init end @@ -158662,14 +269617,6 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_a" module \dec_a - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77" - wire width 3 input 0 \sel_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -158743,14 +269690,20 @@ module \dec_a attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 0 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + wire width 3 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 output 2 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 3 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80" - wire width 1 output 4 \immz_out attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -158863,24 +269816,24 @@ module \dec_a attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 5 \spr_a + wire width 10 output 4 \spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 6 \spr_a_ok + wire width 1 output 5 \spr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 7 \fast_a + wire width 3 output 6 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 8 \fast_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 9 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 10 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 11 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 10 input 12 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 10 input 13 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + wire width 1 output 7 \fast_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 8 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 input 12 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -158993,22 +269946,31 @@ module \dec_a attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \sprmap_fast_o_ok cell \sprmap \sprmap connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 5 \ra process $group_0 assign \ra 5'00000 assign \ra \RA sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -159019,9 +269981,9 @@ module \dec_a connect \B 3'001 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" cell $eq $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -159032,9 +269994,9 @@ module \dec_a connect \B 3'010 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" cell $ne $6 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -159045,9 +270007,9 @@ module \dec_a connect \B 5'00000 connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" cell $and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -159058,9 +270020,9 @@ module \dec_a connect \B $5 connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" cell $or $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -159071,9 +270033,9 @@ module \dec_a connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" cell $eq $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -159086,23 +270048,23 @@ module \dec_a end process $group_1 assign \reg_a 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" case 1'1 assign \reg_a \ra end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" case 1'1 assign \reg_a \RS end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" cell $eq $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -159113,9 +270075,9 @@ module \dec_a connect \B 3'001 connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" cell $eq $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -159126,9 +270088,9 @@ module \dec_a connect \B 3'010 connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" cell $ne $18 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -159139,9 +270101,9 @@ module \dec_a connect \B 5'00000 connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -159152,9 +270114,9 @@ module \dec_a connect \B $17 connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" cell $or $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -159165,9 +270127,9 @@ module \dec_a connect \B $19 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" cell $eq $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -159180,353 +270142,136 @@ module \dec_a end process $group_2 assign \reg_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" case 1'1 assign \reg_a_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" switch { $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" case 1'1 assign \reg_a_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + cell $not $26 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 + connect \A \BO [2] connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $not $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \reg_a - connect \B 5'00000 + connect \A \XL_XO [5] connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $25 + connect \A \XL_XO [9] connect \B $27 connect \Y $29 end process $group_3 - assign \immz_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - case 1'1 - assign \immz_out 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $and $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B $33 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" - wire width 10 \spr - process $group_4 assign \fast_a 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - case 1'1 - assign \fast_a 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - switch { $35 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - case 1'1 - assign \fast_a 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - assign \fast_a 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - assign \fast_a 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - assign \fast_a 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - assign \fast_a 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - assign \fast_a 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B $39 - connect \Y $41 - end - process $group_5 assign \fast_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" case 1'1 + assign \fast_a 3'000 assign \fast_a_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" case 1'1 + assign \fast_a 3'000 assign \fast_a_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - end + assign { \fast_a_ok \fast_a } { \sprmap_fast_o_ok \sprmap_fast_o } end sync init end - process $group_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + wire width 10 \spr + process $group_5 assign \spr 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 assign \spr { \SPR [4:0] \SPR [9:5] } end sync init end - process $group_7 + process $group_6 assign \sprmap_spr_i 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - assign \sprmap_spr_i \spr - end + assign \sprmap_spr_i \spr end sync init end - process $group_8 + process $group_7 assign \spr_a 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - assign \spr_a \sprmap_spr_o - end - end - sync init - end - process $group_9 assign \spr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" attribute \nmigen.decoding "OP_MFSPR/46" case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - assign \spr_a_ok 1'1 - end + assign { \spr_a_ok \spr_a } { \sprmap_spr_o_ok \sprmap_spr_o } end sync init end @@ -159534,23 +270279,6 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_b" module \dec_b - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" - wire width 4 input 0 \sel_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -159624,643 +270352,73 @@ module \dec_b attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 0 \internal_op + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 output 2 \reg_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 3 \reg_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 4 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \fast_b + wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 7 \fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 8 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 9 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 16 input 10 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 16 input 11 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 12 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 6 input 13 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 24 input 14 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 14 input 15 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 14 input 16 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 10 input 17 \XL_XO + wire width 1 output 5 \fast_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 6 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 5 input 7 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" + wire width 10 input 8 \XL_XO process $group_0 assign \reg_b 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:186" attribute \nmigen.decoding "RB/1" case 4'0001 assign \reg_b \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" attribute \nmigen.decoding "RS/13" case 4'1101 assign \reg_b \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 end sync init end process $group_1 assign \reg_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:186" attribute \nmigen.decoding "RB/1" case 4'0001 assign \reg_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" attribute \nmigen.decoding "RS/13" case 4'1101 assign \reg_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" - wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \SH32 - connect \Y $11 - end - process $group_2 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_3 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_4 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_5 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_6 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" - wire width 27 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" - wire width 27 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" - cell $sshl $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LI - connect \B 2'10 - connect \Y $17 - end - connect $16 $17 - process $group_7 - assign \li 26'00000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \li $16 [25:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" - wire width 17 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" - wire width 17 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" - cell $sshl $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BD - connect \B 2'10 - connect \Y $20 - end - connect $19 $20 - process $group_8 - assign \bd 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \bd $19 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 17 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 17 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - cell $sshl $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DS - connect \B 2'10 - connect \Y $23 - end - connect $22 $23 - process $group_9 - assign \ds 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \ds $22 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - cell $eq $26 + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -160268,40 +270426,40 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $25 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - cell $not $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $27 + connect \Y $3 end - process $group_10 + process $group_2 assign \fast_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - switch { \XL_XO [5] $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" case 2'-1 assign \fast_b 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" case 2'1- assign \fast_b 3'010 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - cell $eq $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $6 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -160309,30 +270467,30 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $29 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - cell $not $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $31 + connect \Y $7 end - process $group_11 + process $group_3 assign \fast_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - switch { \XL_XO [5] $31 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" case 2'-1 assign \fast_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" case 2'1- assign \fast_b_ok 1'1 end @@ -160347,25 +270505,25 @@ module \dec_c attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 2 input 0 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 output 1 \reg_c attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 2 \reg_c_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 input 3 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 input 4 \RB process $group_0 assign \reg_c 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" attribute \nmigen.decoding "RB/2" case 2'10 assign \reg_c \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293" attribute \nmigen.decoding "RS/1" case 2'01 assign \reg_c \RS @@ -160374,13 +270532,13 @@ module \dec_c end process $group_1 assign \reg_c_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" attribute \nmigen.decoding "RB/2" case 2'10 assign \reg_c_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293" attribute \nmigen.decoding "RS/1" case 2'01 assign \reg_c_ok 1'1 @@ -160390,8 +270548,8 @@ module \dec_c end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" -module \sprmap$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" +module \sprmap$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" wire width 10 input 0 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -160504,356 +270662,1146 @@ module \sprmap$134 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \fast_o_ok process $group_0 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000000001 + assign \fast_o 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001000 + assign \fast_o 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001001 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000010110 + assign \fast_o 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011010 + assign \fast_o 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011011 + assign \fast_o 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0100001100 + assign \fast_o 3'111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0110111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0111010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'1100101111 + assign \fast_o 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1111111111 + end + sync init + end + process $group_1 + assign \fast_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000000001 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001000 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001001 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000010110 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011010 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011011 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0100001100 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0110111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0111010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'1100101111 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1111111111 + end + sync init + end + process $group_2 assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000000001 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000000011 assign \spr_o 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000001000 - assign \spr_o 10'0000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000001001 - assign \spr_o 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000001101 assign \spr_o 10'0000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000010001 assign \spr_o 10'0000000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000010010 assign \spr_o 10'0000000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000010011 assign \spr_o 10'0000000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000010110 - assign \spr_o 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000011010 - assign \spr_o 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0000011011 - assign \spr_o 10'0000001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000011100 assign \spr_o 10'0000001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000011101 assign \spr_o 10'0000001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000110000 assign \spr_o 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0000111101 assign \spr_o 10'0000001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000000 assign \spr_o 10'0000001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000001 assign \spr_o 10'0000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000010 assign \spr_o 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010000011 assign \spr_o 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010001000 assign \spr_o 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010010000 assign \spr_o 10'0000010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011000 assign \spr_o 10'0000010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011001 assign \spr_o 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011101 assign \spr_o 10'0000010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011110 assign \spr_o 10'0000011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010011111 assign \spr_o 10'0000011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010110000 assign \spr_o 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010110100 assign \spr_o 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111010 assign \spr_o 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111011 assign \spr_o 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111100 assign \spr_o 10'0000011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0010111110 assign \spr_o 10'0000011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100000000 assign \spr_o 10'0000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100000011 assign \spr_o 10'0000100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'0100001100 - assign \spr_o 10'0000100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100001101 assign \spr_o 10'0000100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010000 assign \spr_o 10'0000100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010001 assign \spr_o 10'0000100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010010 assign \spr_o 10'0000100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100010011 assign \spr_o 10'0000100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011011 assign \spr_o 10'0000101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011100 assign \spr_o 10'0000101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011101 assign \spr_o 10'0000101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011110 assign \spr_o 10'0000101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100011111 assign \spr_o 10'0000101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110000 assign \spr_o 10'0000101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110001 assign \spr_o 10'0000101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110010 assign \spr_o 10'0000101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110011 assign \spr_o 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110100 assign \spr_o 10'0000110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110101 assign \spr_o 10'0000110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100110110 assign \spr_o 10'0000110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111001 assign \spr_o 10'0000110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111010 assign \spr_o 10'0000110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111011 assign \spr_o 10'0000110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111110 assign \spr_o 10'0000110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0100111111 assign \spr_o 10'0000111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010000 assign \spr_o 10'0000111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010001 assign \spr_o 10'0000111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010010 assign \spr_o 10'0000111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101010011 assign \spr_o 10'0000111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0101011101 assign \spr_o 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0110111110 assign \spr_o 10'0000111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'0111010000 assign \spr_o 10'0000111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000000 assign \spr_o 10'0001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000001 assign \spr_o 10'0001000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000010 assign \spr_o 10'0001000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000011 assign \spr_o 10'0001000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000100 assign \spr_o 10'0001000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000101 assign \spr_o 10'0001000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000110 assign \spr_o 10'0001000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100000111 assign \spr_o 10'0001000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001000 assign \spr_o 10'0001001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001011 assign \spr_o 10'0001001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001100 assign \spr_o 10'0001001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001101 assign \spr_o 10'0001001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100001110 assign \spr_o 10'0001001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010000 assign \spr_o 10'0001001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010001 assign \spr_o 10'0001001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010010 assign \spr_o 10'0001001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010011 assign \spr_o 10'0001010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010100 assign \spr_o 10'0001010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010101 assign \spr_o 10'0001010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010110 assign \spr_o 10'0001010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100010111 assign \spr_o 10'0001010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011000 assign \spr_o 10'0001010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011011 assign \spr_o 10'0001010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011100 assign \spr_o 10'0001010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011101 assign \spr_o 10'0001011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100011110 assign \spr_o 10'0001011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100000 assign \spr_o 10'0001011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100001 assign \spr_o 10'0001011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100010 assign \spr_o 10'0001011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100011 assign \spr_o 10'0001011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100100 assign \spr_o 10'0001011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100101 assign \spr_o 10'0001011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100100110 assign \spr_o 10'0001100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101000 assign \spr_o 10'0001100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101001 assign \spr_o 10'0001100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101010 assign \spr_o 10'0001100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100101011 assign \spr_o 10'0001100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" case 10'1100101111 - assign \spr_o 10'0001100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100110000 assign \spr_o 10'0001100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1100110111 assign \spr_o 10'0001100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1101010000 assign \spr_o 10'0001101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1101010001 assign \spr_o 10'0001101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1101010111 assign \spr_o 10'0001101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1110000000 assign \spr_o 10'0001101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1110000010 assign \spr_o 10'0001101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" case 10'1111111111 assign \spr_o 10'0001101101 end sync init end + process $group_3 + assign \spr_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000000011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000001101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000010011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000110000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0000111101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010000011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010001000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010011111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010110100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0010111110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100000011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'0100001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100001101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100010011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100011111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100110110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0100111111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101010011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0101011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0110111110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'0111010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100000111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100001110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100010111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100011110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100100 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100101 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100100110 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100101011 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1100110111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010001 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1101010111 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000000 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1110000010 + assign \spr_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" + case 10'1111111111 + assign \spr_o_ok 1'1 + end + sync init + end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" module \dec_o - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - wire width 2 input 0 \sel_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -160927,8 +271875,15 @@ module \dec_o attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 0 \internal_op + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 output 2 \reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -161052,15 +272007,15 @@ module \dec_o wire width 3 output 6 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 7 \fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 input 8 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -161173,25 +272128,34 @@ module \dec_o attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 10 \sprmap_spr_o - cell \sprmap$134 \sprmap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \sprmap_fast_o_ok + cell \sprmap$209 \sprmap connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok end process $group_0 assign \reg_o 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" attribute \nmigen.decoding "RT/1" case 2'01 assign \reg_o \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" attribute \nmigen.decoding "RA/2" case 2'10 assign \reg_o \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" attribute \nmigen.decoding "SPR/3" case 2'11 end @@ -161199,44 +272163,44 @@ module \dec_o end process $group_1 assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" attribute \nmigen.decoding "RT/1" case 2'01 assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" attribute \nmigen.decoding "RA/2" case 2'10 assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" attribute \nmigen.decoding "SPR/3" case 2'11 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" wire width 10 \spr process $group_2 assign \spr 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" attribute \nmigen.decoding "RT/1" case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" attribute \nmigen.decoding "RA/2" case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" attribute \nmigen.decoding "SPR/3" case 2'11 assign \spr { \SPR [4:0] \SPR [9:5] } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -161247,78 +272211,67 @@ module \dec_o connect \B 7'0110001 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + process $group_3 + assign \sprmap_spr_i 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case 1'1 + assign \sprmap_spr_i \spr + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \BO [2] + connect \A \internal_op + connect \B 7'0110001 connect \Y $3 end - process $group_3 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + process $group_4 + assign \spr_o 10'0000000000 + assign \spr_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" attribute \nmigen.decoding "RT/1" case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" attribute \nmigen.decoding "RA/2" case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" attribute \nmigen.decoding "SPR/3" case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - assign \fast_o 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - assign \fast_o 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - assign \fast_o 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - assign \fast_o 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - end - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" - attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8" - case 7'0000111, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" case 1'1 - assign \fast_o 3'000 + assign { \spr_o_ok \spr_o } { \sprmap_spr_o_ok \sprmap_spr_o } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o 3'011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" cell $eq $6 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -161339,45 +272292,25 @@ module \dec_o connect \A \BO [2] connect \Y $7 end - process $group_4 + process $group_6 + assign \fast_o 3'000 assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" attribute \nmigen.decoding "RT/1" case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" attribute \nmigen.decoding "RA/2" case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" attribute \nmigen.decoding "SPR/3" case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case 1'1 + assign { \fast_o_ok \fast_o } { \sprmap_fast_o_ok \sprmap_fast_o } end end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" @@ -161389,177 +272322,21 @@ module \dec_o switch { $7 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" case 1'1 + assign \fast_o 3'000 assign \fast_o_ok 1'1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + assign \fast_o 3'011 assign \fast_o_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $9 - end - process $group_5 - assign \sprmap_spr_i 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - assign \sprmap_spr_i \spr - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $11 - end - process $group_6 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - assign \spr_o \sprmap_spr_o - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $13 - end - process $group_7 - assign \spr_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - assign \spr_o_ok 1'1 - end - end - end - sync init - end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" module \dec_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire width 1 input 0 \lk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -161633,8 +272410,10 @@ module \dec_o2 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 7 input 0 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire width 1 input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 output 2 \reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -161648,9 +272427,9 @@ module \dec_o2 attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 input 7 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" wire width 1 $1 @@ -161665,9 +272444,9 @@ module \dec_o2 connect \B 2'01 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" cell $pos $4 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -161729,555 +272508,17 @@ module \dec_o2 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" -module \dec_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 1 input 3 \Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" -module \dec_oe - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 1 input 4 \OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52" - case 7'0110011, 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52" - case 7'0110011, 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" -module \dec_cr_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 1 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 5 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 6 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" - wire width 1 output 7 \whole_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 8 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 9 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 10 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 11 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 input 12 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 3 input 13 \X_BFA - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_2 - assign \whole_reg 1'0 - assign \whole_reg 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \whole_reg 1'1 - end - sync init - end - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" -module \dec_cr_out - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" - wire width 1 input 1 \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 2 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531" - wire width 1 output 4 \whole_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" - wire width 5 input 6 \XL_BT - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - process $group_1 - assign \whole_reg 1'0 - assign \whole_reg 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \whole_reg 1'1 - end - sync init - end - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end -end -attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2" module \dec2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" wire width 1 input 0 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:337" - wire width 32 input 1 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 2 \dec2_pc + wire width 64 input 1 \cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 3 \dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 64 input 2 \cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 input 3 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" wire width 8 output 4 \asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 output 5 \rego @@ -162529,9 +272770,9 @@ module \dec2 wire width 10 output 17 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 18 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 output 19 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 output 19 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" wire width 1 output 20 \xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 3 output 21 \fast1 @@ -162565,11 +272806,11 @@ module \dec2 wire width 3 output 35 \cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 output 36 \cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" wire width 64 output 37 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 output 38 \cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" wire width 32 output 39 \insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -162644,7 +272885,7 @@ module \dec2 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 7 output 40 \insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -162658,112 +272899,49 @@ module \dec2 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 11 output 41 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 output 42 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 1 output 44 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \rc + wire width 1 output 43 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 46 \rc_ok + wire width 1 output 44 \rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \oe + wire width 1 output 45 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 48 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 output 49 \invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 output 50 \zero_a + wire width 1 output 46 \oe_ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 output 51 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 output 52 \output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 output 53 \input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 output 54 \output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 output 55 \invert_out + wire width 2 output 47 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 output 56 \is_32bit + wire width 7 output 48 \traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 output 57 \is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 output 58 \data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 output 59 \byte_reverse + wire width 13 output 49 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 50 \cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 51 \cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 52 \cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 53 \cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 output 60 \sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 output 61 \ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 output 62 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 13 output 63 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 output 64 \read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 output 65 \write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 output 66 \write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 1 output 54 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire width 1 input 55 \cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 input 56 \cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" wire width 32 \dec_opcode_in - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 3 \dec_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 4 \dec_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_rc_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -162773,7 +272951,7 @@ module \dec2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -162781,7 +272959,7 @@ module \dec2 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 3 \dec_cr_out attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -162856,7 +273034,7 @@ module \dec2 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 7 \dec_internal_op attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -162870,138 +273048,131 @@ module \dec2 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 11 \dec_function_unit - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 4 \dec_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 \dec_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 \dec_inv_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 \dec_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 \dec_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" wire width 1 \dec_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 1 \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 \dec_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" - wire width 1 \dec_sgn_ext + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 3 \dec_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" + wire width 2 \dec_out_sel attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" wire width 2 \dec_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 16 \dec_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 16 \dec_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 5 \dec_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 6 \dec_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 24 \dec_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 1 \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 1 \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 14 \dec_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" + wire width 8 \dec_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" - wire width 14 \dec_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" wire width 10 \dec_XL_XO - cell \dec \dec + cell \dec$202 \dec connect \bigendian \bigendian connect \raw_opcode_in \raw_opcode_in connect \opcode_in \dec_opcode_in - connect \in1_sel \dec_in1_sel - connect \in2_sel \dec_in2_sel - connect \in3_sel \dec_in3_sel - connect \out_sel \dec_out_sel connect \rc_sel \dec_rc_sel connect \cr_in \dec_cr_in connect \cr_out \dec_cr_out connect \internal_op \dec_internal_op connect \function_unit \dec_function_unit - connect \ldst_len \dec_ldst_len - connect \inv_a \dec_inv_a - connect \inv_out \dec_inv_out connect \cry_in \dec_cry_in - connect \cry_out \dec_cry_out connect \is_32b \dec_is_32b - connect \sgn \dec_sgn connect \lk \dec_lk connect \LK \dec_LK - connect \br \dec_br - connect \sgn_ext \dec_sgn_ext + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \out_sel \dec_out_sel connect \upd \dec_upd connect \RS \dec_RS connect \RT \dec_RT connect \RA \dec_RA connect \RB \dec_RB - connect \SI \dec_SI - connect \UI \dec_UI - connect \SH32 \dec_SH32 - connect \sh \dec_sh - connect \LI \dec_LI connect \Rc \dec_Rc connect \OE \dec_OE - connect \BD \dec_BD connect \BB \dec_BB connect \BA \dec_BA connect \BT \dec_BT + connect \FXM \dec_FXM connect \BO \dec_BO connect \BI \dec_BI - connect \DS \dec_DS connect \BC \dec_BC connect \SPR \dec_SPR connect \X_BF \dec_X_BF @@ -163009,20 +273180,132 @@ module \dec2 connect \XL_BT \dec_XL_BT connect \XL_XO \dec_XL_XO end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc$203 \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \Rc \dec_Rc + end + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe$204 \dec_oe + connect \sel_in \dec_oe_sel_in + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \OE \dec_OE + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_in_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_bitfield_o_ok + cell \dec_cr_in$205 \dec_cr_in$3 + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + connect \internal_op \dec_internal_op + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \BB \dec_BB + connect \BA \dec_BA + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \BI \dec_BI + connect \BC \dec_BC + connect \X_BFA \dec_X_BFA + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_out_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + cell \dec_cr_out$207 \dec_cr_out$4 + connect \insn_in \dec_cr_out_insn_in + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \internal_op \dec_internal_op + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \FXM \dec_FXM + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT + end attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" wire width 3 \dec_a_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 \dec_a_reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec_a_reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80" - wire width 1 \dec_a_immz_out attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -163143,11 +273426,10 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec_a_fast_a_ok cell \dec_a \dec_a - connect \sel_in \dec_a_sel_in connect \internal_op \dec_internal_op + connect \sel_in \dec_a_sel_in connect \reg_a \dec_a_reg_a connect \reg_a_ok \dec_a_reg_a_ok - connect \immz_out \dec_a_immz_out connect \spr_a \dec_a_spr_a connect \spr_a_ok \dec_a_spr_a_ok connect \fast_a \dec_a_fast_a @@ -163173,45 +273455,32 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 \dec_b_reg_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec_b_reg_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_b_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_b_imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 3 \dec_b_fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec_b_fast_b_ok cell \dec_b \dec_b - connect \sel_in \dec_b_sel_in connect \internal_op \dec_internal_op + connect \sel_in \dec_b_sel_in connect \reg_b \dec_b_reg_b connect \reg_b_ok \dec_b_reg_b_ok - connect \imm_b \dec_b_imm_b - connect \imm_b_ok \dec_b_imm_b_ok connect \fast_b \dec_b_fast_b connect \fast_b_ok \dec_b_fast_b_ok connect \RS \dec_RS connect \RB \dec_RB - connect \SI \dec_SI - connect \UI \dec_UI - connect \SH32 \dec_SH32 - connect \sh \dec_sh - connect \LI \dec_LI - connect \BD \dec_BD - connect \DS \dec_DS connect \XL_XO \dec_XL_XO end attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 2 \dec_c_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 \dec_c_reg_c @@ -163229,7 +273498,7 @@ module \dec2 attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" wire width 2 \dec_o_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 \dec_o_reg_o @@ -163355,8 +273624,8 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec_o_fast_o_ok cell \dec_o \dec_o - connect \sel_in \dec_o_sel_in connect \internal_op \dec_internal_op + connect \sel_in \dec_o_sel_in connect \reg_o \dec_o_reg_o connect \reg_o_ok \dec_o_reg_o_ok connect \spr_o \dec_o_spr_o @@ -163379,8 +273648,8 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec_o2_fast_o_ok cell \dec_o2 \dec_o2 - connect \lk \dec_o2_lk connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk connect \reg_o \dec_o2_reg_o connect \reg_o_ok \dec_o2_reg_o_ok connect \fast_o \dec_o2_fast_o @@ -163388,250 +273657,75 @@ module \dec2 connect \upd \dec_upd connect \RA \dec_RA end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc_ok - cell \dec_rc \dec_rc - connect \sel_in \dec_rc_sel_in - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \Rc \dec_Rc - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe \dec_oe - connect \sel_in \dec_oe_sel_in - connect \internal_op \dec_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \OE \dec_OE - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" - wire width 1 \dec_cr_in_whole_reg - cell \dec_cr_in \dec_cr_in$3 - connect \sel_in \dec_cr_in_sel_in - connect \cr_bitfield \dec_cr_in_cr_bitfield - connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok - connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b - connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok - connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o - connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok - connect \whole_reg \dec_cr_in_whole_reg - connect \BB \dec_BB - connect \BA \dec_BA - connect \BT \dec_BT - connect \BI \dec_BI - connect \BC \dec_BC - connect \X_BFA \dec_X_BFA - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" - wire width 1 \dec_cr_out_rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531" - wire width 1 \dec_cr_out_whole_reg - cell \dec_cr_out \dec_cr_out$4 - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \cr_bitfield \dec_cr_out_cr_bitfield - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \whole_reg \dec_cr_out_whole_reg - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" - wire width 32 \insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \tmp_tmp_insn process $group_0 - assign \insn$5 32'00000000000000000000000000000000 - assign \insn$5 \dec_opcode_in + assign \tmp_tmp_insn 32'00000000000000000000000000000000 + assign \tmp_tmp_insn \dec_opcode_in + assign \tmp_tmp_insn \dec_opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" wire width 32 \insn_in process $group_1 assign \insn_in 32'00000000000000000000000000000000 assign \insn_in \dec_opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - wire width 32 \insn_in$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$5 process $group_2 - assign \insn_in$6 32'00000000000000000000000000000000 - assign \insn_in$6 \dec_opcode_in + assign \insn_in$5 32'00000000000000000000000000000000 + assign \insn_in$5 \dec_opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 32 \insn_in$7 process $group_3 - assign \insn_in$7 32'00000000000000000000000000000000 - assign \insn_in$7 \dec_opcode_in + assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_in_insn_in \dec_opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:287" - wire width 32 \insn_in$8 process $group_4 - assign \insn_in$8 32'00000000000000000000000000000000 - assign \insn_in$8 \dec_opcode_in + assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 + assign \dec_cr_out_insn_in \dec_opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - wire width 32 \insn_in$9 process $group_5 - assign \insn_in$9 32'00000000000000000000000000000000 - assign \insn_in$9 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in$10 - process $group_6 - assign \insn_in$10 32'00000000000000000000000000000000 - assign \insn_in$10 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$11 - process $group_7 - assign \insn_in$11 32'00000000000000000000000000000000 - assign \insn_in$11 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" - wire width 32 \insn_in$12 - process $group_8 - assign \insn_in$12 32'00000000000000000000000000000000 - assign \insn_in$12 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - wire width 32 \insn_in$13 - process $group_9 - assign \insn_in$13 32'00000000000000000000000000000000 - assign \insn_in$13 \dec_opcode_in - sync init - end - process $group_10 - assign \dec_a_sel_in 3'000 - assign \dec_a_sel_in \dec_in1_sel - sync init - end - process $group_11 - assign \dec_b_sel_in 4'0000 - assign \dec_b_sel_in \dec_in2_sel - sync init - end - process $group_12 - assign \dec_c_sel_in 2'00 - assign \dec_c_sel_in \dec_in3_sel - sync init - end - process $group_13 - assign \dec_o_sel_in 2'00 - assign \dec_o_sel_in \dec_out_sel - sync init - end - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" - wire width 2 \sel_in - process $group_14 - assign \sel_in 2'00 - assign \sel_in \dec_out_sel - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 1 \lk$14 - process $group_15 - assign \dec_o2_lk 1'0 - assign \dec_o2_lk \lk$14 - sync init - end - process $group_16 assign \dec_rc_sel_in 2'00 assign \dec_rc_sel_in \dec_rc_sel sync init end - process $group_17 + process $group_6 assign \dec_oe_sel_in 2'00 assign \dec_oe_sel_in \dec_rc_sel sync init end - process $group_18 + process $group_7 assign \dec_cr_in_sel_in 3'000 assign \dec_cr_in_sel_in \dec_cr_in sync init end - process $group_19 + process $group_8 assign \dec_cr_out_sel_in 3'000 assign \dec_cr_out_sel_in \dec_cr_out sync init end - process $group_20 + process $group_9 assign \dec_cr_out_rc_in 1'0 assign \dec_cr_out_rc_in \dec_rc_rc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 64 \msr$15 - process $group_21 - assign \msr$15 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr$15 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \tmp_tmp_msr + process $group_10 + assign \tmp_tmp_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \tmp_tmp_msr \cur_msr sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" - wire width 64 \cia$16 - process $group_22 - assign \cia$16 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \cia$16 \dec2_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_cia + process $group_11 + assign \tmp_tmp_cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \tmp_tmp_cia \cur_pc sync init end attribute \enum_base_type "MicrOp" @@ -163707,11 +273801,11 @@ module \dec2 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" - wire width 7 \insn_type$17 - process $group_23 - assign \insn_type$17 7'0000000 - assign \insn_type$17 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \tmp_tmp_insn_type + process $group_12 + assign \tmp_tmp_insn_type 7'0000000 + assign \tmp_tmp_insn_type \dec_internal_op sync init end attribute \enum_base_type "Function" @@ -163726,98 +273820,203 @@ module \dec2 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" - wire width 11 \fn_unit$18 - process $group_24 - assign \fn_unit$18 11'00000000000 - assign \fn_unit$18 \dec_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 11 \tmp_tmp_fn_unit + process $group_13 + assign \tmp_tmp_fn_unit 11'00000000000 + assign \tmp_tmp_fn_unit \dec_function_unit sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \reg1$19 + wire width 1 \tmp_tmp_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \reg1_ok$20 - process $group_25 - assign \reg1$19 5'00000 - assign \reg1_ok$20 1'0 - assign { \reg1_ok$20 \reg1$19 } { \dec_a_reg_a_ok \dec_a_reg_a } + wire width 1 \tmp_tmp_rc_ok + process $group_14 + assign \tmp_tmp_rc 1'0 + assign \tmp_tmp_rc_ok 1'0 + assign { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \reg2$21 + wire width 1 \tmp_tmp_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \reg2_ok$22 - process $group_27 - assign \reg2$21 5'00000 - assign \reg2_ok$22 1'0 - assign { \reg2_ok$22 \reg2$21 } { \dec_b_reg_b_ok \dec_b_reg_b } + wire width 1 \tmp_tmp_oe_ok + process $group_16 + assign \tmp_tmp_oe 1'0 + assign \tmp_tmp_oe_ok 1'0 + assign { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \reg3$23 + wire width 8 \tmp_tmp_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \reg3_ok$24 - process $group_29 - assign \reg3$23 5'00000 - assign \reg3_ok$24 1'0 - assign { \reg3_ok$24 \reg3$23 } { \dec_c_reg_c_ok \dec_c_reg_c } + wire width 1 \tmp_tmp_cr_rd_ok + process $group_18 + assign \tmp_tmp_cr_rd 8'00000000 + assign \tmp_tmp_cr_rd_ok 1'0 + assign { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \rego$25 + wire width 8 \tmp_tmp_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rego_ok$26 + wire width 1 \tmp_tmp_cr_wr_ok + process $group_20 + assign \tmp_tmp_cr_wr 8'00000000 + assign \tmp_tmp_cr_wr_ok 1'0 + assign { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + sync init + end + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \tmp_tmp_input_carry + process $group_22 + assign \tmp_tmp_input_carry 2'00 + assign \tmp_tmp_input_carry \dec_cry_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 \tmp_tmp_is_32bit + process $group_23 + assign \tmp_tmp_is_32bit 1'0 + assign \tmp_tmp_is_32bit \dec_is_32b + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \tmp_tmp_lk + process $group_24 + assign \tmp_tmp_lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" + switch { \dec_lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" + case 1'1 + assign \tmp_tmp_lk \dec_LK + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" + wire width 32 \insn_in$6 + process $group_25 + assign \insn_in$6 32'00000000000000000000000000000000 + assign \insn_in$6 \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + wire width 32 \insn_in$7 + process $group_26 + assign \insn_in$7 32'00000000000000000000000000000000 + assign \insn_in$7 \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" + wire width 32 \insn_in$8 + process $group_27 + assign \insn_in$8 32'00000000000000000000000000000000 + assign \insn_in$8 \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + wire width 32 \insn_in$9 + process $group_28 + assign \insn_in$9 32'00000000000000000000000000000000 + assign \insn_in$9 \dec_opcode_in + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + wire width 32 \insn_in$10 + process $group_29 + assign \insn_in$10 32'00000000000000000000000000000000 + assign \insn_in$10 \dec_opcode_in + sync init + end + process $group_30 + assign \dec_a_sel_in 3'000 + assign \dec_a_sel_in \dec_in1_sel + sync init + end process $group_31 - assign \rego$25 5'00000 - assign \rego_ok$26 1'0 - assign { \rego_ok$26 \rego$25 } { \dec_o_reg_o_ok \dec_o_reg_o } + assign \dec_b_sel_in 4'0000 + assign \dec_b_sel_in \dec_in2_sel + sync init + end + process $group_32 + assign \dec_c_sel_in 2'00 + assign \dec_c_sel_in \dec_in3_sel sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \ea$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ea_ok$28 process $group_33 - assign \ea$27 5'00000 - assign \ea_ok$28 1'0 - assign { \ea_ok$28 \ea$27 } { \dec_o2_reg_o_ok \dec_o2_reg_o } + assign \dec_o_sel_in 2'00 + assign \dec_o_sel_in \dec_out_sel + sync init + end + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + wire width 2 \sel_in + process $group_34 + assign \sel_in 2'00 + assign \sel_in \dec_out_sel sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \imm$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \imm_ok$30 process $group_35 - assign \imm$29 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \imm_ok$30 1'0 - assign { \imm_ok$30 \imm$29 } { \dec_b_imm_b_ok \dec_b_imm_b } + assign \dec_o2_lk 1'0 + assign \dec_o2_lk \tmp_tmp_lk sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 \zero_a$31 - process $group_37 - assign \zero_a$31 1'0 - assign \zero_a$31 \dec_a_immz_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \tmp_reg1_ok + process $group_36 + assign \tmp_reg1 5'00000 + assign \tmp_reg1_ok 1'0 + assign { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rc$32 + wire width 5 \tmp_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rc_ok$33 + wire width 1 \tmp_reg2_ok process $group_38 - assign \rc$32 1'0 - assign \rc_ok$33 1'0 - assign { \rc_ok$33 \rc$32 } { \dec_rc_rc_ok \dec_rc_rc } + assign \tmp_reg2 5'00000 + assign \tmp_reg2_ok 1'0 + assign { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe$34 + wire width 5 \tmp_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe_ok$35 + wire width 1 \tmp_reg3_ok process $group_40 - assign \oe$34 1'0 - assign \oe_ok$35 1'0 - assign { \oe_ok$35 \oe$34 } { \dec_oe_oe_ok \dec_oe_oe } + assign \tmp_reg3 5'00000 + assign \tmp_reg3_ok 1'0 + assign { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \tmp_rego_ok + process $group_42 + assign \tmp_rego 5'00000 + assign \tmp_rego_ok 1'0 + assign { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \tmp_ea_ok + process $group_44 + assign \tmp_ea 5'00000 + assign \tmp_ea_ok 1'0 + assign { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } sync init end attribute \enum_base_type "SPR" @@ -163932,13 +274131,13 @@ module \dec2 attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \spr1$36 + wire width 10 \tmp_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$37 - process $group_42 - assign \spr1$36 10'0000000000 - assign \spr1_ok$37 1'0 - assign { \spr1_ok$37 \spr1$36 } { \dec_a_spr_a_ok \dec_a_spr_a } + wire width 1 \tmp_spr1_ok + process $group_46 + assign \tmp_spr1 10'0000000000 + assign \tmp_spr1_ok 1'0 + assign { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } sync init end attribute \enum_base_type "SPR" @@ -164053,225 +274252,101 @@ module \dec2 attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \spro$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spro_ok$39 - process $group_44 - assign \spro$38 10'0000000000 - assign \spro_ok$39 1'0 - assign { \spro_ok$39 \spro$38 } { \dec_o_spr_o_ok \dec_o_spr_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \fast1$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$41 - process $group_46 - assign \fast1$40 3'000 - assign \fast1_ok$41 1'0 - assign { \fast1_ok$41 \fast1$40 } { \dec_a_fast_a_ok \dec_a_fast_a } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \fast2$42 + wire width 10 \tmp_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$43 + wire width 1 \tmp_spro_ok process $group_48 - assign \fast2$42 3'000 - assign \fast2_ok$43 1'0 - assign { \fast2_ok$43 \fast2$42 } { \dec_b_fast_b_ok \dec_b_fast_b } + assign \tmp_spro 10'0000000000 + assign \tmp_spro_ok 1'0 + assign { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \fasto1$44 + wire width 3 \tmp_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto1_ok$45 + wire width 1 \tmp_fast1_ok process $group_50 - assign \fasto1$44 3'000 - assign \fasto1_ok$45 1'0 - assign { \fasto1_ok$45 \fasto1$44 } { \dec_o_fast_o_ok \dec_o_fast_o } + assign \tmp_fast1 3'000 + assign \tmp_fast1_ok 1'0 + assign { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \fasto2$46 + wire width 3 \tmp_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto2_ok$47 + wire width 1 \tmp_fast2_ok process $group_52 - assign \fasto2$46 3'000 - assign \fasto2_ok$47 1'0 - assign { \fasto2_ok$47 \fasto2$46 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + assign \tmp_fast2 3'000 + assign \tmp_fast2_ok 1'0 + assign { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_in1$48 + wire width 3 \tmp_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_in1_ok$49 + wire width 1 \tmp_fasto1_ok process $group_54 - assign \cr_in1$48 3'000 - assign \cr_in1_ok$49 1'0 - assign { \cr_in1_ok$49 \cr_in1$48 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + assign \tmp_fasto1 3'000 + assign \tmp_fasto1_ok 1'0 + assign { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_in2$50 + wire width 3 \tmp_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_in2_ok$51 + wire width 1 \tmp_fasto2_ok process $group_56 - assign \cr_in2$50 3'000 - assign \cr_in2_ok$51 1'0 - assign { \cr_in2_ok$51 \cr_in2$50 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + assign \tmp_fasto2 3'000 + assign \tmp_fasto2_ok 1'0 + assign { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_in2$52 + wire width 3 \tmp_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_in2_ok$53 + wire width 1 \tmp_cr_in1_ok process $group_58 - assign \cr_in2$52 3'000 - assign \cr_in2_ok$53 1'0 - assign { \cr_in2_ok$53 \cr_in2$52 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + assign \tmp_cr_in1 3'000 + assign \tmp_cr_in1_ok 1'0 + assign { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_out$54 + wire width 3 \tmp_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_out_ok$55 + wire width 1 \tmp_cr_in2_ok process $group_60 - assign \cr_out$54 3'000 - assign \cr_out_ok$55 1'0 - assign { \cr_out_ok$55 \cr_out$54 } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + assign \tmp_cr_in2 3'000 + assign \tmp_cr_in2_ok 1'0 + assign { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 \read_cr_whole$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \tmp_cr_in2_ok$12 process $group_62 - assign \read_cr_whole$56 1'0 - assign \read_cr_whole$56 \dec_cr_in_whole_reg - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 \write_cr_whole$57 - process $group_63 - assign \write_cr_whole$57 1'0 - assign \write_cr_whole$57 \dec_cr_out_whole_reg + assign \tmp_cr_in2$11 3'000 + assign \tmp_cr_in2_ok$12 1'0 + assign { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 \write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \tmp_cr_out_ok process $group_64 - assign \write_cr0$58 1'0 - assign \write_cr0$58 \dec_cr_out_cr_bitfield_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 \data_len$59 - process $group_65 - assign \data_len$59 4'0000 - assign \data_len$59 \dec_ldst_len - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 \invert_in$60 - process $group_66 - assign \invert_in$60 1'0 - assign \invert_in$60 \dec_inv_a - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 \invert_out$61 - process $group_67 - assign \invert_out$61 1'0 - assign \invert_out$61 \dec_inv_out - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 \input_carry$62 - process $group_68 - assign \input_carry$62 2'00 - assign \input_carry$62 \dec_cry_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \output_carry$63 - process $group_69 - assign \output_carry$63 1'0 - assign \output_carry$63 \dec_cry_out - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 \is_32bit$64 - process $group_70 - assign \is_32bit$64 1'0 - assign \is_32bit$64 \dec_is_32b - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 \is_signed$65 - process $group_71 - assign \is_signed$65 1'0 - assign \is_signed$65 \dec_sgn - sync init - end - process $group_72 - assign \lk$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680" - switch { \dec_lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680" - case 1'1 - assign \lk$14 \dec_LK - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 \byte_reverse$66 - process $group_73 - assign \byte_reverse$66 1'0 - assign \byte_reverse$66 \dec_br - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \sign_extend$67 - process $group_74 - assign \sign_extend$67 1'0 - assign \sign_extend$67 \dec_sgn_ext - sync init - end - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 \ldst_mode$68 - process $group_75 - assign \ldst_mode$68 2'00 - assign \ldst_mode$68 \dec_upd - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 \input_cr$69 - process $group_76 - assign \input_cr$69 1'0 - assign \input_cr$69 \dec_cr_in [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 \output_cr$70 - process $group_77 - assign \output_cr$70 1'0 - assign \output_cr$70 \dec_cr_out [0] + assign \tmp_cr_out 3'000 + assign \tmp_cr_out_ok 1'0 + assign { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 \xer_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" - cell $eq $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + cell $eq $14 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164279,24 +274354,43 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $72 + connect \Y $13 end - process $group_78 - assign \xer_in$71 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" - switch { $72 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" + cell $eq $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $15 + end + process $group_66 + assign \tmp_xer_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + case 1'1 + assign \tmp_xer_in 3'111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" + switch { $15 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" case 1'1 - assign \xer_in$71 1'1 + assign \tmp_xer_in 3'001 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" - wire width 1 \xer_out$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - cell $eq $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire width 1 \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" + cell $eq $18 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164304,24 +274398,24 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $75 + connect \Y $17 end - process $group_79 - assign \xer_out$74 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" + process $group_67 + assign \tmp_xer_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" + switch { $17 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" case 1'1 - assign \xer_out$74 1'1 + assign \tmp_xer_out 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 13 \trapaddr$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" - cell $eq $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164329,57 +274423,106 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $78 + connect \Y $19 end - process $group_80 - assign \trapaddr$77 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" - switch { $78 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" + process $group_68 + assign \tmp_tmp_trapaddr 13'0000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" case 1'1 - assign \trapaddr$77 13'0000001110000 + assign \tmp_tmp_trapaddr 13'0000001110000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" wire width 1 \is_priv_insn - process $group_81 + process $group_69 assign \is_priv_insn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" switch \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110 assign \is_priv_insn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:48" attribute \nmigen.decoding "OP_MFSPR/46|OP_MTSPR/49" case 7'0101110, 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" - switch { \insn$5 [20] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" + switch { \tmp_tmp_insn [20] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" case 1'1 assign \is_priv_insn 1'1 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" - cell $and $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:881" + wire width 1 \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $21 + end + process $group_70 + assign \ext_irq_ok 1'0 + assign \ext_irq_ok $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + wire width 1 \dec_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + cell $and $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $23 + end + process $group_71 + assign \dec_irq_ok 1'0 + assign \dec_irq_ok $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:883" + wire width 1 \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" + cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_priv_insn - connect \B \dec2_msr [14] - connect \Y $80 + connect \B \cur_msr [14] + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" - cell $eq $83 + process $group_72 + assign \priv_ok 1'0 + assign \priv_ok $25 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" + wire width 1 \illeg_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164387,16 +274530,21 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $82 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 8 \asmcode$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 \traptype$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:724" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:724" - cell $eq $87 + process $group_73 + assign \illeg_ok 1'0 + assign \illeg_ok $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $30 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164404,12 +274552,12 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $86 + connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" - wire width 1 $88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" - cell $eq $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + cell $eq $32 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164417,25 +274565,25 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $88 + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" - wire width 1 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" - cell $or $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + cell $or $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $86 - connect \B $88 - connect \Y $90 + connect \A $29 + connect \B $31 + connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" - cell $eq $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" + cell $eq $36 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -164443,9 +274591,9 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $92 + connect \Y $35 end - process $group_82 + process $group_74 assign \asmcode 8'00000000 assign \rego 5'00000 assign \rego_ok 1'0 @@ -164461,7 +274609,7 @@ module \dec2 assign \spro_ok 1'0 assign \spr1 10'0000000000 assign \spr1_ok 1'0 - assign \xer_in 1'0 + assign \xer_in 3'000 assign \xer_out 1'0 assign \fast1 3'000 assign \fast1_ok 1'0 @@ -164484,69 +274632,77 @@ module \dec2 assign \insn 32'00000000000000000000000000000000 assign \insn_type 7'0000000 assign \fn_unit 11'00000000000 - assign \imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \imm_ok 1'0 assign \lk 1'0 assign \rc 1'0 assign \rc_ok 1'0 assign \oe 1'0 assign \oe_ok 1'0 - assign \invert_in 1'0 - assign \zero_a 1'0 assign \input_carry 2'00 - assign \output_carry 1'0 - assign \input_cr 1'0 - assign \output_cr 1'0 - assign \invert_out 1'0 - assign \is_32bit 1'0 - assign \is_signed 1'0 - assign \data_len 4'0000 - assign \byte_reverse 1'0 - assign \sign_extend 1'0 - assign \ldst_mode 2'00 - assign \traptype 5'00000 + assign \traptype 7'0000000 assign \trapaddr 13'0000000000000 - assign \read_cr_whole 1'0 - assign \write_cr_whole 1'0 - assign \write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" - switch { $82 $80 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" - case 2'-1 - assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_in \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \cr_rd 8'00000000 + assign \cr_rd_ok 1'0 + assign \cr_wr 8'00000000 + assign \cr_wr_ok 1'0 + assign \is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + case 4'---1 + assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \insn \dec_opcode_in + assign \insn_type 7'0111111 + assign \fn_unit 11'00010000000 + assign \trapaddr 13'0000010010000 + assign \traptype 7'0100000 + assign \msr \cur_msr + assign \cia \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:896" + case 4'--1- + assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \insn \dec_opcode_in + assign \insn_type 7'0111111 + assign \fn_unit 11'00010000000 + assign \trapaddr 13'0000001010000 + assign \traptype 7'0010000 + assign \msr \cur_msr + assign \cia \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:900" + case 4'-1-- + assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign \insn \dec_opcode_in assign \insn_type 7'0111111 assign \fn_unit 11'00010000000 assign \trapaddr 13'0000001110000 - assign \traptype 5'00010 - assign \msr \dec2_msr - assign \cia \dec2_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" - case 2'1- - assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_in \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \traptype 7'0000010 + assign \msr \cur_msr + assign \cia \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:907" + case 4'1--- + assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign \insn \dec_opcode_in assign \insn_type 7'0111111 assign \fn_unit 11'00010000000 assign \trapaddr 13'0000001110000 - assign \traptype 5'10000 - assign \msr \dec2_msr - assign \cia \dec2_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + assign \traptype 7'1000000 + assign \msr \cur_msr + assign \cia \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" case - assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_in \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } { \write_cr0$58 \write_cr_whole$57 \read_cr_whole$56 \trapaddr$77 \traptype$85 \ldst_mode$68 \sign_extend$67 \byte_reverse$66 \data_len$59 \is_signed$65 \is_32bit$64 \invert_out$61 \output_cr$70 \input_cr$69 \output_carry$63 \input_carry$62 \zero_a$31 \invert_in$60 \oe_ok$35 \oe$34 \rc_ok$33 \rc$32 \lk$14 \imm_ok$30 \imm$29 \fn_unit$18 \insn_type$17 \insn$5 \cia$16 \msr$15 { \cr_out_ok$55 \cr_out$54 } { \cr_in2_ok$53 \cr_in2$52 } { \cr_in2_ok$51 \cr_in2$50 } { \cr_in1_ok$49 \cr_in1$48 } { \fasto2_ok$47 \fasto2$46 } { \fasto1_ok$45 \fasto1$44 } { \fast2_ok$43 \fast2$42 } { \fast1_ok$41 \fast1$40 } \xer_out$74 \xer_in$71 { \spr1_ok$37 \spr1$36 } { \spro_ok$39 \spro$38 } { \reg3_ok$24 \reg3$23 } { \reg2_ok$22 \reg2$21 } { \reg1_ok$20 \reg1$19 } { \ea_ok$28 \ea$27 } { \rego_ok$26 \rego$25 } \asmcode$84 } + assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr { \tmp_cr_out_ok \tmp_cr_out } { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \tmp_cr_in2_ok \tmp_cr_in2 } { \tmp_cr_in1_ok \tmp_cr_in1 } { \tmp_fasto2_ok \tmp_fasto2 } { \tmp_fasto1_ok \tmp_fasto1 } { \tmp_fast2_ok \tmp_fast2 } { \tmp_fast1_ok \tmp_fast1 } \tmp_xer_out \tmp_xer_in { \tmp_spr1_ok \tmp_spr1 } { \tmp_spro_ok \tmp_spro } { \tmp_reg3_ok \tmp_reg3 } { \tmp_reg2_ok \tmp_reg2 } { \tmp_reg1_ok \tmp_reg1 } { \tmp_ea_ok \tmp_ea } { \tmp_rego_ok \tmp_rego } \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" - switch { $90 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + switch { $33 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" case 1'1 assign \fasto1 3'011 assign \fasto1_ok 1'1 assign \fasto2 3'100 assign \fasto2_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" - switch { $92 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" + switch { $35 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" case 1'1 assign \fast1 3'011 assign \fast1_ok 1'1 @@ -164555,8 +274711,8 @@ module \dec2 end sync init end - connect \asmcode$84 8'00000000 - connect \traptype$85 5'00000 + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 7'0000000 end attribute \generator "nMigen" attribute \top 1 @@ -164566,29 +274722,29 @@ module \test_issuer wire width 64 input 0 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 input 1 \pc_i_ok - attribute \src "simple/issuer.py:62" + attribute \src "simple/issuer.py:81" wire width 64 output 2 \pc_o - attribute \src "simple/issuer.py:66" + attribute \src "simple/issuer.py:85" wire width 1 input 3 \memerr_o - attribute \src "simple/issuer.py:64" + attribute \src "simple/issuer.py:83" wire width 1 input 4 \core_bigendian_i - attribute \src "simple/issuer.py:101" - wire width 1 input 5 \clk - attribute \src "simple/issuer.py:101" - wire width 1 input 6 \rst - attribute \src "simple/issuer.py:65" - wire width 1 output 7 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55" + attribute \src "simple/issuer.py:84" + wire width 1 output 5 \busy_o + attribute \src "simple/issuer.py:140" + wire width 1 input 6 \clk + attribute \src "simple/issuer.py:140" + wire width 1 input 7 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" wire width 4 input 8 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" wire width 64 input 9 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" wire width 64 output 10 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" wire width 1 input 11 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" wire width 1 input 12 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire width 1 output 13 \dmi_ack_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 45 output 14 \ibus__adr @@ -164634,13 +274790,13 @@ module \test_issuer wire width 2 input 34 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 1 input 35 \dbus__err - attribute \src "simple/issuer.py:100" + attribute \src "simple/issuer.py:139" wire width 1 \por_clk - attribute \src "simple/issuer.py:102" + attribute \src "simple/issuer.py:141" wire width 1 \core_coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire width 1 \core_core_reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:84" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 1 \core_corebusy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 1 \core_cu_st__rel_o @@ -164651,49 +274807,49 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 1 \core_cu_st__go_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_cia__ren + wire width 4 \core_cia__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_wen + wire width 4 \core_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire width 4 \core_msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" wire width 1 \core_core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_rego + wire width 5 \core_core_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_rego$next + wire width 5 \core_core_rego$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_ea + wire width 5 \core_core_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_ea$next + wire width 5 \core_core_ea$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg1 + wire width 5 \core_core_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg1$next + wire width 5 \core_core_reg1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_reg1_ok + wire width 1 \core_core_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_reg1_ok$next + wire width 1 \core_core_reg1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg2 + wire width 5 \core_core_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg2$next + wire width 5 \core_core_reg2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_reg2_ok + wire width 1 \core_core_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_reg2_ok$next + wire width 1 \core_core_reg2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg3 + wire width 5 \core_core_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg3$next + wire width 5 \core_core_reg3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_reg3_ok + wire width 1 \core_core_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_reg3_ok$next + wire width 1 \core_core_reg3_ok$next attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -164806,9 +274962,9 @@ module \test_issuer attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spro + wire width 10 \core_core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spro$next + wire width 10 \core_core_spro$next attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -164921,81 +275077,81 @@ module \test_issuer attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spr1 + wire width 10 \core_core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spr1$next + wire width 10 \core_core_spr1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_spr1_ok + wire width 1 \core_core_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 \core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 \core_xer_in$next + wire width 1 \core_core_spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \core_core_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast1 + wire width 3 \core_core_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast1$next + wire width 3 \core_core_fast1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fast1_ok + wire width 1 \core_core_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fast1_ok$next + wire width 1 \core_core_fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast2 + wire width 3 \core_core_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast2$next + wire width 3 \core_core_fast2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fast2_ok + wire width 1 \core_core_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fast2_ok$next + wire width 1 \core_core_fast2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto1 + wire width 3 \core_core_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto1$next + wire width 3 \core_core_fasto1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto2 + wire width 3 \core_core_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto2$next + wire width 3 \core_core_fasto2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in1 + wire width 3 \core_core_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in1$next + wire width 3 \core_core_cr_in1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_in1_ok + wire width 1 \core_core_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_in1_ok$next + wire width 1 \core_core_cr_in1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2 + wire width 3 \core_core_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2$next + wire width 3 \core_core_cr_in2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_in2_ok + wire width 1 \core_core_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_in2_ok$next + wire width 1 \core_core_cr_in2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2$1 + wire width 3 \core_core_cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2$1$next + wire width 3 \core_core_cr_in2$1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_in2_ok$2 + wire width 1 \core_core_cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_in2_ok$2$next + wire width 1 \core_core_cr_in2_ok$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_out + wire width 3 \core_core_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 64 \core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 64 \core_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" - wire width 64 \core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" - wire width 64 \core_cia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" - wire width 32 \core_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" - wire width 32 \core_insn$next + wire width 3 \core_core_cr_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_core_cia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_core_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_core_insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -165069,10 +275225,10 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" - wire width 7 \core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" - wire width 7 \core_insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_core_insn_type$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -165085,133 +275241,104 @@ module \test_issuer attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" - wire width 11 \core_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" - wire width 11 \core_fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \core_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \core_imm$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_imm_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 1 \core_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 1 \core_lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 11 \core_core_core_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 11 \core_core_core_fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_rc + wire width 1 \core_core_core_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_rc$next + wire width 1 \core_core_core_rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_rc_ok + wire width 1 \core_core_core_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_rc_ok$next + wire width 1 \core_core_core_rc_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_oe + wire width 1 \core_core_core_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_oe$next + wire width 1 \core_core_core_oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_oe_ok + wire width 1 \core_core_core_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_oe_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 \core_invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 \core_invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 \core_zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 \core_zero_a$next + wire width 1 \core_core_core_oe_ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 \core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 \core_input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \core_output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \core_output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 \core_input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 \core_input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 \core_output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 \core_output_cr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 \core_invert_out + wire width 2 \core_core_core_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 \core_invert_out$next + wire width 2 \core_core_core_input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 \core_is_32bit + wire width 7 \core_core_core_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 \core_is_32bit$next + wire width 7 \core_core_core_traptype$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 \core_is_signed + wire width 13 \core_core_core_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 \core_is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 \core_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 \core_data_len$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 \core_byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 \core_byte_reverse$next + wire width 13 \core_core_core_trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \core_core_core_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \core_core_core_cr_rd_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_wr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \core_sign_extend + wire width 1 \core_core_core_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \core_sign_extend$next - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 \core_ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 \core_ldst_mode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 \core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 \core_traptype$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 13 \core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 13 \core_trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 \core_read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 \core_read_cr_whole$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 \core_write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 \core_write_cr_whole$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 \core_write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 \core_write_cr0$next + wire width 1 \core_core_core_is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" + wire width 32 \core_raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" + wire width 32 \core_raw_insn_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + wire width 1 \core_bigendian_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + wire width 1 \core_bigendian_i$3$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_msr__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \core_core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \core_core_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" wire width 1 \core_ivalid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" wire width 1 \core_issue_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_state_nia_wen + wire width 4 \core_state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 5 \core_dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \core_dmi__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \core_full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \core_full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \core_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \core_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \core_issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \core_issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \core_issue__addr$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \core_issue__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_issue__data_i cell \core \core connect \coresync_clk \core_coresync_clk connect \core_reset_i \core_core_reset_i @@ -165226,68 +275353,67 @@ module \test_issuer connect \data_i \core_data_i connect \msr__ren \core_msr__ren connect \core_terminate_o \core_core_terminate_o - connect \rego \core_rego - connect \ea \core_ea - connect \reg1 \core_reg1 - connect \reg1_ok \core_reg1_ok - connect \reg2 \core_reg2 - connect \reg2_ok \core_reg2_ok - connect \reg3 \core_reg3 - connect \reg3_ok \core_reg3_ok - connect \spro \core_spro - connect \spr1 \core_spr1 - connect \spr1_ok \core_spr1_ok - connect \xer_in \core_xer_in - connect \fast1 \core_fast1 - connect \fast1_ok \core_fast1_ok - connect \fast2 \core_fast2 - connect \fast2_ok \core_fast2_ok - connect \fasto1 \core_fasto1 - connect \fasto2 \core_fasto2 - connect \cr_in1 \core_cr_in1 - connect \cr_in1_ok \core_cr_in1_ok - connect \cr_in2 \core_cr_in2 - connect \cr_in2_ok \core_cr_in2_ok - connect \cr_in2$1 \core_cr_in2$1 - connect \cr_in2_ok$2 \core_cr_in2_ok$2 - connect \cr_out \core_cr_out - connect \msr \core_msr - connect \cia \core_cia - connect \insn \core_insn - connect \insn_type \core_insn_type - connect \fn_unit \core_fn_unit - connect \imm \core_imm - connect \imm_ok \core_imm_ok - connect \lk \core_lk - connect \rc \core_rc - connect \rc_ok \core_rc_ok - connect \oe \core_oe - connect \oe_ok \core_oe_ok - connect \invert_in \core_invert_in - connect \zero_a \core_zero_a - connect \input_carry \core_input_carry - connect \output_carry \core_output_carry - connect \input_cr \core_input_cr - connect \output_cr \core_output_cr - connect \invert_out \core_invert_out - connect \is_32bit \core_is_32bit - connect \is_signed \core_is_signed - connect \data_len \core_data_len - connect \byte_reverse \core_byte_reverse - connect \sign_extend \core_sign_extend - connect \ldst_mode \core_ldst_mode - connect \traptype \core_traptype - connect \trapaddr \core_trapaddr - connect \read_cr_whole \core_read_cr_whole - connect \write_cr_whole \core_write_cr_whole - connect \write_cr0 \core_write_cr0 + connect \core_rego \core_core_rego + connect \core_ea \core_core_ea + connect \core_reg1 \core_core_reg1 + connect \core_reg1_ok \core_core_reg1_ok + connect \core_reg2 \core_core_reg2 + connect \core_reg2_ok \core_core_reg2_ok + connect \core_reg3 \core_core_reg3 + connect \core_reg3_ok \core_core_reg3_ok + connect \core_spro \core_core_spro + connect \core_spr1 \core_core_spr1 + connect \core_spr1_ok \core_core_spr1_ok + connect \core_xer_in \core_core_xer_in + connect \core_fast1 \core_core_fast1 + connect \core_fast1_ok \core_core_fast1_ok + connect \core_fast2 \core_core_fast2 + connect \core_fast2_ok \core_core_fast2_ok + connect \core_fasto1 \core_core_fasto1 + connect \core_fasto2 \core_core_fasto2 + connect \core_cr_in1 \core_core_cr_in1 + connect \core_cr_in1_ok \core_core_cr_in1_ok + connect \core_cr_in2 \core_core_cr_in2 + connect \core_cr_in2_ok \core_core_cr_in2_ok + connect \core_cr_in2$1 \core_core_cr_in2$1 + connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 + connect \core_cr_out \core_core_cr_out + connect \core_core_msr \core_core_core_msr + connect \core_core_cia \core_core_core_cia + connect \core_core_insn \core_core_core_insn + connect \core_core_insn_type \core_core_core_insn_type + connect \core_core_fn_unit \core_core_core_fn_unit + connect \core_core_rc \core_core_core_rc + connect \core_core_rc_ok \core_core_core_rc_ok + connect \core_core_oe \core_core_core_oe + connect \core_core_oe_ok \core_core_core_oe_ok + connect \core_core_input_carry \core_core_core_input_carry + connect \core_core_traptype \core_core_core_traptype + connect \core_core_trapaddr \core_core_core_trapaddr + connect \core_core_cr_rd \core_core_core_cr_rd + connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok + connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_is_32bit \core_core_core_is_32bit + connect \raw_insn_i \core_raw_insn_i + connect \bigendian_i \core_bigendian_i$3 connect \msr__data_o \core_msr__data_o + connect \core_pc \core_core_pc connect \ivalid_i \core_ivalid_i connect \issue_i \core_issue_i connect \state_nia_wen \core_state_nia_wen connect \dmi__addr \core_dmi__addr connect \dmi__ren \core_dmi__ren connect \dmi__data_o \core_dmi__data_o + connect \full_rd2__ren \core_full_rd2__ren + connect \full_rd2__data_o \core_full_rd2__data_o + connect \full_rd__ren \core_full_rd__ren + connect \full_rd__data_o \core_full_rd__data_o + connect \issue__addr \core_issue__addr + connect \issue__ren \core_issue__ren + connect \issue__data_o \core_issue__data_o + connect \issue__addr$3 \core_issue__addr$4 + connect \issue__wen \core_issue__wen + connect \issue__data_i \core_issue__data_i connect \dbus__cyc \dbus__cyc connect \dbus__ack \dbus__ack connect \dbus__err \dbus__err @@ -165324,26 +275450,38 @@ module \test_issuer connect \ibus__dat_r \ibus__dat_r connect \ibus__adr \ibus__adr end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:90" wire width 1 \dbg_core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:94" wire width 1 \dbg_terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 \dbg_core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:89" wire width 1 \dbg_core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" wire width 1 \dbg_core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66" - wire width 1 \dbg_dbg_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 7 \dbg_dbg_gpr_addr + wire width 1 \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:70" + wire width 7 \dbg_d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 \dbg_d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire width 1 \dbg_d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire width 1 \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 \dbg_d_cr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 64 \dbg_dbg_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67" - wire width 1 \dbg_dbg_gpr_ack + wire width 1 \dbg_d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire width 1 \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 \dbg_d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire width 1 \dbg_d_xer_ack cell \dbg \dbg connect \clk \clk connect \core_rst_o \dbg_core_rst_o @@ -165352,27 +275490,37 @@ module \test_issuer connect \core_dbg_msr \dbg_core_dbg_msr connect \core_stop_o \dbg_core_stop_o connect \core_stopped_i \dbg_core_stopped_i - connect \dbg_gpr_req \dbg_dbg_gpr_req - connect \dbg_gpr_addr \dbg_dbg_gpr_addr - connect \dbg_gpr_data \dbg_dbg_gpr_data - connect \dbg_gpr_ack \dbg_dbg_gpr_ack + connect \d_gpr_req \dbg_d_gpr_req + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_cr_req \dbg_d_cr_req + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_ack \dbg_d_cr_ack + connect \d_xer_req \dbg_d_xer_req + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_ack \dbg_d_xer_ack connect \rst \rst - connect \dmi_ack_o \dmi_ack_o connect \dmi_addr_i \dmi_addr_i + connect \dmi_ack_o \dmi_ack_o connect \dmi_req_i \dmi_req_i connect \dmi_dout \dmi_dout connect \dmi_we_i \dmi_we_i connect \dmi_din \dmi_din end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" wire width 1 \dec2_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:337" - wire width 32 \dec2_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_dec2_pc + wire width 64 \dec2_cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 64 \dec2_cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" wire width 8 \dec2_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 5 \dec2_rego @@ -165624,9 +275772,9 @@ module \test_issuer wire width 10 \dec2_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec2_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 \dec2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" wire width 1 \dec2_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 3 \dec2_fast1 @@ -165653,18 +275801,18 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec2_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in2$3 + wire width 3 \dec2_cr_in2$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_in2_ok$4 + wire width 1 \dec2_cr_in2_ok$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 3 \dec2_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec2_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" wire width 64 \dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 \dec2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -165739,7 +275887,7 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 7 \dec2_insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" @@ -165753,13 +275901,9 @@ module \test_issuer attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 11 \dec2_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec2_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 1 \dec2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec2_rc @@ -165769,56 +275913,37 @@ module \test_issuer wire width 1 \dec2_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 \dec2_invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 \dec2_zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 \dec2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \dec2_output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 \dec2_input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 \dec2_output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 \dec2_invert_out + wire width 2 \dec2_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 \dec2_is_32bit + wire width 7 \dec2_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 \dec2_is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 \dec2_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 \dec2_byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \dec2_sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 \dec2_ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 \dec2_read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 \dec2_write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 \dec2_write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire width 1 \dec2_cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec$next cell \dec2 \dec2 connect \bigendian \dec2_bigendian + connect \cur_pc \dec2_cur_pc + connect \cur_msr \dec2_cur_msr connect \raw_opcode_in \dec2_raw_opcode_in - connect \dec2_pc \dec2_dec2_pc - connect \dec2_msr \dec2_dec2_msr connect \asmcode \dec2_asmcode connect \rego \dec2_rego connect \rego_ok \dec2_rego_ok @@ -165848,8 +275973,8 @@ module \test_issuer connect \cr_in1_ok \dec2_cr_in1_ok connect \cr_in2 \dec2_cr_in2 connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2$1 \dec2_cr_in2$3 - connect \cr_in2_ok$2 \dec2_cr_in2_ok$4 + connect \cr_in2$1 \dec2_cr_in2$5 + connect \cr_in2_ok$2 \dec2_cr_in2_ok$6 connect \cr_out \dec2_cr_out connect \cr_out_ok \dec2_cr_out_ok connect \msr \dec2_msr @@ -165857,40 +275982,30 @@ module \test_issuer connect \insn \dec2_insn connect \insn_type \dec2_insn_type connect \fn_unit \dec2_fn_unit - connect \imm \dec2_imm - connect \imm_ok \dec2_imm_ok connect \lk \dec2_lk connect \rc \dec2_rc connect \rc_ok \dec2_rc_ok connect \oe \dec2_oe connect \oe_ok \dec2_oe_ok - connect \invert_in \dec2_invert_in - connect \zero_a \dec2_zero_a connect \input_carry \dec2_input_carry - connect \output_carry \dec2_output_carry - connect \input_cr \dec2_input_cr - connect \output_cr \dec2_output_cr - connect \invert_out \dec2_invert_out - connect \is_32bit \dec2_is_32bit - connect \is_signed \dec2_is_signed - connect \data_len \dec2_data_len - connect \byte_reverse \dec2_byte_reverse - connect \sign_extend \dec2_sign_extend - connect \ldst_mode \dec2_ldst_mode connect \traptype \dec2_traptype connect \trapaddr \dec2_trapaddr - connect \read_cr_whole \dec2_read_cr_whole - connect \write_cr_whole \dec2_write_cr_whole - connect \write_cr0 \dec2_write_cr0 + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \is_32bit \dec2_is_32bit + connect \cur_eint \dec2_cur_eint + connect \cur_dec \dec2_cur_dec end - attribute \src "simple/issuer.py:105" + attribute \src "simple/issuer.py:144" wire width 2 \delay - attribute \src "simple/issuer.py:105" + attribute \src "simple/issuer.py:144" wire width 2 \delay$next - attribute \src "simple/issuer.py:106" - wire width 1 $5 - attribute \src "simple/issuer.py:106" - cell $ne $6 + attribute \src "simple/issuer.py:145" + wire width 1 $7 + attribute \src "simple/issuer.py:145" + cell $ne $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -165898,14 +276013,14 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $5 + connect \Y $7 end - attribute \src "simple/issuer.py:107" - wire width 3 $7 - attribute \src "simple/issuer.py:107" - wire width 3 $8 - attribute \src "simple/issuer.py:107" - cell $sub $9 + attribute \src "simple/issuer.py:146" + wire width 3 $9 + attribute \src "simple/issuer.py:146" + wire width 3 $10 + attribute \src "simple/issuer.py:146" + cell $sub $11 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -165913,16 +276028,16 @@ module \test_issuer parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $8 + connect \Y $10 end - connect $7 $8 + connect $9 $10 process $group_0 assign \delay$next \delay - attribute \src "simple/issuer.py:106" - switch { $5 } - attribute \src "simple/issuer.py:106" + attribute \src "simple/issuer.py:145" + switch { $7 } + attribute \src "simple/issuer.py:145" case 1'1 - assign \delay$next $7 [1:0] + assign \delay$next $9 [1:0] end sync init update \delay 2'11 @@ -165939,10 +276054,10 @@ module \test_issuer assign \core_coresync_clk \clk sync init end - attribute \src "simple/issuer.py:111" - wire width 1 $10 - attribute \src "simple/issuer.py:111" - cell $or $11 + attribute \src "simple/issuer.py:150" + wire width 1 $12 + attribute \src "simple/issuer.py:150" + cell $or $13 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -165950,24 +276065,24 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $10 + connect \Y $12 end - attribute \src "simple/issuer.py:111" - wire width 1 $12 - attribute \src "simple/issuer.py:111" - cell $ne $13 + attribute \src "simple/issuer.py:150" + wire width 1 $14 + attribute \src "simple/issuer.py:150" + cell $ne $15 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \delay - connect \B $10 - connect \Y $12 + connect \B $12 + connect \Y $14 end process $group_3 assign \core_core_reset_i 1'0 - assign \core_core_reset_i $12 + assign \core_core_reset_i $14 sync init end process $group_4 @@ -165995,31 +276110,31 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire width 1 \cu_st__rel_o_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $14 + wire width 1 $16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $15 + cell $not $17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $14 + connect \Y $16 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $16 + wire width 1 $18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $17 + cell $and $19 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o - connect \B $14 - connect \Y $16 + connect \B $16 + connect \Y $18 end process $group_7 assign \cu_st__rel_o_rise 1'0 - assign \cu_st__rel_o_rise $16 + assign \cu_st__rel_o_rise $18 sync init end process $group_8 @@ -166032,55 +276147,51 @@ module \test_issuer assign \core_cu_st__go_i \cu_st__rel_o_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \cur_pc$next process $group_10 assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pc_o \cur_pc + assign \pc_o \dec2_cur_pc sync init end - attribute \src "simple/issuer.py:133" + attribute \src "simple/issuer.py:169" wire width 64 \nia - attribute \src "simple/issuer.py:134" - wire width 65 $18 - attribute \src "simple/issuer.py:134" - wire width 65 $19 - attribute \src "simple/issuer.py:134" - cell $add $20 + attribute \src "simple/issuer.py:170" + wire width 65 $20 + attribute \src "simple/issuer.py:170" + wire width 65 $21 + attribute \src "simple/issuer.py:170" + cell $add $22 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 65 - connect \A \cur_pc + connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $19 + connect \Y $21 end - connect $18 $19 + connect $20 $21 process $group_11 assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia $18 [63:0] + assign \nia $20 [63:0] sync init end - attribute \src "simple/issuer.py:138" + attribute \src "simple/issuer.py:174" wire width 1 \pc_ok_delay - attribute \src "simple/issuer.py:138" + attribute \src "simple/issuer.py:174" wire width 1 \pc_ok_delay$next - attribute \src "simple/issuer.py:139" - wire width 1 $21 - attribute \src "simple/issuer.py:139" - cell $not $22 + attribute \src "simple/issuer.py:175" + wire width 1 $23 + attribute \src "simple/issuer.py:175" + cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $21 + connect \Y $23 end process $group_12 assign \pc_ok_delay$next \pc_ok_delay - assign \pc_ok_delay$next $21 + assign \pc_ok_delay$next $23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -166091,141 +276202,141 @@ module \test_issuer sync posedge \clk update \pc_ok_delay \pc_ok_delay$next end - attribute \src "simple/issuer.py:137" + attribute \src "simple/issuer.py:173" wire width 64 \pc process $group_13 assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:140" + attribute \src "simple/issuer.py:176" switch { \pc_i_ok } - attribute \src "simple/issuer.py:140" + attribute \src "simple/issuer.py:176" case 1'1 assign \pc \pc_i - attribute \src "simple/issuer.py:143" + attribute \src "simple/issuer.py:179" case end - attribute \src "simple/issuer.py:147" + attribute \src "simple/issuer.py:183" switch { \pc_ok_delay } - attribute \src "simple/issuer.py:147" + attribute \src "simple/issuer.py:183" case 1'1 assign \pc \core_cia__data_o end sync init end process $group_14 - assign \core_cia__ren 2'00 - attribute \src "simple/issuer.py:140" + assign \core_cia__ren 4'0000 + attribute \src "simple/issuer.py:176" switch { \pc_i_ok } - attribute \src "simple/issuer.py:140" + attribute \src "simple/issuer.py:176" case 1'1 - attribute \src "simple/issuer.py:143" + attribute \src "simple/issuer.py:179" case - assign \core_cia__ren 2'01 + assign \core_cia__ren 4'0001 end sync init end - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" wire width 2 \fsm_state - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" wire width 2 \fsm_state$next - attribute \src "simple/issuer.py:238" - wire width 1 $23 - attribute \src "simple/issuer.py:238" - cell $not $24 + attribute \src "simple/issuer.py:280" + wire width 1 $25 + attribute \src "simple/issuer.py:280" + cell $not $26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $23 + connect \Y $25 end - attribute \src "simple/issuer.py:242" - wire width 1 $25 - attribute \src "simple/issuer.py:128" + attribute \src "simple/issuer.py:284" + wire width 1 $27 + attribute \src "simple/issuer.py:164" wire width 1 \pc_changed - attribute \src "simple/issuer.py:128" + attribute \src "simple/issuer.py:164" wire width 1 \pc_changed$next - attribute \src "simple/issuer.py:242" - cell $not $26 + attribute \src "simple/issuer.py:284" + cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed - connect \Y $25 + connect \Y $27 end process $group_15 - assign \core_wen 2'00 - assign \core_wen 2'00 - attribute \src "simple/issuer.py:178" + assign \core_wen 4'0000 + assign \core_wen 4'0000 + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 - attribute \src "simple/issuer.py:238" - switch { $23 } - attribute \src "simple/issuer.py:238" + attribute \src "simple/issuer.py:280" + switch { $25 } + attribute \src "simple/issuer.py:280" case 1'1 - attribute \src "simple/issuer.py:242" - switch { $25 } - attribute \src "simple/issuer.py:242" + attribute \src "simple/issuer.py:284" + switch { $27 } + attribute \src "simple/issuer.py:284" case 1'1 - assign \core_wen 2'01 + assign \core_wen 4'0001 end end end sync init end - attribute \src "simple/issuer.py:238" - wire width 1 $27 - attribute \src "simple/issuer.py:238" - cell $not $28 + attribute \src "simple/issuer.py:280" + wire width 1 $29 + attribute \src "simple/issuer.py:280" + cell $not $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $27 + connect \Y $29 end - attribute \src "simple/issuer.py:242" - wire width 1 $29 - attribute \src "simple/issuer.py:242" - cell $not $30 + attribute \src "simple/issuer.py:284" + wire width 1 $31 + attribute \src "simple/issuer.py:284" + cell $not $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed - connect \Y $29 + connect \Y $31 end process $group_16 assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 - attribute \src "simple/issuer.py:238" - switch { $27 } - attribute \src "simple/issuer.py:238" + attribute \src "simple/issuer.py:280" + switch { $29 } + attribute \src "simple/issuer.py:280" case 1'1 - attribute \src "simple/issuer.py:242" - switch { $29 } - attribute \src "simple/issuer.py:242" + attribute \src "simple/issuer.py:284" + switch { $31 } + attribute \src "simple/issuer.py:284" case 1'1 assign \core_data_i \nia end @@ -166233,62 +276344,62 @@ module \test_issuer end sync init end - attribute \src "simple/issuer.py:184" - wire width 1 $31 - attribute \src "simple/issuer.py:184" - cell $not $32 + attribute \src "simple/issuer.py:222" + wire width 1 $33 + attribute \src "simple/issuer.py:222" + cell $not $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $31 + connect \Y $33 end - attribute \src "simple/issuer.py:184" - wire width 1 $33 - attribute \src "simple/issuer.py:184" - cell $not $34 + attribute \src "simple/issuer.py:222" + wire width 1 $35 + attribute \src "simple/issuer.py:222" + cell $not $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $33 + connect \Y $35 end - attribute \src "simple/issuer.py:184" - wire width 1 $35 - attribute \src "simple/issuer.py:184" - cell $and $36 + attribute \src "simple/issuer.py:222" + wire width 1 $37 + attribute \src "simple/issuer.py:222" + cell $and $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $31 - connect \B $33 - connect \Y $35 + connect \A $33 + connect \B $35 + connect \Y $37 end process $group_17 - assign \core_msr__ren 2'00 - assign \core_msr__ren 2'00 - attribute \src "simple/issuer.py:178" + assign \core_msr__ren 4'0000 + assign \core_msr__ren 4'0000 + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $35 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $37 } + attribute \src "simple/issuer.py:222" case 1'1 - assign \core_msr__ren 2'10 - attribute \src "simple/issuer.py:198" + assign \core_msr__ren 4'0010 + attribute \src "simple/issuer.py:237" case end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end @@ -166304,45 +276415,54 @@ module \test_issuer assign \dbg_core_dbg_pc \pc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \cur_msr$next process $group_20 assign \dbg_core_dbg_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \dbg_core_dbg_msr \cur_msr + assign \dbg_core_dbg_msr \dec2_cur_msr sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $37 + wire width 1 $39 + attribute \src "simple/issuer.py:278" + wire width 4 $40 + attribute \src "simple/issuer.py:278" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \core_state_nia_wen + connect \B 1'1 + connect \Y $40 + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $38 + cell $reduce_bool $42 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \core_state_nia_wen - connect \Y $37 + connect \A $40 + connect \Y $39 end process $group_21 assign \pc_changed$next \pc_changed - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 assign \pc_changed$next 1'0 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 - attribute \src "simple/issuer.py:236" - switch { $37 } - attribute \src "simple/issuer.py:236" + attribute \src "simple/issuer.py:278" + switch { $39 } + attribute \src "simple/issuer.py:278" case 1'1 assign \pc_changed$next 1'1 end @@ -166357,636 +276477,801 @@ module \test_issuer sync posedge \clk update \pc_changed \pc_changed$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 8 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 8 \asmcode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rego_ok + wire width 1 \core_rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rego_ok$next + wire width 1 \core_rego_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ea_ok + wire width 1 \core_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ea_ok$next + wire width 1 \core_ea_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spro_ok + wire width 1 \core_spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spro_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" - wire width 1 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" - wire width 1 \xer_out$next + wire width 1 \core_spro_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire width 1 \core_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire width 1 \core_xer_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto1_ok + wire width 1 \core_fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto1_ok$next + wire width 1 \core_fasto1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto2_ok + wire width 1 \core_fasto2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto2_ok$next + wire width 1 \core_fasto2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_out_ok + wire width 1 \core_cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_out_ok$next - attribute \src "simple/issuer.py:238" - wire width 1 $39 - attribute \src "simple/issuer.py:238" - cell $not $40 + wire width 1 \core_cr_out_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \core_core_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \core_core_lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \core_core_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \core_core_cr_wr_ok$next + attribute \src "simple/issuer.py:280" + wire width 1 $43 + attribute \src "simple/issuer.py:280" + cell $not $44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $39 + connect \Y $43 end process $group_22 - assign \asmcode$next \asmcode - assign \core_rego$next \core_rego - assign \rego_ok$next \rego_ok - assign \core_ea$next \core_ea - assign \ea_ok$next \ea_ok - assign \core_reg1$next \core_reg1 - assign \core_reg1_ok$next \core_reg1_ok - assign \core_reg2$next \core_reg2 - assign \core_reg2_ok$next \core_reg2_ok - assign \core_reg3$next \core_reg3 - assign \core_reg3_ok$next \core_reg3_ok - assign \core_spro$next \core_spro - assign \spro_ok$next \spro_ok - assign \core_spr1$next \core_spr1 - assign \core_spr1_ok$next \core_spr1_ok - assign \core_xer_in$next \core_xer_in - assign \xer_out$next \xer_out - assign \core_fast1$next \core_fast1 - assign \core_fast1_ok$next \core_fast1_ok - assign \core_fast2$next \core_fast2 - assign \core_fast2_ok$next \core_fast2_ok - assign \core_fasto1$next \core_fasto1 - assign \fasto1_ok$next \fasto1_ok - assign \core_fasto2$next \core_fasto2 - assign \fasto2_ok$next \fasto2_ok - assign \core_cr_in1$next \core_cr_in1 - assign \core_cr_in1_ok$next \core_cr_in1_ok - assign \core_cr_in2$next \core_cr_in2 - assign \core_cr_in2_ok$next \core_cr_in2_ok - assign \core_cr_in2$1$next \core_cr_in2$1 - assign \core_cr_in2_ok$2$next \core_cr_in2_ok$2 - assign \core_cr_out$next \core_cr_out - assign \cr_out_ok$next \cr_out_ok - assign \core_msr$next \core_msr - assign \core_cia$next \core_cia - assign \core_insn$next \core_insn - assign \core_insn_type$next \core_insn_type - assign \core_fn_unit$next \core_fn_unit - assign \core_imm$next \core_imm - assign \core_imm_ok$next \core_imm_ok - assign \core_lk$next \core_lk - assign \core_rc$next \core_rc - assign \core_rc_ok$next \core_rc_ok - assign \core_oe$next \core_oe - assign \core_oe_ok$next \core_oe_ok - assign \core_invert_in$next \core_invert_in - assign \core_zero_a$next \core_zero_a - assign \core_input_carry$next \core_input_carry - assign \core_output_carry$next \core_output_carry - assign \core_input_cr$next \core_input_cr - assign \core_output_cr$next \core_output_cr - assign \core_invert_out$next \core_invert_out - assign \core_is_32bit$next \core_is_32bit - assign \core_is_signed$next \core_is_signed - assign \core_data_len$next \core_data_len - assign \core_byte_reverse$next \core_byte_reverse - assign \core_sign_extend$next \core_sign_extend - assign \core_ldst_mode$next \core_ldst_mode - assign \core_traptype$next \core_traptype - assign \core_trapaddr$next \core_trapaddr - assign \core_read_cr_whole$next \core_read_cr_whole - assign \core_write_cr_whole$next \core_write_cr_whole - assign \core_write_cr0$next \core_write_cr0 - attribute \src "simple/issuer.py:178" + assign \core_asmcode$next \core_asmcode + assign \core_core_rego$next \core_core_rego + assign \core_rego_ok$next \core_rego_ok + assign \core_core_ea$next \core_core_ea + assign \core_ea_ok$next \core_ea_ok + assign \core_core_reg1$next \core_core_reg1 + assign \core_core_reg1_ok$next \core_core_reg1_ok + assign \core_core_reg2$next \core_core_reg2 + assign \core_core_reg2_ok$next \core_core_reg2_ok + assign \core_core_reg3$next \core_core_reg3 + assign \core_core_reg3_ok$next \core_core_reg3_ok + assign \core_core_spro$next \core_core_spro + assign \core_spro_ok$next \core_spro_ok + assign \core_core_spr1$next \core_core_spr1 + assign \core_core_spr1_ok$next \core_core_spr1_ok + assign \core_core_xer_in$next \core_core_xer_in + assign \core_xer_out$next \core_xer_out + assign \core_core_fast1$next \core_core_fast1 + assign \core_core_fast1_ok$next \core_core_fast1_ok + assign \core_core_fast2$next \core_core_fast2 + assign \core_core_fast2_ok$next \core_core_fast2_ok + assign \core_core_fasto1$next \core_core_fasto1 + assign \core_fasto1_ok$next \core_fasto1_ok + assign \core_core_fasto2$next \core_core_fasto2 + assign \core_fasto2_ok$next \core_fasto2_ok + assign \core_core_cr_in1$next \core_core_cr_in1 + assign \core_core_cr_in1_ok$next \core_core_cr_in1_ok + assign \core_core_cr_in2$next \core_core_cr_in2 + assign \core_core_cr_in2_ok$next \core_core_cr_in2_ok + assign \core_core_cr_in2$1$next \core_core_cr_in2$1 + assign \core_core_cr_in2_ok$2$next \core_core_cr_in2_ok$2 + assign \core_core_cr_out$next \core_core_cr_out + assign \core_cr_out_ok$next \core_cr_out_ok + assign \core_core_core_msr$next \core_core_core_msr + assign \core_core_core_cia$next \core_core_core_cia + assign \core_core_core_insn$next \core_core_core_insn + assign \core_core_core_insn_type$next \core_core_core_insn_type + assign \core_core_core_fn_unit$next \core_core_core_fn_unit + assign \core_core_lk$next \core_core_lk + assign \core_core_core_rc$next \core_core_core_rc + assign \core_core_core_rc_ok$next \core_core_core_rc_ok + assign \core_core_core_oe$next \core_core_core_oe + assign \core_core_core_oe_ok$next \core_core_core_oe_ok + assign \core_core_core_input_carry$next \core_core_core_input_carry + assign \core_core_core_traptype$next \core_core_core_traptype + assign \core_core_core_trapaddr$next \core_core_core_trapaddr + assign \core_core_core_cr_rd$next \core_core_core_cr_rd + assign \core_core_core_cr_rd_ok$next \core_core_core_cr_rd_ok + assign \core_core_core_cr_wr$next \core_core_core_cr_wr + assign \core_core_cr_wr_ok$next \core_core_cr_wr_ok + assign \core_core_core_is_32bit$next \core_core_core_is_32bit + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - assign { \core_write_cr0$next \core_write_cr_whole$next \core_read_cr_whole$next \core_trapaddr$next \core_traptype$next \core_ldst_mode$next \core_sign_extend$next \core_byte_reverse$next \core_data_len$next \core_is_signed$next \core_is_32bit$next \core_invert_out$next \core_output_cr$next \core_input_cr$next \core_output_carry$next \core_input_carry$next \core_zero_a$next \core_invert_in$next \core_oe_ok$next \core_oe$next \core_rc_ok$next \core_rc$next \core_lk$next \core_imm_ok$next \core_imm$next \core_fn_unit$next \core_insn_type$next \core_insn$next \core_cia$next \core_msr$next { \cr_out_ok$next \core_cr_out$next } { \core_cr_in2_ok$2$next \core_cr_in2$1$next } { \core_cr_in2_ok$next \core_cr_in2$next } { \core_cr_in1_ok$next \core_cr_in1$next } { \fasto2_ok$next \core_fasto2$next } { \fasto1_ok$next \core_fasto1$next } { \core_fast2_ok$next \core_fast2$next } { \core_fast1_ok$next \core_fast1$next } \xer_out$next \core_xer_in$next { \core_spr1_ok$next \core_spr1$next } { \spro_ok$next \core_spro$next } { \core_reg3_ok$next \core_reg3$next } { \core_reg2_ok$next \core_reg2$next } { \core_reg1_ok$next \core_reg1$next } { \ea_ok$next \core_ea$next } { \rego_ok$next \core_rego$next } \asmcode$next } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:203" + assign { \core_core_core_is_32bit$next \core_core_cr_wr_ok$next \core_core_core_cr_wr$next \core_core_core_cr_rd_ok$next \core_core_core_cr_rd$next \core_core_core_trapaddr$next \core_core_core_traptype$next \core_core_core_input_carry$next \core_core_core_oe_ok$next \core_core_core_oe$next \core_core_core_rc_ok$next \core_core_core_rc$next \core_core_lk$next \core_core_core_fn_unit$next \core_core_core_insn_type$next \core_core_core_insn$next \core_core_core_cia$next \core_core_core_msr$next { \core_cr_out_ok$next \core_core_cr_out$next } { \core_core_cr_in2_ok$2$next \core_core_cr_in2$1$next } { \core_core_cr_in2_ok$next \core_core_cr_in2$next } { \core_core_cr_in1_ok$next \core_core_cr_in1$next } { \core_fasto2_ok$next \core_core_fasto2$next } { \core_fasto1_ok$next \core_core_fasto1$next } { \core_core_fast2_ok$next \core_core_fast2$next } { \core_core_fast1_ok$next \core_core_fast1$next } \core_xer_out$next \core_core_xer_in$next { \core_core_spr1_ok$next \core_core_spr1$next } { \core_spro_ok$next \core_core_spro$next } { \core_core_reg3_ok$next \core_core_reg3$next } { \core_core_reg2_ok$next \core_core_reg2$next } { \core_core_reg1_ok$next \core_core_reg1$next } { \core_ea_ok$next \core_core_ea$next } { \core_rego_ok$next \core_core_rego$next } \core_asmcode$next } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case - assign { \core_write_cr0$next \core_write_cr_whole$next \core_read_cr_whole$next \core_trapaddr$next \core_traptype$next \core_ldst_mode$next \core_sign_extend$next \core_byte_reverse$next \core_data_len$next \core_is_signed$next \core_is_32bit$next \core_invert_out$next \core_output_cr$next \core_input_cr$next \core_output_carry$next \core_input_carry$next \core_zero_a$next \core_invert_in$next \core_oe_ok$next \core_oe$next \core_rc_ok$next \core_rc$next \core_lk$next \core_imm_ok$next \core_imm$next \core_fn_unit$next \core_insn_type$next \core_insn$next \core_cia$next \core_msr$next { \cr_out_ok$next \core_cr_out$next } { \core_cr_in2_ok$2$next \core_cr_in2$1$next } { \core_cr_in2_ok$next \core_cr_in2$next } { \core_cr_in1_ok$next \core_cr_in1$next } { \fasto2_ok$next \core_fasto2$next } { \fasto1_ok$next \core_fasto1$next } { \core_fast2_ok$next \core_fast2$next } { \core_fast1_ok$next \core_fast1$next } \xer_out$next \core_xer_in$next { \core_spr1_ok$next \core_spr1$next } { \spro_ok$next \core_spro$next } { \core_reg3_ok$next \core_reg3$next } { \core_reg2_ok$next \core_reg2$next } { \core_reg1_ok$next \core_reg1$next } { \ea_ok$next \core_ea$next } { \rego_ok$next \core_rego$next } \asmcode$next } { \dec2_write_cr0 \dec2_write_cr_whole \dec2_read_cr_whole \dec2_trapaddr \dec2_traptype \dec2_ldst_mode \dec2_sign_extend \dec2_byte_reverse \dec2_data_len \dec2_is_signed \dec2_is_32bit \dec2_invert_out \dec2_output_cr \dec2_input_cr \dec2_output_carry \dec2_input_carry \dec2_zero_a \dec2_invert_in \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_imm_ok \dec2_imm \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr { \dec2_cr_out_ok \dec2_cr_out } { \dec2_cr_in2_ok$4 \dec2_cr_in2$3 } { \dec2_cr_in2_ok \dec2_cr_in2 } { \dec2_cr_in1_ok \dec2_cr_in1 } { \dec2_fasto2_ok \dec2_fasto2 } { \dec2_fasto1_ok \dec2_fasto1 } { \dec2_fast2_ok \dec2_fast2 } { \dec2_fast1_ok \dec2_fast1 } \dec2_xer_out \dec2_xer_in { \dec2_spr1_ok \dec2_spr1 } { \dec2_spro_ok \dec2_spro } { \dec2_reg3_ok \dec2_reg3 } { \dec2_reg2_ok \dec2_reg2 } { \dec2_reg1_ok \dec2_reg1 } { \dec2_ea_ok \dec2_ea } { \dec2_rego_ok \dec2_rego } \dec2_asmcode } + assign { \core_core_core_is_32bit$next \core_core_cr_wr_ok$next \core_core_core_cr_wr$next \core_core_core_cr_rd_ok$next \core_core_core_cr_rd$next \core_core_core_trapaddr$next \core_core_core_traptype$next \core_core_core_input_carry$next \core_core_core_oe_ok$next \core_core_core_oe$next \core_core_core_rc_ok$next \core_core_core_rc$next \core_core_lk$next \core_core_core_fn_unit$next \core_core_core_insn_type$next \core_core_core_insn$next \core_core_core_cia$next \core_core_core_msr$next { \core_cr_out_ok$next \core_core_cr_out$next } { \core_core_cr_in2_ok$2$next \core_core_cr_in2$1$next } { \core_core_cr_in2_ok$next \core_core_cr_in2$next } { \core_core_cr_in1_ok$next \core_core_cr_in1$next } { \core_fasto2_ok$next \core_core_fasto2$next } { \core_fasto1_ok$next \core_core_fasto1$next } { \core_core_fast2_ok$next \core_core_fast2$next } { \core_core_fast1_ok$next \core_core_fast1$next } \core_xer_out$next \core_core_xer_in$next { \core_core_spr1_ok$next \core_core_spr1$next } { \core_spro_ok$next \core_core_spro$next } { \core_core_reg3_ok$next \core_core_reg3$next } { \core_core_reg2_ok$next \core_core_reg2$next } { \core_core_reg1_ok$next \core_core_reg1$next } { \core_ea_ok$next \core_core_ea$next } { \core_rego_ok$next \core_core_rego$next } \core_asmcode$next } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr { \dec2_cr_out_ok \dec2_cr_out } { \dec2_cr_in2_ok$6 \dec2_cr_in2$5 } { \dec2_cr_in2_ok \dec2_cr_in2 } { \dec2_cr_in1_ok \dec2_cr_in1 } { \dec2_fasto2_ok \dec2_fasto2 } { \dec2_fasto1_ok \dec2_fasto1 } { \dec2_fast2_ok \dec2_fast2 } { \dec2_fast1_ok \dec2_fast1 } \dec2_xer_out \dec2_xer_in { \dec2_spr1_ok \dec2_spr1 } { \dec2_spro_ok \dec2_spro } { \dec2_reg3_ok \dec2_reg3 } { \dec2_reg2_ok \dec2_reg2 } { \dec2_reg1_ok \dec2_reg1 } { \dec2_ea_ok \dec2_ea } { \dec2_rego_ok \dec2_rego } \dec2_asmcode } end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 - attribute \src "simple/issuer.py:238" - switch { $39 } - attribute \src "simple/issuer.py:238" + attribute \src "simple/issuer.py:280" + switch { $43 } + attribute \src "simple/issuer.py:280" case 1'1 - assign { \core_write_cr0$next \core_write_cr_whole$next \core_read_cr_whole$next \core_trapaddr$next \core_traptype$next \core_ldst_mode$next \core_sign_extend$next \core_byte_reverse$next \core_data_len$next \core_is_signed$next \core_is_32bit$next \core_invert_out$next \core_output_cr$next \core_input_cr$next \core_output_carry$next \core_input_carry$next \core_zero_a$next \core_invert_in$next \core_oe_ok$next \core_oe$next \core_rc_ok$next \core_rc$next \core_lk$next \core_imm_ok$next \core_imm$next \core_fn_unit$next \core_insn_type$next \core_insn$next \core_cia$next \core_msr$next { \cr_out_ok$next \core_cr_out$next } { \core_cr_in2_ok$2$next \core_cr_in2$1$next } { \core_cr_in2_ok$next \core_cr_in2$next } { \core_cr_in1_ok$next \core_cr_in1$next } { \fasto2_ok$next \core_fasto2$next } { \fasto1_ok$next \core_fasto1$next } { \core_fast2_ok$next \core_fast2$next } { \core_fast1_ok$next \core_fast1$next } \xer_out$next \core_xer_in$next { \core_spr1_ok$next \core_spr1$next } { \spro_ok$next \core_spro$next } { \core_reg3_ok$next \core_reg3$next } { \core_reg2_ok$next \core_reg2$next } { \core_reg1_ok$next \core_reg1$next } { \ea_ok$next \core_ea$next } { \rego_ok$next \core_rego$next } \asmcode$next } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { \core_core_core_is_32bit$next \core_core_cr_wr_ok$next \core_core_core_cr_wr$next \core_core_core_cr_rd_ok$next \core_core_core_cr_rd$next \core_core_core_trapaddr$next \core_core_core_traptype$next \core_core_core_input_carry$next \core_core_core_oe_ok$next \core_core_core_oe$next \core_core_core_rc_ok$next \core_core_core_rc$next \core_core_lk$next \core_core_core_fn_unit$next \core_core_core_insn_type$next \core_core_core_insn$next \core_core_core_cia$next \core_core_core_msr$next { \core_cr_out_ok$next \core_core_cr_out$next } { \core_core_cr_in2_ok$2$next \core_core_cr_in2$1$next } { \core_core_cr_in2_ok$next \core_core_cr_in2$next } { \core_core_cr_in1_ok$next \core_core_cr_in1$next } { \core_fasto2_ok$next \core_core_fasto2$next } { \core_fasto1_ok$next \core_core_fasto1$next } { \core_core_fast2_ok$next \core_core_fast2$next } { \core_core_fast1_ok$next \core_core_fast1$next } \core_xer_out$next \core_core_xer_in$next { \core_core_spr1_ok$next \core_core_spr1$next } { \core_spro_ok$next \core_core_spro$next } { \core_core_reg3_ok$next \core_core_reg3$next } { \core_core_reg2_ok$next \core_core_reg2$next } { \core_core_reg1_ok$next \core_core_reg1$next } { \core_ea_ok$next \core_core_ea$next } { \core_rego_ok$next \core_core_rego$next } \core_asmcode$next } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \rego_ok$next 1'0 - assign \ea_ok$next 1'0 - assign \core_reg1_ok$next 1'0 - assign \core_reg2_ok$next 1'0 - assign \core_reg3_ok$next 1'0 - assign \spro_ok$next 1'0 - assign \core_spr1_ok$next 1'0 - assign \core_fast1_ok$next 1'0 - assign \core_fast2_ok$next 1'0 - assign \fasto1_ok$next 1'0 - assign \fasto2_ok$next 1'0 - assign \core_cr_in1_ok$next 1'0 - assign \core_cr_in2_ok$next 1'0 - assign \core_cr_in2_ok$2$next 1'0 - assign \cr_out_ok$next 1'0 - assign \core_imm_ok$next 1'0 - assign \core_rc_ok$next 1'0 - assign \core_oe_ok$next 1'0 - end - sync init - update \asmcode 8'00000000 - update \core_rego 5'00000 - update \rego_ok 1'0 - update \core_ea 5'00000 - update \ea_ok 1'0 - update \core_reg1 5'00000 - update \core_reg1_ok 1'0 - update \core_reg2 5'00000 - update \core_reg2_ok 1'0 - update \core_reg3 5'00000 - update \core_reg3_ok 1'0 - update \core_spro 10'0000000000 - update \spro_ok 1'0 - update \core_spr1 10'0000000000 - update \core_spr1_ok 1'0 - update \core_xer_in 1'0 - update \xer_out 1'0 - update \core_fast1 3'000 - update \core_fast1_ok 1'0 - update \core_fast2 3'000 - update \core_fast2_ok 1'0 - update \core_fasto1 3'000 - update \fasto1_ok 1'0 - update \core_fasto2 3'000 - update \fasto2_ok 1'0 - update \core_cr_in1 3'000 - update \core_cr_in1_ok 1'0 - update \core_cr_in2 3'000 - update \core_cr_in2_ok 1'0 - update \core_cr_in2$1 3'000 - update \core_cr_in2_ok$2 1'0 - update \core_cr_out 3'000 - update \cr_out_ok 1'0 - update \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_cia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_insn 32'00000000000000000000000000000000 - update \core_insn_type 7'0000000 - update \core_fn_unit 11'00000000000 - update \core_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_imm_ok 1'0 - update \core_lk 1'0 - update \core_rc 1'0 - update \core_rc_ok 1'0 - update \core_oe 1'0 - update \core_oe_ok 1'0 - update \core_invert_in 1'0 - update \core_zero_a 1'0 - update \core_input_carry 2'00 - update \core_output_carry 1'0 - update \core_input_cr 1'0 - update \core_output_cr 1'0 - update \core_invert_out 1'0 - update \core_is_32bit 1'0 - update \core_is_signed 1'0 - update \core_data_len 4'0000 - update \core_byte_reverse 1'0 - update \core_sign_extend 1'0 - update \core_ldst_mode 2'00 - update \core_traptype 5'00000 - update \core_trapaddr 13'0000000000000 - update \core_read_cr_whole 1'0 - update \core_write_cr_whole 1'0 - update \core_write_cr0 1'0 + assign \core_rego_ok$next 1'0 + assign \core_ea_ok$next 1'0 + assign \core_core_reg1_ok$next 1'0 + assign \core_core_reg2_ok$next 1'0 + assign \core_core_reg3_ok$next 1'0 + assign \core_spro_ok$next 1'0 + assign \core_core_spr1_ok$next 1'0 + assign \core_core_fast1_ok$next 1'0 + assign \core_core_fast2_ok$next 1'0 + assign \core_fasto1_ok$next 1'0 + assign \core_fasto2_ok$next 1'0 + assign \core_core_cr_in1_ok$next 1'0 + assign \core_core_cr_in2_ok$next 1'0 + assign \core_core_cr_in2_ok$2$next 1'0 + assign \core_cr_out_ok$next 1'0 + assign \core_core_core_rc_ok$next 1'0 + assign \core_core_core_oe_ok$next 1'0 + assign \core_core_core_cr_rd_ok$next 1'0 + assign \core_core_cr_wr_ok$next 1'0 + end + sync init + update \core_asmcode 8'00000000 + update \core_core_rego 5'00000 + update \core_rego_ok 1'0 + update \core_core_ea 5'00000 + update \core_ea_ok 1'0 + update \core_core_reg1 5'00000 + update \core_core_reg1_ok 1'0 + update \core_core_reg2 5'00000 + update \core_core_reg2_ok 1'0 + update \core_core_reg3 5'00000 + update \core_core_reg3_ok 1'0 + update \core_core_spro 10'0000000000 + update \core_spro_ok 1'0 + update \core_core_spr1 10'0000000000 + update \core_core_spr1_ok 1'0 + update \core_core_xer_in 3'000 + update \core_xer_out 1'0 + update \core_core_fast1 3'000 + update \core_core_fast1_ok 1'0 + update \core_core_fast2 3'000 + update \core_core_fast2_ok 1'0 + update \core_core_fasto1 3'000 + update \core_fasto1_ok 1'0 + update \core_core_fasto2 3'000 + update \core_fasto2_ok 1'0 + update \core_core_cr_in1 3'000 + update \core_core_cr_in1_ok 1'0 + update \core_core_cr_in2 3'000 + update \core_core_cr_in2_ok 1'0 + update \core_core_cr_in2$1 3'000 + update \core_core_cr_in2_ok$2 1'0 + update \core_core_cr_out 3'000 + update \core_cr_out_ok 1'0 + update \core_core_core_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_core_core_cia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_core_core_insn 32'00000000000000000000000000000000 + update \core_core_core_insn_type 7'0000000 + update \core_core_core_fn_unit 11'00000000000 + update \core_core_lk 1'0 + update \core_core_core_rc 1'0 + update \core_core_core_rc_ok 1'0 + update \core_core_core_oe 1'0 + update \core_core_core_oe_ok 1'0 + update \core_core_core_input_carry 2'00 + update \core_core_core_traptype 7'0000000 + update \core_core_core_trapaddr 13'0000000000000 + update \core_core_core_cr_rd 8'00000000 + update \core_core_core_cr_rd_ok 1'0 + update \core_core_core_cr_wr 8'00000000 + update \core_core_cr_wr_ok 1'0 + update \core_core_core_is_32bit 1'0 sync posedge \clk - update \asmcode \asmcode$next - update \core_rego \core_rego$next - update \rego_ok \rego_ok$next - update \core_ea \core_ea$next - update \ea_ok \ea_ok$next - update \core_reg1 \core_reg1$next - update \core_reg1_ok \core_reg1_ok$next - update \core_reg2 \core_reg2$next - update \core_reg2_ok \core_reg2_ok$next - update \core_reg3 \core_reg3$next - update \core_reg3_ok \core_reg3_ok$next - update \core_spro \core_spro$next - update \spro_ok \spro_ok$next - update \core_spr1 \core_spr1$next - update \core_spr1_ok \core_spr1_ok$next - update \core_xer_in \core_xer_in$next - update \xer_out \xer_out$next - update \core_fast1 \core_fast1$next - update \core_fast1_ok \core_fast1_ok$next - update \core_fast2 \core_fast2$next - update \core_fast2_ok \core_fast2_ok$next - update \core_fasto1 \core_fasto1$next - update \fasto1_ok \fasto1_ok$next - update \core_fasto2 \core_fasto2$next - update \fasto2_ok \fasto2_ok$next - update \core_cr_in1 \core_cr_in1$next - update \core_cr_in1_ok \core_cr_in1_ok$next - update \core_cr_in2 \core_cr_in2$next - update \core_cr_in2_ok \core_cr_in2_ok$next - update \core_cr_in2$1 \core_cr_in2$1$next - update \core_cr_in2_ok$2 \core_cr_in2_ok$2$next - update \core_cr_out \core_cr_out$next - update \cr_out_ok \cr_out_ok$next - update \core_msr \core_msr$next - update \core_cia \core_cia$next - update \core_insn \core_insn$next - update \core_insn_type \core_insn_type$next - update \core_fn_unit \core_fn_unit$next - update \core_imm \core_imm$next - update \core_imm_ok \core_imm_ok$next - update \core_lk \core_lk$next - update \core_rc \core_rc$next - update \core_rc_ok \core_rc_ok$next - update \core_oe \core_oe$next - update \core_oe_ok \core_oe_ok$next - update \core_invert_in \core_invert_in$next - update \core_zero_a \core_zero_a$next - update \core_input_carry \core_input_carry$next - update \core_output_carry \core_output_carry$next - update \core_input_cr \core_input_cr$next - update \core_output_cr \core_output_cr$next - update \core_invert_out \core_invert_out$next - update \core_is_32bit \core_is_32bit$next - update \core_is_signed \core_is_signed$next - update \core_data_len \core_data_len$next - update \core_byte_reverse \core_byte_reverse$next - update \core_sign_extend \core_sign_extend$next - update \core_ldst_mode \core_ldst_mode$next - update \core_traptype \core_traptype$next - update \core_trapaddr \core_trapaddr$next - update \core_read_cr_whole \core_read_cr_whole$next - update \core_write_cr_whole \core_write_cr_whole$next - update \core_write_cr0 \core_write_cr0$next - end - attribute \src "simple/issuer.py:184" - wire width 1 $41 - attribute \src "simple/issuer.py:184" - cell $not $42 + update \core_asmcode \core_asmcode$next + update \core_core_rego \core_core_rego$next + update \core_rego_ok \core_rego_ok$next + update \core_core_ea \core_core_ea$next + update \core_ea_ok \core_ea_ok$next + update \core_core_reg1 \core_core_reg1$next + update \core_core_reg1_ok \core_core_reg1_ok$next + update \core_core_reg2 \core_core_reg2$next + update \core_core_reg2_ok \core_core_reg2_ok$next + update \core_core_reg3 \core_core_reg3$next + update \core_core_reg3_ok \core_core_reg3_ok$next + update \core_core_spro \core_core_spro$next + update \core_spro_ok \core_spro_ok$next + update \core_core_spr1 \core_core_spr1$next + update \core_core_spr1_ok \core_core_spr1_ok$next + update \core_core_xer_in \core_core_xer_in$next + update \core_xer_out \core_xer_out$next + update \core_core_fast1 \core_core_fast1$next + update \core_core_fast1_ok \core_core_fast1_ok$next + update \core_core_fast2 \core_core_fast2$next + update \core_core_fast2_ok \core_core_fast2_ok$next + update \core_core_fasto1 \core_core_fasto1$next + update \core_fasto1_ok \core_fasto1_ok$next + update \core_core_fasto2 \core_core_fasto2$next + update \core_fasto2_ok \core_fasto2_ok$next + update \core_core_cr_in1 \core_core_cr_in1$next + update \core_core_cr_in1_ok \core_core_cr_in1_ok$next + update \core_core_cr_in2 \core_core_cr_in2$next + update \core_core_cr_in2_ok \core_core_cr_in2_ok$next + update \core_core_cr_in2$1 \core_core_cr_in2$1$next + update \core_core_cr_in2_ok$2 \core_core_cr_in2_ok$2$next + update \core_core_cr_out \core_core_cr_out$next + update \core_cr_out_ok \core_cr_out_ok$next + update \core_core_core_msr \core_core_core_msr$next + update \core_core_core_cia \core_core_core_cia$next + update \core_core_core_insn \core_core_core_insn$next + update \core_core_core_insn_type \core_core_core_insn_type$next + update \core_core_core_fn_unit \core_core_core_fn_unit$next + update \core_core_lk \core_core_lk$next + update \core_core_core_rc \core_core_core_rc$next + update \core_core_core_rc_ok \core_core_core_rc_ok$next + update \core_core_core_oe \core_core_core_oe$next + update \core_core_core_oe_ok \core_core_core_oe_ok$next + update \core_core_core_input_carry \core_core_core_input_carry$next + update \core_core_core_traptype \core_core_core_traptype$next + update \core_core_core_trapaddr \core_core_core_trapaddr$next + update \core_core_core_cr_rd \core_core_core_cr_rd$next + update \core_core_core_cr_rd_ok \core_core_core_cr_rd_ok$next + update \core_core_core_cr_wr \core_core_core_cr_wr$next + update \core_core_cr_wr_ok \core_core_cr_wr_ok$next + update \core_core_core_is_32bit \core_core_core_is_32bit$next + end + attribute \src "simple/issuer.py:280" + wire width 1 $45 + attribute \src "simple/issuer.py:280" + cell $not $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $45 + end + process $group_73 + assign \core_raw_insn_i$next \core_raw_insn_i + attribute \src "simple/issuer.py:214" + switch \fsm_state + attribute \src "simple/issuer.py:217" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + assign \core_raw_insn_i$next 32'00000000000000000000000000000000 + attribute \src "simple/issuer.py:242" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:247" + switch { \imem_f_busy_o } + attribute \src "simple/issuer.py:247" + case 1'1 + attribute \src "simple/issuer.py:251" + case + assign \core_raw_insn_i$next \dec2_raw_opcode_in + end + attribute \src "simple/issuer.py:268" + attribute \nmigen.decoding "INSN_START/2" + case 2'10 + attribute \src "simple/issuer.py:275" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:280" + switch { $45 } + attribute \src "simple/issuer.py:280" + case 1'1 + assign \core_raw_insn_i$next 32'00000000000000000000000000000000 + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \core_raw_insn_i$next 32'00000000000000000000000000000000 + end + sync init + update \core_raw_insn_i 32'00000000000000000000000000000000 + sync posedge \clk + update \core_raw_insn_i \core_raw_insn_i$next + end + attribute \src "simple/issuer.py:280" + wire width 1 $47 + attribute \src "simple/issuer.py:280" + cell $not $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $47 + end + process $group_74 + assign \core_bigendian_i$3$next \core_bigendian_i$3 + attribute \src "simple/issuer.py:214" + switch \fsm_state + attribute \src "simple/issuer.py:217" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + assign \core_bigendian_i$3$next 1'0 + attribute \src "simple/issuer.py:242" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:247" + switch { \imem_f_busy_o } + attribute \src "simple/issuer.py:247" + case 1'1 + attribute \src "simple/issuer.py:251" + case + assign \core_bigendian_i$3$next \core_bigendian_i + end + attribute \src "simple/issuer.py:268" + attribute \nmigen.decoding "INSN_START/2" + case 2'10 + attribute \src "simple/issuer.py:275" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:280" + switch { $47 } + attribute \src "simple/issuer.py:280" + case 1'1 + assign \core_bigendian_i$3$next 1'0 + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \core_bigendian_i$3$next 1'0 + end + sync init + update \core_bigendian_i$3 1'0 + sync posedge \clk + update \core_bigendian_i$3 \core_bigendian_i$3$next + end + attribute \src "simple/issuer.py:222" + wire width 1 $49 + attribute \src "simple/issuer.py:222" + cell $not $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $41 + connect \Y $49 end - attribute \src "simple/issuer.py:184" - wire width 1 $43 - attribute \src "simple/issuer.py:184" - cell $not $44 + attribute \src "simple/issuer.py:222" + wire width 1 $51 + attribute \src "simple/issuer.py:222" + cell $not $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $43 + connect \Y $51 end - attribute \src "simple/issuer.py:184" - wire width 1 $45 - attribute \src "simple/issuer.py:184" - cell $and $46 + attribute \src "simple/issuer.py:222" + wire width 1 $53 + attribute \src "simple/issuer.py:222" + cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $41 - connect \B $43 - connect \Y $45 + connect \A $49 + connect \B $51 + connect \Y $53 end - process $group_85 + process $group_75 assign \imem_a_pc_i 48'000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $45 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $53 } + attribute \src "simple/issuer.py:222" case 1'1 assign \imem_a_pc_i \pc [47:0] - attribute \src "simple/issuer.py:198" + attribute \src "simple/issuer.py:237" case end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - attribute \src "simple/issuer.py:184" - wire width 1 $47 - attribute \src "simple/issuer.py:184" - cell $not $48 + attribute \src "simple/issuer.py:222" + wire width 1 $55 + attribute \src "simple/issuer.py:222" + cell $not $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $47 + connect \Y $55 end - attribute \src "simple/issuer.py:184" - wire width 1 $49 - attribute \src "simple/issuer.py:184" - cell $not $50 + attribute \src "simple/issuer.py:222" + wire width 1 $57 + attribute \src "simple/issuer.py:222" + cell $not $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $49 + connect \Y $57 end - attribute \src "simple/issuer.py:184" - wire width 1 $51 - attribute \src "simple/issuer.py:184" - cell $and $52 + attribute \src "simple/issuer.py:222" + wire width 1 $59 + attribute \src "simple/issuer.py:222" + cell $and $60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $47 - connect \B $49 - connect \Y $51 + connect \A $55 + connect \B $57 + connect \Y $59 end - process $group_86 + process $group_76 assign \imem_a_valid_i 1'0 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $51 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $59 } + attribute \src "simple/issuer.py:222" case 1'1 assign \imem_a_valid_i 1'1 - attribute \src "simple/issuer.py:198" + attribute \src "simple/issuer.py:237" case end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 assign \imem_a_valid_i 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - attribute \src "simple/issuer.py:184" - wire width 1 $53 - attribute \src "simple/issuer.py:184" - cell $not $54 + attribute \src "simple/issuer.py:222" + wire width 1 $61 + attribute \src "simple/issuer.py:222" + cell $not $62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $53 + connect \Y $61 end - attribute \src "simple/issuer.py:184" - wire width 1 $55 - attribute \src "simple/issuer.py:184" - cell $not $56 + attribute \src "simple/issuer.py:222" + wire width 1 $63 + attribute \src "simple/issuer.py:222" + cell $not $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $55 + connect \Y $63 end - attribute \src "simple/issuer.py:184" - wire width 1 $57 - attribute \src "simple/issuer.py:184" - cell $and $58 + attribute \src "simple/issuer.py:222" + wire width 1 $65 + attribute \src "simple/issuer.py:222" + cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $53 - connect \B $55 - connect \Y $57 + connect \A $61 + connect \B $63 + connect \Y $65 end - process $group_87 + process $group_77 assign \imem_f_valid_i 1'0 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $57 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $65 } + attribute \src "simple/issuer.py:222" case 1'1 assign \imem_f_valid_i 1'1 - attribute \src "simple/issuer.py:198" + attribute \src "simple/issuer.py:237" case end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 assign \imem_f_valid_i 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - attribute \src "simple/issuer.py:184" - wire width 1 $59 - attribute \src "simple/issuer.py:184" - cell $not $60 + attribute \src "simple/issuer.py:222" + wire width 1 $67 + attribute \src "simple/issuer.py:222" + cell $not $68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $59 + connect \Y $67 end - attribute \src "simple/issuer.py:184" - wire width 1 $61 - attribute \src "simple/issuer.py:184" - cell $not $62 + attribute \src "simple/issuer.py:222" + wire width 1 $69 + attribute \src "simple/issuer.py:222" + cell $not $70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $61 + connect \Y $69 end - attribute \src "simple/issuer.py:184" - wire width 1 $63 - attribute \src "simple/issuer.py:184" - cell $and $64 + attribute \src "simple/issuer.py:222" + wire width 1 $71 + attribute \src "simple/issuer.py:222" + cell $and $72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $59 - connect \B $61 - connect \Y $63 + connect \A $67 + connect \B $69 + connect \Y $71 end - process $group_88 - assign \cur_pc$next \cur_pc - attribute \src "simple/issuer.py:178" + process $group_78 + assign \dec2_cur_pc$next \dec2_cur_pc + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $63 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $71 } + attribute \src "simple/issuer.py:222" case 1'1 - assign \cur_pc$next \pc - attribute \src "simple/issuer.py:198" + assign \dec2_cur_pc$next \pc + attribute \src "simple/issuer.py:237" case end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \cur_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \dec2_cur_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \cur_pc 64'0000000000000000000000000000000000000000000000000000000000000000 + update \dec2_cur_pc 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \cur_pc \cur_pc$next + update \dec2_cur_pc \dec2_cur_pc$next end - attribute \src "simple/issuer.py:184" - wire width 1 $65 - attribute \src "simple/issuer.py:184" - cell $not $66 + attribute \src "simple/issuer.py:192" + wire width 1 \msr_read + attribute \src "simple/issuer.py:192" + wire width 1 \msr_read$next + attribute \src "simple/issuer.py:222" + wire width 1 $73 + attribute \src "simple/issuer.py:222" + cell $not $74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $65 + connect \Y $73 end - attribute \src "simple/issuer.py:184" - wire width 1 $67 - attribute \src "simple/issuer.py:184" - cell $not $68 + attribute \src "simple/issuer.py:222" + wire width 1 $75 + attribute \src "simple/issuer.py:222" + cell $not $76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $67 + connect \Y $75 end - attribute \src "simple/issuer.py:184" - wire width 1 $69 - attribute \src "simple/issuer.py:184" - cell $and $70 + attribute \src "simple/issuer.py:222" + wire width 1 $77 + attribute \src "simple/issuer.py:222" + cell $and $78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $65 - connect \B $67 - connect \Y $69 + connect \A $73 + connect \B $75 + connect \Y $77 end - attribute \src "simple/issuer.py:238" - wire width 1 $71 - attribute \src "simple/issuer.py:238" - cell $not $72 + attribute \src "simple/issuer.py:244" + wire width 1 $79 + attribute \src "simple/issuer.py:244" + cell $not $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $79 + end + process $group_79 + assign \msr_read$next \msr_read + attribute \src "simple/issuer.py:214" + switch \fsm_state + attribute \src "simple/issuer.py:217" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + attribute \src "simple/issuer.py:222" + switch { $77 } + attribute \src "simple/issuer.py:222" + case 1'1 + assign \msr_read$next 1'0 + attribute \src "simple/issuer.py:237" + case + end + attribute \src "simple/issuer.py:242" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:244" + switch { $79 } + attribute \src "simple/issuer.py:244" + case 1'1 + assign \msr_read$next 1'1 + end + attribute \src "simple/issuer.py:268" + attribute \nmigen.decoding "INSN_START/2" + case 2'10 + attribute \src "simple/issuer.py:275" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \msr_read$next 1'1 + end + sync init + update \msr_read 1'1 + sync posedge \clk + update \msr_read \msr_read$next + end + attribute \src "simple/issuer.py:222" + wire width 1 $81 + attribute \src "simple/issuer.py:222" + cell $not $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $81 + end + attribute \src "simple/issuer.py:222" + wire width 1 $83 + attribute \src "simple/issuer.py:222" + cell $not $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $83 + end + attribute \src "simple/issuer.py:222" + wire width 1 $85 + attribute \src "simple/issuer.py:222" + cell $and $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $81 + connect \B $83 + connect \Y $85 + end + attribute \src "simple/issuer.py:280" + wire width 1 $87 + attribute \src "simple/issuer.py:280" + cell $not $88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $71 + connect \Y $87 end - process $group_89 + process $group_80 assign \fsm_state$next \fsm_state - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $69 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $85 } + attribute \src "simple/issuer.py:222" case 1'1 assign \fsm_state$next 2'01 - attribute \src "simple/issuer.py:198" + attribute \src "simple/issuer.py:237" case end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case assign \fsm_state$next 2'10 end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 assign \fsm_state$next 2'11 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 - attribute \src "simple/issuer.py:238" - switch { $71 } - attribute \src "simple/issuer.py:238" + attribute \src "simple/issuer.py:280" + switch { $87 } + attribute \src "simple/issuer.py:280" case 1'1 assign \fsm_state$next 2'00 end @@ -167001,289 +277286,335 @@ module \test_issuer sync posedge \clk update \fsm_state \fsm_state$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:96" wire width 1 \core_stopped_i - attribute \src "simple/issuer.py:184" - wire width 1 $73 - attribute \src "simple/issuer.py:184" - cell $not $74 + attribute \src "simple/issuer.py:222" + wire width 1 $89 + attribute \src "simple/issuer.py:222" + cell $not $90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $73 + connect \Y $89 end - attribute \src "simple/issuer.py:184" - wire width 1 $75 - attribute \src "simple/issuer.py:184" - cell $not $76 + attribute \src "simple/issuer.py:222" + wire width 1 $91 + attribute \src "simple/issuer.py:222" + cell $not $92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $75 + connect \Y $91 end - attribute \src "simple/issuer.py:184" - wire width 1 $77 - attribute \src "simple/issuer.py:184" - cell $and $78 + attribute \src "simple/issuer.py:222" + wire width 1 $93 + attribute \src "simple/issuer.py:222" + cell $and $94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $73 - connect \B $75 - connect \Y $77 + connect \A $89 + connect \B $91 + connect \Y $93 end - process $group_90 + process $group_81 assign \core_stopped_i 1'0 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $77 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $93 } + attribute \src "simple/issuer.py:222" case 1'1 - attribute \src "simple/issuer.py:198" + attribute \src "simple/issuer.py:237" case assign \core_stopped_i 1'1 end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - attribute \src "simple/issuer.py:184" - wire width 1 $79 - attribute \src "simple/issuer.py:184" - cell $not $80 + attribute \src "simple/issuer.py:222" + wire width 1 $95 + attribute \src "simple/issuer.py:222" + cell $not $96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $79 + connect \Y $95 end - attribute \src "simple/issuer.py:184" - wire width 1 $81 - attribute \src "simple/issuer.py:184" - cell $not $82 + attribute \src "simple/issuer.py:222" + wire width 1 $97 + attribute \src "simple/issuer.py:222" + cell $not $98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_reset_i - connect \Y $81 + connect \Y $97 end - attribute \src "simple/issuer.py:184" - wire width 1 $83 - attribute \src "simple/issuer.py:184" - cell $and $84 + attribute \src "simple/issuer.py:222" + wire width 1 $99 + attribute \src "simple/issuer.py:222" + cell $and $100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $79 - connect \B $81 - connect \Y $83 + connect \A $95 + connect \B $97 + connect \Y $99 end - process $group_91 + process $group_82 assign \dbg_core_stopped_i 1'0 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:184" - switch { $83 } - attribute \src "simple/issuer.py:184" + attribute \src "simple/issuer.py:222" + switch { $99 } + attribute \src "simple/issuer.py:222" case 1'1 - attribute \src "simple/issuer.py:198" + attribute \src "simple/issuer.py:237" case assign \dbg_core_stopped_i 1'1 end - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - process $group_92 - assign \cur_msr$next \cur_msr - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:244" + wire width 1 $101 + attribute \src "simple/issuer.py:244" + cell $not $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $101 + end + process $group_83 + assign \dec2_cur_msr$next \dec2_cur_msr + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - assign \cur_msr$next \core_msr__data_o - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:244" + switch { $101 } + attribute \src "simple/issuer.py:244" + case 1'1 + assign \dec2_cur_msr$next \core_msr__data_o + end + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \dec2_cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \dec2_cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \cur_msr \cur_msr$next + update \dec2_cur_msr \dec2_cur_msr$next end - attribute \src "simple/issuer.py:216" - wire width 32 $85 + attribute \src "simple/issuer.py:257" + wire width 32 $103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $86 + wire width 7 $104 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $87 + cell $mul $105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 - connect \A \cur_pc [2] + connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $86 + connect \Y $104 end - attribute \src "simple/issuer.py:216" - cell $shift $88 + attribute \src "simple/issuer.py:257" + cell $shift $106 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 32 connect \A \imem_f_instr_o - connect \B $86 - connect \Y $85 + connect \B $104 + connect \Y $103 end - process $group_93 + process $group_84 assign \dec2_raw_opcode_in 32'00000000000000000000000000000000 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case - assign \dec2_raw_opcode_in $85 + assign \dec2_raw_opcode_in $103 end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - process $group_94 - assign \dec2_dec2_pc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \dec2_dec2_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire width 1 \core_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire width 1 \core_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec$next + process $group_85 + assign \core_core_pc$next \core_core_pc + assign \core_msr$next \core_msr + assign \core_eint$next \core_eint + assign \core_dec$next \core_dec + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case - assign { \dec2_dec2_msr \dec2_dec2_pc } { \cur_msr \cur_pc } + assign { \core_dec$next \core_eint$next \core_msr$next \core_core_pc$next } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \core_core_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_eint$next 1'0 + assign \core_dec$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end sync init + update \core_core_pc 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_eint 1'0 + update \core_dec 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \core_core_pc \core_core_pc$next + update \core_msr \core_msr$next + update \core_eint \core_eint$next + update \core_dec \core_dec$next end - attribute \src "simple/issuer.py:130" + attribute \src "simple/issuer.py:166" wire width 32 \ilatch - attribute \src "simple/issuer.py:130" + attribute \src "simple/issuer.py:166" wire width 32 \ilatch$next - attribute \src "simple/issuer.py:216" - wire width 32 $89 + attribute \src "simple/issuer.py:257" + wire width 32 $107 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $90 + wire width 7 $108 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $91 + cell $mul $109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 - connect \A \cur_pc [2] + connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $90 + connect \Y $108 end - attribute \src "simple/issuer.py:216" - cell $shift $92 + attribute \src "simple/issuer.py:257" + cell $shift $110 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 32 connect \A \imem_f_instr_o - connect \B $90 - connect \Y $89 + connect \B $108 + connect \Y $107 end - process $group_96 + process $group_89 assign \ilatch$next \ilatch - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:206" + attribute \src "simple/issuer.py:247" case 1'1 - attribute \src "simple/issuer.py:210" + attribute \src "simple/issuer.py:251" case - assign \ilatch$next $89 + assign \ilatch$next $107 end - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end @@ -167297,92 +277628,92 @@ module \test_issuer sync posedge \clk update \ilatch \ilatch$next end - attribute \src "simple/issuer.py:234" - wire width 1 $93 - attribute \src "simple/issuer.py:234" - cell $ne $94 + attribute \src "simple/issuer.py:276" + wire width 1 $111 + attribute \src "simple/issuer.py:276" + cell $ne $112 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \core_insn_type + connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $93 + connect \Y $111 end - process $group_97 + process $group_90 assign \core_ivalid_i 1'0 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 assign \core_ivalid_i 1'1 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 - attribute \src "simple/issuer.py:234" - switch { $93 } - attribute \src "simple/issuer.py:234" + attribute \src "simple/issuer.py:276" + switch { $111 } + attribute \src "simple/issuer.py:276" case 1'1 assign \core_ivalid_i 1'1 end end sync init end - process $group_98 + process $group_91 assign \core_issue_i 1'0 - attribute \src "simple/issuer.py:178" + attribute \src "simple/issuer.py:214" switch \fsm_state - attribute \src "simple/issuer.py:181" + attribute \src "simple/issuer.py:217" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:203" + attribute \src "simple/issuer.py:242" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:268" attribute \nmigen.decoding "INSN_START/2" case 2'10 assign \core_issue_i 1'1 - attribute \src "simple/issuer.py:233" + attribute \src "simple/issuer.py:275" attribute \nmigen.decoding "INSN_ACTIVE/3" case 2'11 end sync init end - process $group_99 + process $group_92 assign \core_dmi__addr 5'00000 - attribute \src "simple/issuer.py:250" - switch { \dbg_dbg_gpr_req } - attribute \src "simple/issuer.py:250" + attribute \src "simple/issuer.py:294" + switch { \dbg_d_gpr_req } + attribute \src "simple/issuer.py:294" case 1'1 - assign \core_dmi__addr \dbg_dbg_gpr_addr [4:0] + assign \core_dmi__addr \dbg_d_gpr_addr [4:0] end sync init end - process $group_100 + process $group_93 assign \core_dmi__ren 1'0 - attribute \src "simple/issuer.py:250" - switch { \dbg_dbg_gpr_req } - attribute \src "simple/issuer.py:250" + attribute \src "simple/issuer.py:294" + switch { \dbg_d_gpr_req } + attribute \src "simple/issuer.py:294" case 1'1 assign \core_dmi__ren 1'1 end sync init end - attribute \src "simple/issuer.py:258" + attribute \src "simple/issuer.py:302" wire width 1 \d_reg_delay - attribute \src "simple/issuer.py:258" + attribute \src "simple/issuer.py:302" wire width 1 \d_reg_delay$next - process $group_101 + process $group_94 assign \d_reg_delay$next \d_reg_delay - assign \d_reg_delay$next \dbg_dbg_gpr_req + assign \d_reg_delay$next \dbg_d_gpr_req attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -167393,24 +277724,383 @@ module \test_issuer sync posedge \clk update \d_reg_delay \d_reg_delay$next end - process $group_102 - assign \dbg_dbg_gpr_data 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:260" + process $group_95 + assign \dbg_d_gpr_data 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:304" switch { \d_reg_delay } - attribute \src "simple/issuer.py:260" + attribute \src "simple/issuer.py:304" case 1'1 - assign \dbg_dbg_gpr_data \core_dmi__data_o + assign \dbg_d_gpr_data \core_dmi__data_o end sync init end - process $group_103 - assign \dbg_dbg_gpr_ack 1'0 - attribute \src "simple/issuer.py:260" + process $group_96 + assign \dbg_d_gpr_ack 1'0 + attribute \src "simple/issuer.py:304" switch { \d_reg_delay } - attribute \src "simple/issuer.py:260" + attribute \src "simple/issuer.py:304" + case 1'1 + assign \dbg_d_gpr_ack 1'1 + end + sync init + end + process $group_97 + assign \core_full_rd2__ren 8'00000000 + attribute \src "simple/issuer.py:310" + switch { \dbg_d_cr_req } + attribute \src "simple/issuer.py:310" + case 1'1 + assign \core_full_rd2__ren 8'11111111 + end + sync init + end + attribute \src "simple/issuer.py:312" + wire width 1 \d_cr_delay + attribute \src "simple/issuer.py:312" + wire width 1 \d_cr_delay$next + process $group_98 + assign \d_cr_delay$next \d_cr_delay + assign \d_cr_delay$next \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \d_cr_delay$next 1'0 + end + sync init + update \d_cr_delay 1'0 + sync posedge \clk + update \d_cr_delay \d_cr_delay$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \core_full_rd2__data_o + connect \Y $113 + end + process $group_99 + assign \dbg_d_cr_data 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:314" + switch { \d_cr_delay } + attribute \src "simple/issuer.py:314" + case 1'1 + assign \dbg_d_cr_data $113 + end + sync init + end + process $group_100 + assign \dbg_d_cr_ack 1'0 + attribute \src "simple/issuer.py:314" + switch { \d_cr_delay } + attribute \src "simple/issuer.py:314" + case 1'1 + assign \dbg_d_cr_ack 1'1 + end + sync init + end + process $group_101 + assign \core_full_rd__ren 3'000 + attribute \src "simple/issuer.py:320" + switch { \dbg_d_xer_req } + attribute \src "simple/issuer.py:320" + case 1'1 + assign \core_full_rd__ren 3'111 + end + sync init + end + attribute \src "simple/issuer.py:322" + wire width 1 \d_xer_delay + attribute \src "simple/issuer.py:322" + wire width 1 \d_xer_delay$next + process $group_102 + assign \d_xer_delay$next \d_xer_delay + assign \d_xer_delay$next \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \d_xer_delay$next 1'0 + end + sync init + update \d_xer_delay 1'0 + sync posedge \clk + update \d_xer_delay \d_xer_delay$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 $115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \core_full_rd__data_o + connect \Y $115 + end + process $group_103 + assign \dbg_d_xer_data 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:324" + switch { \d_xer_delay } + attribute \src "simple/issuer.py:324" case 1'1 - assign \dbg_dbg_gpr_ack 1'1 + assign \dbg_d_xer_data $115 + end + sync init + end + process $group_104 + assign \dbg_d_xer_ack 1'0 + attribute \src "simple/issuer.py:324" + switch { \d_xer_delay } + attribute \src "simple/issuer.py:324" + case 1'1 + assign \dbg_d_xer_ack 1'1 + end + sync init + end + attribute \src "simple/issuer.py:350" + wire width 2 \fsm_state$117 + attribute \src "simple/issuer.py:350" + wire width 2 \fsm_state$117$next + process $group_105 + assign \core_issue__addr 3'000 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + assign \core_issue__addr 3'110 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + assign \core_issue__addr 3'111 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + end + sync init + end + process $group_106 + assign \core_issue__ren 1'0 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + assign \core_issue__ren 1'1 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + assign \core_issue__ren 1'1 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + end + sync init + end + process $group_107 + assign \fsm_state$117$next \fsm_state$117 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + assign \fsm_state$117$next 2'01 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + assign \fsm_state$117$next 2'10 + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + assign \fsm_state$117$next 2'11 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + assign \fsm_state$117$next 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \fsm_state$117$next 2'00 + end + sync init + update \fsm_state$117 2'00 + sync posedge \clk + update \fsm_state$117 \fsm_state$117$next + end + attribute \src "simple/issuer.py:360" + wire width 64 \new_dec + attribute \src "simple/issuer.py:362" + wire width 65 $118 + attribute \src "simple/issuer.py:362" + wire width 65 $119 + attribute \src "simple/issuer.py:362" + cell $sub $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $119 + end + connect $118 $119 + process $group_108 + assign \new_dec 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + assign \new_dec $118 [63:0] + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + end + sync init + end + process $group_109 + assign \core_issue__addr$4 3'000 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + assign \core_issue__addr$4 3'110 + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + assign \core_issue__addr$4 3'111 + end + sync init + end + process $group_110 + assign \core_issue__wen 1'0 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + assign \core_issue__wen 1'1 + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + assign \core_issue__wen 1'1 + end + sync init + end + attribute \src "simple/issuer.py:377" + wire width 64 \new_tb + process $group_111 + assign \core_issue__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + assign \core_issue__data_i \new_dec + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + assign \core_issue__data_i \new_tb + end + sync init + end + process $group_112 + assign \dec2_cur_dec$next \dec2_cur_dec + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + assign \dec2_cur_dec$next \new_dec + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \dec2_cur_dec$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \dec2_cur_dec 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \dec2_cur_dec \dec2_cur_dec$next + end + attribute \src "simple/issuer.py:378" + wire width 65 $121 + attribute \src "simple/issuer.py:378" + wire width 65 $122 + attribute \src "simple/issuer.py:378" + cell $add $123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $122 + end + connect $121 $122 + process $group_113 + assign \new_tb 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "simple/issuer.py:353" + attribute \nmigen.decoding "DEC_READ/0" + case 2'00 + attribute \src "simple/issuer.py:359" + attribute \nmigen.decoding "DEC_WRITE/1" + case 2'01 + attribute \src "simple/issuer.py:370" + attribute \nmigen.decoding "TB_READ/2" + case 2'10 + attribute \src "simple/issuer.py:376" + attribute \nmigen.decoding "TB_WRITE/3" + case 2'11 + assign \new_tb $121 [63:0] end sync init end + connect \dec2_cur_eint 1'0 end