From: lkcl <lkcl@web>
Date: Sun, 9 Oct 2022 19:28:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~136
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a1851029c537e43950568dc9819b1efc05b91a9a;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls002/discussion.mdwn b/openpower/sv/rfc/ls002/discussion.mdwn
index 64a9f3cbe..1087729ed 100644
--- a/openpower/sv/rfc/ls002/discussion.mdwn
+++ b/openpower/sv/rfc/ls002/discussion.mdwn
@@ -4,14 +4,20 @@
 
 # Questions (09 oct 2022)
 
+**
 1. What is "BF16"?  It seems not to be mentioned in the architecture spec.
    The architecture spec (VSX chapter) defines two 16-bit binary FP formats.
    Judging by the way the RFC uses "BF16", I think it means what the VSX
    chapter calls "bfloat16", which has the exponent in the same bits as
    single format.  This should be clarified, and the corresponding format
    will need to be defined in Section 4.3.1 (Data Format).
+**
+
+**
 2. For fishmv, what happens if the value supplied in the FPR is not
    representable in single format?
+**
+
 3. The first clause of the verbal description of fishmv seems to assume
    that the contents of the specified register were produced by fmvis.
    Is there any other use of fishmv?  If yes, the verbal description should