From: lkcl <lkcl@web>
Date: Thu, 2 Jun 2022 16:40:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2010
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a19dc232cf7af49a1393b4d83b6c5d70b7adbbab;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index fe7cc9509..ae0459ed4 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -30,13 +30,18 @@ Other "modifications" such as saturation or Data-dependent Fail-First
 likewise are post-augmentation or post-analysis, and do not actually
 fundamentally change an add operation into a subtract for example.
 
-*(An experiment was attempted to modify LD-immediate instructions
+An experiment was attempted to modify LD-immediate instructions
 to include a
 third RC register i.e. reinterpret the normal
 v3.0 32-bit instruction as a
 different encoding if SVP64-prefixed: it did not go well.
 The complexity that resulted
-in the decode phase was too great)*
+in the decode phase was too great. The lesson was learned, the
+hard way: it is infinitely preferable to add a 32-bit Scalar Load-with-Shift
+instruction *first*, which then inherently becomes Vectorised.
+Perhaps a future Power ISA spec will have this Load-with-Shift instruction:
+both ARM and x86 have it, because it saves greatly on instruction count in
+hot-loops. 
 
 # Instruction Groups